drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly separated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/time.h>
  27 #include <linux/sched.h>
  28 #include <linux/delay.h>
  29 #include <linux/errno.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/i2c-pxa.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/err.h>
  36 #include <linux/clk.h>
  37 #include <linux/slab.h>
  38 #include <linux/io.h>
  39 #include <linux/i2c/pxa-i2c.h>
  40
  41 #include <asm/irq.h>
  42
  43 struct pxa_reg_layout {
  44         u32 ibmr;
  45         u32 idbr;
  46         u32 icr;
  47         u32 isr;
  48         u32 isar;
  49         u32 ilcr;
  50         u32 iwcr;
  51 };
  52
  53 enum pxa_i2c_types {
  54         REGS_PXA2XX,
  55         REGS_PXA3XX,
  56         REGS_CE4100,
  57         REGS_PXA910,
  58 };
  59
  60 /*
  61  * I2C registers definitions
  62  */
  63 static struct pxa_reg_layout pxa_reg_layout[] = {
  64         [REGS_PXA2XX] = {
  65                 .ibmr = 0x00,
  66                 .idbr = 0x08,
  67                 .icr =  0x10,
  68                 .isr =  0x18,
  69                 .isar = 0x20,
  70         },
  71         [REGS_PXA3XX] = {
  72                 .ibmr = 0x00,
  73                 .idbr = 0x04,
  74                 .icr =  0x08,
  75                 .isr =  0x0c,
  76                 .isar = 0x10,
  77         },
  78         [REGS_CE4100] = {
  79                 .ibmr = 0x14,
  80                 .idbr = 0x0c,
  81                 .icr =  0x00,
  82                 .isr =  0x04,
  83                 /* no isar register */
  84         },
  85         [REGS_PXA910] = {
  86                 .ibmr = 0x00,
  87                 .idbr = 0x08,
  88                 .icr =  0x10,
  89                 .isr =  0x18,
  90                 .isar = 0x20,
  91                 .ilcr = 0x28,
  92                 .iwcr = 0x30,
  93         },
  94 };
  95
  96 static const struct platform_device_id i2c_pxa_id_table[] = {
  97         { "pxa2xx-i2c",         REGS_PXA2XX },
  98         { "pxa3xx-pwri2c",      REGS_PXA3XX },
  99         { "ce4100-i2c",         REGS_CE4100 },
 100         { "pxa910-i2c",         REGS_PXA910 },
 101         { },
 102 };
 103 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
 104
 105 /*
 106  * I2C bit definitions
 107  */
 108
 109 #define ICR_START       (1 << 0)           /* start bit */
 110 #define ICR_STOP        (1 << 1)           /* stop bit */
 111 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
 112 #define ICR_TB          (1 << 3)           /* transfer byte bit */
 113 #define ICR_MA          (1 << 4)           /* master abort */
 114 #define ICR_SCLE        (1 << 5)           /* master clock enable */
 115 #define ICR_IUE         (1 << 6)           /* unit enable */
 116 #define ICR_GCD         (1 << 7)           /* general call disable */
 117 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
 118 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
 119 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
 120 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
 121 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
 122 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
 123 #define ICR_UR          (1 << 14)          /* unit reset */
 124 #define ICR_FM          (1 << 15)          /* fast mode */
 125 #define ICR_HS          (1 << 16)          /* High Speed mode */
 126 #define ICR_GPIOEN      (1 << 19)          /* enable GPIO mode for SCL in HS */
 127
 128 #define ISR_RWM         (1 << 0)           /* read/write mode */
 129 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
 130 #define ISR_UB          (1 << 2)           /* unit busy */
 131 #define ISR_IBB         (1 << 3)           /* bus busy */
 132 #define ISR_SSD         (1 << 4)           /* slave stop detected */
 133 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
 134 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
 135 #define ISR_IRF         (1 << 7)           /* rx buffer full */
 136 #define ISR_GCAD        (1 << 8)           /* general call address detected */
 137 #define ISR_SAD         (1 << 9)           /* slave address detected */
 138 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
 139
 140 /* bit field shift & mask */
 141 #define ILCR_SLV_SHIFT          0
 142 #define ILCR_SLV_MASK           (0x1FF << ILCR_SLV_SHIFT)
 143 #define ILCR_FLV_SHIFT          9
 144 #define ILCR_FLV_MASK           (0x1FF << ILCR_FLV_SHIFT)
 145 #define ILCR_HLVL_SHIFT         18
 146 #define ILCR_HLVL_MASK          (0x1FF << ILCR_HLVL_SHIFT)
 147 #define ILCR_HLVH_SHIFT         27
 148 #define ILCR_HLVH_MASK          (0x1F << ILCR_HLVH_SHIFT)
 149
 150 #define IWCR_CNT_SHIFT          0
 151 #define IWCR_CNT_MASK           (0x1F << IWCR_CNT_SHIFT)
 152 #define IWCR_HS_CNT1_SHIFT      5
 153 #define IWCR_HS_CNT1_MASK       (0x1F << IWCR_HS_CNT1_SHIFT)
 154 #define IWCR_HS_CNT2_SHIFT      10
 155 #define IWCR_HS_CNT2_MASK       (0x1F << IWCR_HS_CNT2_SHIFT)
 156
 157 struct pxa_i2c {
 158         spinlock_t              lock;
 159         wait_queue_head_t       wait;
 160         struct i2c_msg          *msg;
 161         unsigned int            msg_num;
 162         unsigned int            msg_idx;
 163         unsigned int            msg_ptr;
 164         unsigned int            slave_addr;
 165         unsigned int            req_slave_addr;
 166
 167         struct i2c_adapter      adap;
 168         struct clk              *clk;
 169 #ifdef CONFIG_I2C_PXA_SLAVE
 170         struct i2c_slave_client *slave;
 171 #endif
 172
 173         unsigned int            irqlogidx;
 174         u32                     isrlog[32];
 175         u32                     icrlog[32];
 176
 177         void __iomem            *reg_base;
 178         void __iomem            *reg_ibmr;
 179         void __iomem            *reg_idbr;
 180         void __iomem            *reg_icr;
 181         void __iomem            *reg_isr;
 182         void __iomem            *reg_isar;
 183         void __iomem            *reg_ilcr;
 184         void __iomem            *reg_iwcr;
 185
 186         unsigned long           iobase;
 187         unsigned long           iosize;
 188
 189         int                     irq;
 190         unsigned int            use_pio :1;
 191         unsigned int            fast_mode :1;
 192         unsigned int            high_mode:1;
 193         unsigned char           master_code;
 194         unsigned long           rate;
 195         bool                    highmode_enter;
 196 };
 197
 198 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
 199 #define _IDBR(i2c)      ((i2c)->reg_idbr)
 200 #define _ICR(i2c)       ((i2c)->reg_icr)
 201 #define _ISR(i2c)       ((i2c)->reg_isr)
 202 #define _ISAR(i2c)      ((i2c)->reg_isar)
 203 #define _ILCR(i2c)      ((i2c)->reg_ilcr)
 204 #define _IWCR(i2c)      ((i2c)->reg_iwcr)
 205
 206 /*
 207  * I2C Slave mode address
 208  */
 209 #define I2C_PXA_SLAVE_ADDR      0x1
 210
 211 #ifdef DEBUG
 212
 213 struct bits {
 214         u32     mask;
 215         const char *set;
 216         const char *unset;
 217 };
 218 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 219
 220 static inline void
 221 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 222 {
 223         printk("%s %08x: ", prefix, val);
 224         while (num--) {
 225                 const char *str = val & bits->mask ? bits->set : bits->unset;
 226                 if (str)
 227                         printk("%s ", str);
 228                 bits++;
 229         }
 230 }
 231
 232 static const struct bits isr_bits[] = {
 233         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 234         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 235         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 236         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 237         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 238         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 239         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 240         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 241         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 242         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 243         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 244 };
 245
 246 static void decode_ISR(unsigned int val)
 247 {
 248         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 249         printk("\n");
 250 }
 251
 252 static const struct bits icr_bits[] = {
 253         PXA_BIT(ICR_START,  "START",    NULL),
 254         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 255         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 256         PXA_BIT(ICR_TB,     "TB",       NULL),
 257         PXA_BIT(ICR_MA,     "MA",       NULL),
 258         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 259         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 260         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 261         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 262         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 263         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 264         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 265         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 266         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 267         PXA_BIT(ICR_UR,     "UR",               "ur"),
 268 };
 269
 270 #ifdef CONFIG_I2C_PXA_SLAVE
 271 static void decode_ICR(unsigned int val)
 272 {
 273         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 274         printk("\n");
 275 }
 276 #endif
 277
 278 static unsigned int i2c_debug = DEBUG;
 279
 280 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 281 {
 282         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 283                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 284 }
 285
 286 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 287
 288 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 289 {
 290         unsigned int i;
 291         struct device *dev = &i2c->adap.dev;
 292
 293         dev_err(dev, "slave_0x%x error: %s\n",
 294                 i2c->req_slave_addr >> 1, why);
 295         dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
 296                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 297         dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
 298                 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
 299                 readl(_ISR(i2c)));
 300         dev_err(dev, "log:");
 301         for (i = 0; i < i2c->irqlogidx; i++)
 302                 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
 303         pr_cont("\n");
 304 }
 305
 306 #else /* ifdef DEBUG */
 307
 308 #define i2c_debug       0
 309
 310 #define show_state(i2c) do { } while (0)
 311 #define decode_ISR(val) do { } while (0)
 312 #define decode_ICR(val) do { } while (0)
 313 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 314
 315 #endif /* ifdef DEBUG / else */
 316
 317 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 318 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 319
 320 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 321 {
 322         return !(readl(_ICR(i2c)) & ICR_SCLE);
 323 }
 324
 325 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 326 {
 327         int i = 250;
 328
 329         if (i2c_pxa_is_slavemode(i2c)) {
 330                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 331                 return;
 332         }
 333
 334         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 335                 unsigned long icr = readl(_ICR(i2c));
 336
 337                 icr &= ~ICR_START;
 338                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 339
 340                 writel(icr, _ICR(i2c));
 341
 342                 show_state(i2c);
 343
 344                 mdelay(1);
 345                 i --;
 346         }
 347
 348         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 349                _ICR(i2c));
 350 }
 351
 352 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 353 {
 354         int timeout = DEF_TIMEOUT;
 355
 356         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 357                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 358                         timeout += 4;
 359
 360                 msleep(2);
 361                 show_state(i2c);
 362         }
 363
 364         if (timeout < 0)
 365                 show_state(i2c);
 366
 367         return timeout < 0 ? I2C_RETRY : 0;
 368 }
 369
 370 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 371 {
 372         unsigned long timeout = jiffies + HZ*4;
 373
 374         while (time_before(jiffies, timeout)) {
 375                 if (i2c_debug > 1)
 376                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 377                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 378
 379                 if (readl(_ISR(i2c)) & ISR_SAD) {
 380                         if (i2c_debug > 0)
 381                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 382                         goto out;
 383                 }
 384
 385                 /* wait for unit and bus being not busy, and we also do a
 386                  * quick check of the i2c lines themselves to ensure they've
 387                  * gone high...
 388                  */
 389                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 390                         if (i2c_debug > 0)
 391                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 392                         return 1;
 393                 }
 394
 395                 msleep(1);
 396         }
 397
 398         if (i2c_debug > 0)
 399                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 400  out:
 401         return 0;
 402 }
 403
 404 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 405 {
 406         if (i2c_debug)
 407                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 408
 409         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 410                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 411                 if (!i2c_pxa_wait_master(i2c)) {
 412                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 413                         return I2C_RETRY;
 414                 }
 415         }
 416
 417         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 418         return 0;
 419 }
 420
 421 #ifdef CONFIG_I2C_PXA_SLAVE
 422 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 423 {
 424         unsigned long timeout = jiffies + HZ*1;
 425
 426         /* wait for stop */
 427
 428         show_state(i2c);
 429
 430         while (time_before(jiffies, timeout)) {
 431                 if (i2c_debug > 1)
 432                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 433                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 434
 435                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 436                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 437                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 438                         if (i2c_debug > 1)
 439                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 440                         return 1;
 441                 }
 442
 443                 msleep(1);
 444         }
 445
 446         if (i2c_debug > 0)
 447                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 448         return 0;
 449 }
 450
 451 /*
 452  * clear the hold on the bus, and take of anything else
 453  * that has been configured
 454  */
 455 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 456 {
 457         show_state(i2c);
 458
 459         if (errcode < 0) {
 460                 udelay(100);   /* simple delay */
 461         } else {
 462                 /* we need to wait for the stop condition to end */
 463
 464                 /* if we where in stop, then clear... */
 465                 if (readl(_ICR(i2c)) & ICR_STOP) {
 466                         udelay(100);
 467                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 468                 }
 469
 470                 if (!i2c_pxa_wait_slave(i2c)) {
 471                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 472                                 __func__);
 473                         return;
 474                 }
 475         }
 476
 477         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 478         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 479
 480         if (i2c_debug) {
 481                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 482                 decode_ICR(readl(_ICR(i2c)));
 483         }
 484 }
 485 #else
 486 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 487 #endif
 488
 489 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 490 {
 491         pr_debug("Resetting I2C Controller Unit\n");
 492
 493         /* abort any transfer currently under way */
 494         i2c_pxa_abort(i2c);
 495
 496         /* reset according to 9.8 */
 497         writel(ICR_UR, _ICR(i2c));
 498         writel(I2C_ISR_INIT, _ISR(i2c));
 499         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 500
 501         if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
 502                 writel(i2c->slave_addr, _ISAR(i2c));
 503
 504         /* set control register values */
 505         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 506         writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
 507
 508 #ifdef CONFIG_I2C_PXA_SLAVE
 509         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 510         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 511 #endif
 512
 513         i2c_pxa_set_slave(i2c, 0);
 514
 515         /* enable unit */
 516         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 517         udelay(100);
 518 }
 519
 520
 521 #ifdef CONFIG_I2C_PXA_SLAVE
 522 /*
 523  * PXA I2C Slave mode
 524  */
 525
 526 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 527 {
 528         if (isr & ISR_BED) {
 529                 /* what should we do here? */
 530         } else {
 531                 int ret = 0;
 532
 533                 if (i2c->slave != NULL)
 534                         ret = i2c->slave->read(i2c->slave->data);
 535
 536                 writel(ret, _IDBR(i2c));
 537                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 538         }
 539 }
 540
 541 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 542 {
 543         unsigned int byte = readl(_IDBR(i2c));
 544
 545         if (i2c->slave != NULL)
 546                 i2c->slave->write(i2c->slave->data, byte);
 547
 548         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 549 }
 550
 551 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 552 {
 553         int timeout;
 554
 555         if (i2c_debug > 0)
 556                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 557                        (isr & ISR_RWM) ? 'r' : 't');
 558
 559         if (i2c->slave != NULL)
 560                 i2c->slave->event(i2c->slave->data,
 561                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 562
 563         /*
 564          * slave could interrupt in the middle of us generating a
 565          * start condition... if this happens, we'd better back off
 566          * and stop holding the poor thing up
 567          */
 568         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 569         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 570
 571         timeout = 0x10000;
 572
 573         while (1) {
 574                 if ((readl(_IBMR(i2c)) & 2) == 2)
 575                         break;
 576
 577                 timeout--;
 578
 579                 if (timeout <= 0) {
 580                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 581                         break;
 582                 }
 583         }
 584
 585         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 586 }
 587
 588 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 589 {
 590         if (i2c_debug > 2)
 591                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 592
 593         if (i2c->slave != NULL)
 594                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 595
 596         if (i2c_debug > 2)
 597                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 598
 599         /*
 600          * If we have a master-mode message waiting,
 601          * kick it off now that the slave has completed.
 602          */
 603         if (i2c->msg)
 604                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 605 }
 606 #else
 607 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 608 {
 609         if (isr & ISR_BED) {
 610                 /* what should we do here? */
 611         } else {
 612                 writel(0, _IDBR(i2c));
 613                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 614         }
 615 }
 616
 617 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 618 {
 619         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 620 }
 621
 622 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 623 {
 624         int timeout;
 625
 626         /*
 627          * slave could interrupt in the middle of us generating a
 628          * start condition... if this happens, we'd better back off
 629          * and stop holding the poor thing up
 630          */
 631         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 632         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 633
 634         timeout = 0x10000;
 635
 636         while (1) {
 637                 if ((readl(_IBMR(i2c)) & 2) == 2)
 638                         break;
 639
 640                 timeout--;
 641
 642                 if (timeout <= 0) {
 643                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 644                         break;
 645                 }
 646         }
 647
 648         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 649 }
 650
 651 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 652 {
 653         if (i2c->msg)
 654                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 655 }
 656 #endif
 657
 658 /*
 659  * PXA I2C Master mode
 660  */
 661
 662 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 663 {
 664         unsigned int addr = (msg->addr & 0x7f) << 1;
 665
 666         if (msg->flags & I2C_M_RD)
 667                 addr |= 1;
 668
 669         return addr;
 670 }
 671
 672 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 673 {
 674         u32 icr;
 675
 676         /*
 677          * Step 1: target slave address into IDBR
 678          */
 679         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 680         i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
 681
 682         /*
 683          * Step 2: initiate the write.
 684          */
 685         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 686         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 687 }
 688
 689 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 690 {
 691         u32 icr;
 692
 693         /* Clear the START, STOP, ACK, TB and MA flags */
 694         icr = readl(_ICR(i2c));
 695         icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
 696         writel(icr, _ICR(i2c));
 697 }
 698
 699 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 700 {
 701         /* make timeout the same as for interrupt based functions */
 702         long timeout = 2 * DEF_TIMEOUT;
 703
 704         /*
 705          * Wait for the bus to become free.
 706          */
 707         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 708                 udelay(1000);
 709                 show_state(i2c);
 710         }
 711
 712         if (timeout < 0) {
 713                 show_state(i2c);
 714                 dev_err(&i2c->adap.dev,
 715                         "i2c_pxa: timeout waiting for bus free\n");
 716                 return I2C_RETRY;
 717         }
 718
 719         /*
 720          * Set master mode.
 721          */
 722         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 723
 724         return 0;
 725 }
 726
 727 /*
 728  * PXA I2C send master code
 729  * 1. Load master code to IDBR and send it.
 730  *    Note for HS mode, set ICR [GPIOEN].
 731  * 2. Wait until win arbitration.
 732  */
 733 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
 734 {
 735         u32 icr;
 736         long timeout;
 737
 738         spin_lock_irq(&i2c->lock);
 739         i2c->highmode_enter = true;
 740         writel(i2c->master_code, _IDBR(i2c));
 741
 742         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 743         icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
 744         writel(icr, _ICR(i2c));
 745
 746         spin_unlock_irq(&i2c->lock);
 747         timeout = wait_event_timeout(i2c->wait,
 748                         i2c->highmode_enter == false, HZ * 1);
 749
 750         i2c->highmode_enter = false;
 751
 752         return (timeout == 0) ? I2C_RETRY : 0;
 753 }
 754
 755 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 756                                struct i2c_msg *msg, int num)
 757 {
 758         unsigned long timeout = 500000; /* 5 seconds */
 759         int ret = 0;
 760
 761         ret = i2c_pxa_pio_set_master(i2c);
 762         if (ret)
 763                 goto out;
 764
 765         i2c->msg = msg;
 766         i2c->msg_num = num;
 767         i2c->msg_idx = 0;
 768         i2c->msg_ptr = 0;
 769         i2c->irqlogidx = 0;
 770
 771         i2c_pxa_start_message(i2c);
 772
 773         while (i2c->msg_num > 0 && --timeout) {
 774                 i2c_pxa_handler(0, i2c);
 775                 udelay(10);
 776         }
 777
 778         i2c_pxa_stop_message(i2c);
 779
 780         /*
 781          * We place the return code in i2c->msg_idx.
 782          */
 783         ret = i2c->msg_idx;
 784
 785 out:
 786         if (timeout == 0) {
 787                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 788                 ret = I2C_RETRY;
 789         }
 790
 791         return ret;
 792 }
 793
 794 /*
 795  * We are protected by the adapter bus mutex.
 796  */
 797 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 798 {
 799         long timeout;
 800         int ret;
 801
 802         /*
 803          * Wait for the bus to become free.
 804          */
 805         ret = i2c_pxa_wait_bus_not_busy(i2c);
 806         if (ret) {
 807                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 808                 goto out;
 809         }
 810
 811         /*
 812          * Set master mode.
 813          */
 814         ret = i2c_pxa_set_master(i2c);
 815         if (ret) {
 816                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 817                 goto out;
 818         }
 819
 820         if (i2c->high_mode) {
 821                 ret = i2c_pxa_send_mastercode(i2c);
 822                 if (ret) {
 823                         dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
 824                         goto out;
 825                         }
 826         }
 827
 828         spin_lock_irq(&i2c->lock);
 829
 830         i2c->msg = msg;
 831         i2c->msg_num = num;
 832         i2c->msg_idx = 0;
 833         i2c->msg_ptr = 0;
 834         i2c->irqlogidx = 0;
 835
 836         i2c_pxa_start_message(i2c);
 837
 838         spin_unlock_irq(&i2c->lock);
 839
 840         /*
 841          * The rest of the processing occurs in the interrupt handler.
 842          */
 843         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 844         i2c_pxa_stop_message(i2c);
 845
 846         /*
 847          * We place the return code in i2c->msg_idx.
 848          */
 849         ret = i2c->msg_idx;
 850
 851         if (!timeout && i2c->msg_num) {
 852                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 853                 ret = I2C_RETRY;
 854         }
 855
 856  out:
 857         return ret;
 858 }
 859
 860 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 861                             struct i2c_msg msgs[], int num)
 862 {
 863         struct pxa_i2c *i2c = adap->algo_data;
 864         int ret, i;
 865
 866         /* If the I2C controller is disabled we need to reset it
 867           (probably due to a suspend/resume destroying state). We do
 868           this here as we can then avoid worrying about resuming the
 869           controller before its users. */
 870         if (!(readl(_ICR(i2c)) & ICR_IUE))
 871                 i2c_pxa_reset(i2c);
 872
 873         for (i = adap->retries; i >= 0; i--) {
 874                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 875                 if (ret != I2C_RETRY)
 876                         goto out;
 877
 878                 if (i2c_debug)
 879                         dev_dbg(&adap->dev, "Retrying transmission\n");
 880                 udelay(100);
 881         }
 882         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 883         ret = -EREMOTEIO;
 884  out:
 885         i2c_pxa_set_slave(i2c, ret);
 886         return ret;
 887 }
 888
 889 /*
 890  * i2c_pxa_master_complete - complete the message and wake up.
 891  */
 892 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 893 {
 894         i2c->msg_ptr = 0;
 895         i2c->msg = NULL;
 896         i2c->msg_idx ++;
 897         i2c->msg_num = 0;
 898         if (ret)
 899                 i2c->msg_idx = ret;
 900         if (!i2c->use_pio)
 901                 wake_up(&i2c->wait);
 902 }
 903
 904 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 905 {
 906         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 907
 908  again:
 909         /*
 910          * If ISR_ALD is set, we lost arbitration.
 911          */
 912         if (isr & ISR_ALD) {
 913                 /*
 914                  * Do we need to do anything here?  The PXA docs
 915                  * are vague about what happens.
 916                  */
 917                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 918
 919                 /*
 920                  * We ignore this error.  We seem to see spurious ALDs
 921                  * for seemingly no reason.  If we handle them as I think
 922                  * they should, we end up causing an I2C error, which
 923                  * is painful for some systems.
 924                  */
 925                 return; /* ignore */
 926         }
 927
 928         if ((isr & ISR_BED) &&
 929                 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
 930                         (isr & ISR_ACKNAK)))) {
 931                 int ret = BUS_ERROR;
 932
 933                 /*
 934                  * I2C bus error - either the device NAK'd us, or
 935                  * something more serious happened.  If we were NAK'd
 936                  * on the initial address phase, we can retry.
 937                  */
 938                 if (isr & ISR_ACKNAK) {
 939                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 940                                 ret = I2C_RETRY;
 941                         else
 942                                 ret = XFER_NAKED;
 943                 }
 944                 i2c_pxa_master_complete(i2c, ret);
 945         } else if (isr & ISR_RWM) {
 946                 /*
 947                  * Read mode.  We have just sent the address byte, and
 948                  * now we must initiate the transfer.
 949                  */
 950                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 951                     i2c->msg_idx == i2c->msg_num - 1)
 952                         icr |= ICR_STOP | ICR_ACKNAK;
 953
 954                 icr |= ICR_ALDIE | ICR_TB;
 955         } else if (i2c->msg_ptr < i2c->msg->len) {
 956                 /*
 957                  * Write mode.  Write the next data byte.
 958                  */
 959                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 960
 961                 icr |= ICR_ALDIE | ICR_TB;
 962
 963                 /*
 964                  * If this is the last byte of the last message or last byte
 965                  * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
 966                  */
 967                 if ((i2c->msg_ptr == i2c->msg->len) &&
 968                         ((i2c->msg->flags & I2C_M_STOP) ||
 969                         (i2c->msg_idx == i2c->msg_num - 1)))
 970                                 icr |= ICR_STOP;
 971
 972         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 973                 /*
 974                  * Next segment of the message.
 975                  */
 976                 i2c->msg_ptr = 0;
 977                 i2c->msg_idx ++;
 978                 i2c->msg++;
 979
 980                 /*
 981                  * If we aren't doing a repeated start and address,
 982                  * go back and try to send the next byte.  Note that
 983                  * we do not support switching the R/W direction here.
 984                  */
 985                 if (i2c->msg->flags & I2C_M_NOSTART)
 986                         goto again;
 987
 988                 /*
 989                  * Write the next address.
 990                  */
 991                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 992                 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
 993
 994                 /*
 995                  * And trigger a repeated start, and send the byte.
 996                  */
 997                 icr &= ~ICR_ALDIE;
 998                 icr |= ICR_START | ICR_TB;
 999         } else {
1000                 if (i2c->msg->len == 0) {
1001                         /*
1002                          * Device probes have a message length of zero
1003                          * and need the bus to be reset before it can
1004                          * be used again.
1005                          */
1006                         i2c_pxa_reset(i2c);
1007                 }
1008                 i2c_pxa_master_complete(i2c, 0);
1009         }
1010
1011         i2c->icrlog[i2c->irqlogidx-1] = icr;
1012
1013         writel(icr, _ICR(i2c));
1014         show_state(i2c);
1015 }
1016
1017 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
1018 {
1019         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
1020
1021         /*
1022          * Read the byte.
1023          */
1024         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
1025
1026         if (i2c->msg_ptr < i2c->msg->len) {
1027                 /*
1028                  * If this is the last byte of the last
1029                  * message, send a STOP.
1030                  */
1031                 if (i2c->msg_ptr == i2c->msg->len - 1)
1032                         icr |= ICR_STOP | ICR_ACKNAK;
1033
1034                 icr |= ICR_ALDIE | ICR_TB;
1035         } else {
1036                 i2c_pxa_master_complete(i2c, 0);
1037         }
1038
1039         i2c->icrlog[i2c->irqlogidx-1] = icr;
1040
1041         writel(icr, _ICR(i2c));
1042 }
1043
1044 #define VALID_INT_SOURCE        (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1045                                 ISR_SAD | ISR_BED)
1046 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1047 {
1048         struct pxa_i2c *i2c = dev_id;
1049         u32 isr = readl(_ISR(i2c));
1050
1051         if (!(isr & VALID_INT_SOURCE))
1052                 return IRQ_NONE;
1053
1054         if (i2c_debug > 2 && 0) {
1055                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1056                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1057                 decode_ISR(isr);
1058         }
1059
1060         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1061                 i2c->isrlog[i2c->irqlogidx++] = isr;
1062
1063         show_state(i2c);
1064
1065         /*
1066          * Always clear all pending IRQs.
1067          */
1068         writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1069
1070         if (isr & ISR_SAD)
1071                 i2c_pxa_slave_start(i2c, isr);
1072         if (isr & ISR_SSD)
1073                 i2c_pxa_slave_stop(i2c);
1074
1075         if (i2c_pxa_is_slavemode(i2c)) {
1076                 if (isr & ISR_ITE)
1077                         i2c_pxa_slave_txempty(i2c, isr);
1078                 if (isr & ISR_IRF)
1079                         i2c_pxa_slave_rxfull(i2c, isr);
1080         } else if (i2c->msg && (!i2c->highmode_enter)) {
1081                 if (isr & ISR_ITE)
1082                         i2c_pxa_irq_txempty(i2c, isr);
1083                 if (isr & ISR_IRF)
1084                         i2c_pxa_irq_rxfull(i2c, isr);
1085         } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1086                 i2c->highmode_enter = false;
1087                 wake_up(&i2c->wait);
1088         } else {
1089                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1090         }
1091
1092         return IRQ_HANDLED;
1093 }
1094
1095
1096 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1097 {
1098         struct pxa_i2c *i2c = adap->algo_data;
1099         int ret, i;
1100
1101         for (i = adap->retries; i >= 0; i--) {
1102                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1103                 if (ret != I2C_RETRY)
1104                         goto out;
1105
1106                 if (i2c_debug)
1107                         dev_dbg(&adap->dev, "Retrying transmission\n");
1108                 udelay(100);
1109         }
1110         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1111         ret = -EREMOTEIO;
1112  out:
1113         i2c_pxa_set_slave(i2c, ret);
1114         return ret;
1115 }
1116
1117 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1118 {
1119         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1120                 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1121 }
1122
1123 static const struct i2c_algorithm i2c_pxa_algorithm = {
1124         .master_xfer    = i2c_pxa_xfer,
1125         .functionality  = i2c_pxa_functionality,
1126 };
1127
1128 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1129         .master_xfer    = i2c_pxa_pio_xfer,
1130         .functionality  = i2c_pxa_functionality,
1131 };
1132
1133 static const struct of_device_id i2c_pxa_dt_ids[] = {
1134         { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1135         { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1136         { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
1137         {}
1138 };
1139 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1140
1141 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1142                             enum pxa_i2c_types *i2c_types)
1143 {
1144         struct device_node *np = pdev->dev.of_node;
1145         const struct of_device_id *of_id =
1146                         of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1147
1148         if (!of_id)
1149                 return 1;
1150
1151         /* For device tree we always use the dynamic or alias-assigned ID */
1152         i2c->adap.nr = -1;
1153
1154         if (of_get_property(np, "mrvl,i2c-polling", NULL))
1155                 i2c->use_pio = 1;
1156         if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1157                 i2c->fast_mode = 1;
1158
1159         *i2c_types = (enum pxa_i2c_types)(of_id->data);
1160
1161         return 0;
1162 }
1163
1164 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1165                                struct pxa_i2c *i2c,
1166                                enum pxa_i2c_types *i2c_types)
1167 {
1168         struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1169         const struct platform_device_id *id = platform_get_device_id(pdev);
1170
1171         *i2c_types = id->driver_data;
1172         if (plat) {
1173                 i2c->use_pio = plat->use_pio;
1174                 i2c->fast_mode = plat->fast_mode;
1175                 i2c->high_mode = plat->high_mode;
1176                 i2c->master_code = plat->master_code;
1177                 if (!i2c->master_code)
1178                         i2c->master_code = 0xe;
1179                 i2c->rate = plat->rate;
1180         }
1181         return 0;
1182 }
1183
1184 static int i2c_pxa_probe(struct platform_device *dev)
1185 {
1186         struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1187         enum pxa_i2c_types i2c_type;
1188         struct pxa_i2c *i2c;
1189         struct resource *res = NULL;
1190         int ret, irq;
1191
1192         i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1193         if (!i2c)
1194                 return -ENOMEM;
1195
1196         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1197         i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1198         if (IS_ERR(i2c->reg_base))
1199                 return PTR_ERR(i2c->reg_base);
1200
1201         irq = platform_get_irq(dev, 0);
1202         if (irq < 0) {
1203                 dev_err(&dev->dev, "no irq resource: %d\n", irq);
1204                 return irq;
1205         }
1206
1207         /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1208         i2c->adap.nr = dev->id;
1209
1210         ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1211         if (ret > 0)
1212                 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1213         if (ret < 0)
1214                 return ret;
1215
1216         i2c->adap.owner   = THIS_MODULE;
1217         i2c->adap.retries = 5;
1218
1219         spin_lock_init(&i2c->lock);
1220         init_waitqueue_head(&i2c->wait);
1221
1222         strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1223
1224         i2c->clk = devm_clk_get(&dev->dev, NULL);
1225         if (IS_ERR(i2c->clk)) {
1226                 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1227                 return PTR_ERR(i2c->clk);
1228         }
1229
1230         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1231         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1232         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1233         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1234         if (i2c_type != REGS_CE4100)
1235                 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1236
1237         if (i2c_type == REGS_PXA910) {
1238                 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1239                 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1240         }
1241
1242         i2c->iobase = res->start;
1243         i2c->iosize = resource_size(res);
1244
1245         i2c->irq = irq;
1246
1247         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1248         i2c->highmode_enter = false;
1249
1250         if (plat) {
1251 #ifdef CONFIG_I2C_PXA_SLAVE
1252                 i2c->slave_addr = plat->slave_addr;
1253                 i2c->slave = plat->slave;
1254 #endif
1255                 i2c->adap.class = plat->class;
1256         }
1257
1258         if (i2c->high_mode) {
1259                 if (i2c->rate) {
1260                         clk_set_rate(i2c->clk, i2c->rate);
1261                         pr_info("i2c: <%s> set rate to %ld\n",
1262                                 i2c->adap.name, clk_get_rate(i2c->clk));
1263                 } else
1264                         pr_warn("i2c: <%s> clock rate not set\n",
1265                                 i2c->adap.name);
1266         }
1267
1268         clk_prepare_enable(i2c->clk);
1269
1270         if (i2c->use_pio) {
1271                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1272         } else {
1273                 i2c->adap.algo = &i2c_pxa_algorithm;
1274                 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1275                                 IRQF_SHARED | IRQF_NO_SUSPEND,
1276                                 dev_name(&dev->dev), i2c);
1277                 if (ret) {
1278                         dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1279                         goto ereqirq;
1280                 }
1281         }
1282
1283         i2c_pxa_reset(i2c);
1284
1285         i2c->adap.algo_data = i2c;
1286         i2c->adap.dev.parent = &dev->dev;
1287 #ifdef CONFIG_OF
1288         i2c->adap.dev.of_node = dev->dev.of_node;
1289 #endif
1290
1291         ret = i2c_add_numbered_adapter(&i2c->adap);
1292         if (ret < 0) {
1293                 dev_err(&dev->dev, "failed to add bus: %d\n", ret);
1294                 goto ereqirq;
1295         }
1296
1297         platform_set_drvdata(dev, i2c);
1298
1299 #ifdef CONFIG_I2C_PXA_SLAVE
1300         dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1301                 i2c->slave_addr);
1302 #else
1303         dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1304 #endif
1305         return 0;
1306
1307 ereqirq:
1308         clk_disable_unprepare(i2c->clk);
1309         return ret;
1310 }
1311
1312 static int i2c_pxa_remove(struct platform_device *dev)
1313 {
1314         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1315
1316         i2c_del_adapter(&i2c->adap);
1317
1318         clk_disable_unprepare(i2c->clk);
1319
1320         return 0;
1321 }
1322
1323 #ifdef CONFIG_PM
1324 static int i2c_pxa_suspend_noirq(struct device *dev)
1325 {
1326         struct platform_device *pdev = to_platform_device(dev);
1327         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1328
1329         clk_disable(i2c->clk);
1330
1331         return 0;
1332 }
1333
1334 static int i2c_pxa_resume_noirq(struct device *dev)
1335 {
1336         struct platform_device *pdev = to_platform_device(dev);
1337         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1338
1339         clk_enable(i2c->clk);
1340         i2c_pxa_reset(i2c);
1341
1342         return 0;
1343 }
1344
1345 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1346         .suspend_noirq = i2c_pxa_suspend_noirq,
1347         .resume_noirq = i2c_pxa_resume_noirq,
1348 };
1349
1350 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1351 #else
1352 #define I2C_PXA_DEV_PM_OPS NULL
1353 #endif
1354
1355 static struct platform_driver i2c_pxa_driver = {
1356         .probe          = i2c_pxa_probe,
1357         .remove         = i2c_pxa_remove,
1358         .driver         = {
1359                 .name   = "pxa2xx-i2c",
1360                 .pm     = I2C_PXA_DEV_PM_OPS,
1361                 .of_match_table = i2c_pxa_dt_ids,
1362         },
1363         .id_table       = i2c_pxa_id_table,
1364 };
1365
1366 static int __init i2c_adap_pxa_init(void)
1367 {
1368         return platform_driver_register(&i2c_pxa_driver);
1369 }
1370
1371 static void __exit i2c_adap_pxa_exit(void)
1372 {
1373         platform_driver_unregister(&i2c_pxa_driver);
1374 }
1375
1376 MODULE_LICENSE("GPL");
1377 MODULE_ALIAS("platform:pxa2xx-i2c");
1378
1379 subsys_initcall(i2c_adap_pxa_init);
1380 module_exit(i2c_adap_pxa_exit);