drivers/i2c/busses/i2c-pxa.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  i2c_adap_pxa.c
   4  *
   5  *  I2C adapter for the PXA I2C bus access.
   6  *
   7  *  Copyright (C) 2002 Intrinsyc Software Inc.
   8  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   9  *
  10  *  History:
  11  *    Apr 2002: Initial version [CS]
  12  *    Jun 2002: Properly separated algo/adap [FB]
  13  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  14  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  15  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  16  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  17  *    Feb 2005: Rework slave mode handling [RMK]
  18  */
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/platform_data/i2c-pxa.h>
  35 #include <linux/slab.h>
  36
  37 /* I2C register field definitions */
  38 #define IBMR_SDAS       (1 << 0)
  39 #define IBMR_SCLS       (1 << 1)
  40
  41 #define ICR_START       (1 << 0)           /* start bit */
  42 #define ICR_STOP        (1 << 1)           /* stop bit */
  43 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
  44 #define ICR_TB          (1 << 3)           /* transfer byte bit */
  45 #define ICR_MA          (1 << 4)           /* master abort */
  46 #define ICR_SCLE        (1 << 5)           /* master clock enable */
  47 #define ICR_IUE         (1 << 6)           /* unit enable */
  48 #define ICR_GCD         (1 << 7)           /* general call disable */
  49 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
  50 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
  51 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
  52 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
  53 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
  54 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
  55 #define ICR_UR          (1 << 14)          /* unit reset */
  56 #define ICR_FM          (1 << 15)          /* fast mode */
  57 #define ICR_HS          (1 << 16)          /* High Speed mode */
  58 #define ICR_A3700_FM    (1 << 16)          /* fast mode for armada-3700 */
  59 #define ICR_A3700_HS    (1 << 17)          /* high speed mode for armada-3700 */
  60 #define ICR_GPIOEN      (1 << 19)          /* enable GPIO mode for SCL in HS */
  61
  62 #define ISR_RWM         (1 << 0)           /* read/write mode */
  63 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
  64 #define ISR_UB          (1 << 2)           /* unit busy */
  65 #define ISR_IBB         (1 << 3)           /* bus busy */
  66 #define ISR_SSD         (1 << 4)           /* slave stop detected */
  67 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
  68 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
  69 #define ISR_IRF         (1 << 7)           /* rx buffer full */
  70 #define ISR_GCAD        (1 << 8)           /* general call address detected */
  71 #define ISR_SAD         (1 << 9)           /* slave address detected */
  72 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
  73
  74 #define ILCR_SLV_SHIFT          0
  75 #define ILCR_SLV_MASK           (0x1FF << ILCR_SLV_SHIFT)
  76 #define ILCR_FLV_SHIFT          9
  77 #define ILCR_FLV_MASK           (0x1FF << ILCR_FLV_SHIFT)
  78 #define ILCR_HLVL_SHIFT         18
  79 #define ILCR_HLVL_MASK          (0x1FF << ILCR_HLVL_SHIFT)
  80 #define ILCR_HLVH_SHIFT         27
  81 #define ILCR_HLVH_MASK          (0x1F << ILCR_HLVH_SHIFT)
  82
  83 #define IWCR_CNT_SHIFT          0
  84 #define IWCR_CNT_MASK           (0x1F << IWCR_CNT_SHIFT)
  85 #define IWCR_HS_CNT1_SHIFT      5
  86 #define IWCR_HS_CNT1_MASK       (0x1F << IWCR_HS_CNT1_SHIFT)
  87 #define IWCR_HS_CNT2_SHIFT      10
  88 #define IWCR_HS_CNT2_MASK       (0x1F << IWCR_HS_CNT2_SHIFT)
  89
  90 /* need a longer timeout if we're dealing with the fact we may well be
  91  * looking at a multi-master environment
  92  */
  93 #define DEF_TIMEOUT             32
  94
  95 #define NO_SLAVE                (-ENXIO)
  96 #define BUS_ERROR               (-EREMOTEIO)
  97 #define XFER_NAKED              (-ECONNREFUSED)
  98 #define I2C_RETRY               (-2000) /* an error has occurred retry transmit */
  99
 100 /* ICR initialize bit values
 101  *
 102  * 15 FM     0 (100 kHz operation)
 103  * 14 UR     0 (No unit reset)
 104  * 13 SADIE  0 (Disables the unit from interrupting on slave addresses
 105  *              matching its slave address)
 106  * 12 ALDIE  0 (Disables the unit from interrupt when it loses arbitration
 107  *              in master mode)
 108  * 11 SSDIE  0 (Disables interrupts from a slave stop detected, in slave mode)
 109  * 10 BEIE   1 (Enable interrupts from detected bus errors, no ACK sent)
 110  *  9 IRFIE  1 (Enable interrupts from full buffer received)
 111  *  8 ITEIE  1 (Enables the I2C unit to interrupt when transmit buffer empty)
 112  *  7 GCD    1 (Disables i2c unit response to general call messages as a slave)
 113  *  6 IUE    0 (Disable unit until we change settings)
 114  *  5 SCLE   1 (Enables the i2c clock output for master mode (drives SCL)
 115  *  4 MA     0 (Only send stop with the ICR stop bit)
 116  *  3 TB     0 (We are not transmitting a byte initially)
 117  *  2 ACKNAK 0 (Send an ACK after the unit receives a byte)
 118  *  1 STOP   0 (Do not send a STOP)
 119  *  0 START  0 (Do not send a START)
 120  */
 121 #define I2C_ICR_INIT    (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
 122
 123 /* I2C status register init values
 124  *
 125  * 10 BED    1 (Clear bus error detected)
 126  *  9 SAD    1 (Clear slave address detected)
 127  *  7 IRF    1 (Clear IDBR Receive Full)
 128  *  6 ITE    1 (Clear IDBR Transmit Empty)
 129  *  5 ALD    1 (Clear Arbitration Loss Detected)
 130  *  4 SSD    1 (Clear Slave Stop Detected)
 131  */
 132 #define I2C_ISR_INIT    0x7FF  /* status register init */
 133
 134 struct pxa_reg_layout {
 135         u32 ibmr;
 136         u32 idbr;
 137         u32 icr;
 138         u32 isr;
 139         u32 isar;
 140         u32 ilcr;
 141         u32 iwcr;
 142         u32 fm;
 143         u32 hs;
 144 };
 145
 146 enum pxa_i2c_types {
 147         REGS_PXA2XX,
 148         REGS_PXA3XX,
 149         REGS_CE4100,
 150         REGS_PXA910,
 151         REGS_A3700,
 152 };
 153
 154 /* I2C register layout definitions */
 155 static struct pxa_reg_layout pxa_reg_layout[] = {
 156         [REGS_PXA2XX] = {
 157                 .ibmr = 0x00,
 158                 .idbr = 0x08,
 159                 .icr =  0x10,
 160                 .isr =  0x18,
 161                 .isar = 0x20,
 162                 .fm = ICR_FM,
 163                 .hs = ICR_HS,
 164         },
 165         [REGS_PXA3XX] = {
 166                 .ibmr = 0x00,
 167                 .idbr = 0x04,
 168                 .icr =  0x08,
 169                 .isr =  0x0c,
 170                 .isar = 0x10,
 171                 .fm = ICR_FM,
 172                 .hs = ICR_HS,
 173         },
 174         [REGS_CE4100] = {
 175                 .ibmr = 0x14,
 176                 .idbr = 0x0c,
 177                 .icr =  0x00,
 178                 .isr =  0x04,
 179                 /* no isar register */
 180                 .fm = ICR_FM,
 181                 .hs = ICR_HS,
 182         },
 183         [REGS_PXA910] = {
 184                 .ibmr = 0x00,
 185                 .idbr = 0x08,
 186                 .icr =  0x10,
 187                 .isr =  0x18,
 188                 .isar = 0x20,
 189                 .ilcr = 0x28,
 190                 .iwcr = 0x30,
 191                 .fm = ICR_FM,
 192                 .hs = ICR_HS,
 193         },
 194         [REGS_A3700] = {
 195                 .ibmr = 0x00,
 196                 .idbr = 0x04,
 197                 .icr =  0x08,
 198                 .isr =  0x0c,
 199                 .isar = 0x10,
 200                 .fm = ICR_A3700_FM,
 201                 .hs = ICR_A3700_HS,
 202         },
 203 };
 204
 205 static const struct of_device_id i2c_pxa_dt_ids[] = {
 206         { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
 207         { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
 208         { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
 209         { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
 210         {}
 211 };
 212 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
 213
 214 static const struct platform_device_id i2c_pxa_id_table[] = {
 215         { "pxa2xx-i2c",         REGS_PXA2XX },
 216         { "pxa3xx-pwri2c",      REGS_PXA3XX },
 217         { "ce4100-i2c",         REGS_CE4100 },
 218         { "pxa910-i2c",         REGS_PXA910 },
 219         { "armada-3700-i2c",    REGS_A3700  },
 220         { },
 221 };
 222 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
 223
 224 struct pxa_i2c {
 225         spinlock_t              lock;
 226         wait_queue_head_t       wait;
 227         struct i2c_msg          *msg;
 228         unsigned int            msg_num;
 229         unsigned int            msg_idx;
 230         unsigned int            msg_ptr;
 231         unsigned int            slave_addr;
 232         unsigned int            req_slave_addr;
 233
 234         struct i2c_adapter      adap;
 235         struct clk              *clk;
 236 #ifdef CONFIG_I2C_PXA_SLAVE
 237         struct i2c_client       *slave;
 238 #endif
 239
 240         unsigned int            irqlogidx;
 241         u32                     isrlog[32];
 242         u32                     icrlog[32];
 243
 244         void __iomem            *reg_base;
 245         void __iomem            *reg_ibmr;
 246         void __iomem            *reg_idbr;
 247         void __iomem            *reg_icr;
 248         void __iomem            *reg_isr;
 249         void __iomem            *reg_isar;
 250         void __iomem            *reg_ilcr;
 251         void __iomem            *reg_iwcr;
 252
 253         unsigned long           iobase;
 254         unsigned long           iosize;
 255
 256         int                     irq;
 257         unsigned int            use_pio :1;
 258         unsigned int            fast_mode :1;
 259         unsigned int            high_mode:1;
 260         unsigned char           master_code;
 261         unsigned long           rate;
 262         bool                    highmode_enter;
 263         u32                     fm_mask;
 264         u32                     hs_mask;
 265
 266         struct i2c_bus_recovery_info recovery;
 267         struct pinctrl          *pinctrl;
 268         struct pinctrl_state    *pinctrl_default;
 269         struct pinctrl_state    *pinctrl_recovery;
 270 };
 271
 272 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
 273 #define _IDBR(i2c)      ((i2c)->reg_idbr)
 274 #define _ICR(i2c)       ((i2c)->reg_icr)
 275 #define _ISR(i2c)       ((i2c)->reg_isr)
 276 #define _ISAR(i2c)      ((i2c)->reg_isar)
 277 #define _ILCR(i2c)      ((i2c)->reg_ilcr)
 278 #define _IWCR(i2c)      ((i2c)->reg_iwcr)
 279
 280 /*
 281  * I2C Slave mode address
 282  */
 283 #define I2C_PXA_SLAVE_ADDR      0x1
 284
 285 #ifdef DEBUG
 286
 287 struct bits {
 288         u32     mask;
 289         const char *set;
 290         const char *unset;
 291 };
 292 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 293
 294 static inline void
 295 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 296 {
 297         printk("%s %08x:", prefix, val);
 298         while (num--) {
 299                 const char *str = val & bits->mask ? bits->set : bits->unset;
 300                 if (str)
 301                         pr_cont(" %s", str);
 302                 bits++;
 303         }
 304         pr_cont("\n");
 305 }
 306
 307 static const struct bits isr_bits[] = {
 308         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 309         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 310         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 311         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 312         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 313         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 314         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 315         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 316         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 317         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 318         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 319 };
 320
 321 static void decode_ISR(unsigned int val)
 322 {
 323         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 324 }
 325
 326 static const struct bits icr_bits[] = {
 327         PXA_BIT(ICR_START,  "START",    NULL),
 328         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 329         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 330         PXA_BIT(ICR_TB,     "TB",       NULL),
 331         PXA_BIT(ICR_MA,     "MA",       NULL),
 332         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 333         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 334         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 335         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 336         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 337         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 338         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 339         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 340         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 341         PXA_BIT(ICR_UR,     "UR",               "ur"),
 342 };
 343
 344 #ifdef CONFIG_I2C_PXA_SLAVE
 345 static void decode_ICR(unsigned int val)
 346 {
 347         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 348 }
 349 #endif
 350
 351 static unsigned int i2c_debug = DEBUG;
 352
 353 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 354 {
 355         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 356                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 357 }
 358
 359 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 360
 361 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 362 {
 363         unsigned int i;
 364         struct device *dev = &i2c->adap.dev;
 365
 366         dev_err(dev, "slave_0x%x error: %s\n",
 367                 i2c->req_slave_addr >> 1, why);
 368         dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
 369                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 370         dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
 371                 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
 372                 readl(_ISR(i2c)));
 373         dev_err(dev, "log:");
 374         for (i = 0; i < i2c->irqlogidx; i++)
 375                 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
 376         pr_cont("\n");
 377 }
 378
 379 #else /* ifdef DEBUG */
 380
 381 #define i2c_debug       0
 382
 383 #define show_state(i2c) do { } while (0)
 384 #define decode_ISR(val) do { } while (0)
 385 #define decode_ICR(val) do { } while (0)
 386 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 387
 388 #endif /* ifdef DEBUG / else */
 389
 390 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 391
 392 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 393 {
 394         return !(readl(_ICR(i2c)) & ICR_SCLE);
 395 }
 396
 397 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 398 {
 399         int i = 250;
 400
 401         if (i2c_pxa_is_slavemode(i2c)) {
 402                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 403                 return;
 404         }
 405
 406         while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
 407                 unsigned long icr = readl(_ICR(i2c));
 408
 409                 icr &= ~ICR_START;
 410                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 411
 412                 writel(icr, _ICR(i2c));
 413
 414                 show_state(i2c);
 415
 416                 mdelay(1);
 417                 i --;
 418         }
 419
 420         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 421                _ICR(i2c));
 422 }
 423
 424 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 425 {
 426         int timeout = DEF_TIMEOUT;
 427         u32 isr;
 428
 429         while (1) {
 430                 isr = readl(_ISR(i2c));
 431                 if (!(isr & (ISR_IBB | ISR_UB)))
 432                         return 0;
 433
 434                 if (isr & ISR_SAD)
 435                         timeout += 4;
 436
 437                 if (!timeout--)
 438                         break;
 439
 440                 msleep(2);
 441                 show_state(i2c);
 442         }
 443
 444         show_state(i2c);
 445
 446         return I2C_RETRY;
 447 }
 448
 449 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 450 {
 451         unsigned long timeout = jiffies + HZ*4;
 452
 453         while (time_before(jiffies, timeout)) {
 454                 if (i2c_debug > 1)
 455                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 456                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 457
 458                 if (readl(_ISR(i2c)) & ISR_SAD) {
 459                         if (i2c_debug > 0)
 460                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 461                         goto out;
 462                 }
 463
 464                 /* wait for unit and bus being not busy, and we also do a
 465                  * quick check of the i2c lines themselves to ensure they've
 466                  * gone high...
 467                  */
 468                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
 469                     readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
 470                         if (i2c_debug > 0)
 471                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 472                         return 1;
 473                 }
 474
 475                 msleep(1);
 476         }
 477
 478         if (i2c_debug > 0)
 479                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 480  out:
 481         return 0;
 482 }
 483
 484 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 485 {
 486         if (i2c_debug)
 487                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 488
 489         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 490                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 491                 if (!i2c_pxa_wait_master(i2c)) {
 492                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 493                         return I2C_RETRY;
 494                 }
 495         }
 496
 497         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 498         return 0;
 499 }
 500
 501 #ifdef CONFIG_I2C_PXA_SLAVE
 502 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 503 {
 504         unsigned long timeout = jiffies + HZ*1;
 505
 506         /* wait for stop */
 507
 508         show_state(i2c);
 509
 510         while (time_before(jiffies, timeout)) {
 511                 if (i2c_debug > 1)
 512                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 513                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 514
 515                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 516                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 517                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 518                         if (i2c_debug > 1)
 519                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 520                         return 1;
 521                 }
 522
 523                 msleep(1);
 524         }
 525
 526         if (i2c_debug > 0)
 527                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 528         return 0;
 529 }
 530
 531 /*
 532  * clear the hold on the bus, and take of anything else
 533  * that has been configured
 534  */
 535 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 536 {
 537         show_state(i2c);
 538
 539         if (errcode < 0) {
 540                 udelay(100);   /* simple delay */
 541         } else {
 542                 /* we need to wait for the stop condition to end */
 543
 544                 /* if we where in stop, then clear... */
 545                 if (readl(_ICR(i2c)) & ICR_STOP) {
 546                         udelay(100);
 547                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 548                 }
 549
 550                 if (!i2c_pxa_wait_slave(i2c)) {
 551                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 552                                 __func__);
 553                         return;
 554                 }
 555         }
 556
 557         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 558         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 559
 560         if (i2c_debug) {
 561                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 562                 decode_ICR(readl(_ICR(i2c)));
 563         }
 564 }
 565 #else
 566 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 567 #endif
 568
 569 static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
 570 {
 571         /* reset according to 9.8 */
 572         writel(ICR_UR, _ICR(i2c));
 573         writel(I2C_ISR_INIT, _ISR(i2c));
 574         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 575
 576         if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
 577                 writel(i2c->slave_addr, _ISAR(i2c));
 578
 579         /* set control register values */
 580         writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
 581         writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
 582
 583 #ifdef CONFIG_I2C_PXA_SLAVE
 584         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 585         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 586 #endif
 587
 588         i2c_pxa_set_slave(i2c, 0);
 589 }
 590
 591 static void i2c_pxa_enable(struct pxa_i2c *i2c)
 592 {
 593         /* enable unit */
 594         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 595         udelay(100);
 596 }
 597
 598 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 599 {
 600         pr_debug("Resetting I2C Controller Unit\n");
 601
 602         /* abort any transfer currently under way */
 603         i2c_pxa_abort(i2c);
 604         i2c_pxa_do_reset(i2c);
 605         i2c_pxa_enable(i2c);
 606 }
 607
 608
 609 #ifdef CONFIG_I2C_PXA_SLAVE
 610 /*
 611  * PXA I2C Slave mode
 612  */
 613
 614 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 615 {
 616         if (isr & ISR_BED) {
 617                 /* what should we do here? */
 618         } else {
 619                 u8 byte = 0;
 620
 621                 if (i2c->slave != NULL)
 622                         i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
 623                                         &byte);
 624
 625                 writel(byte, _IDBR(i2c));
 626                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 627         }
 628 }
 629
 630 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 631 {
 632         u8 byte = readl(_IDBR(i2c));
 633
 634         if (i2c->slave != NULL)
 635                 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
 636
 637         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 638 }
 639
 640 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 641 {
 642         int timeout;
 643
 644         if (i2c_debug > 0)
 645                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 646                        (isr & ISR_RWM) ? 'r' : 't');
 647
 648         if (i2c->slave != NULL) {
 649                 if (isr & ISR_RWM) {
 650                         u8 byte = 0;
 651
 652                         i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
 653                                         &byte);
 654                         writel(byte, _IDBR(i2c));
 655                 } else {
 656                         i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
 657                                         NULL);
 658                 }
 659         }
 660
 661         /*
 662          * slave could interrupt in the middle of us generating a
 663          * start condition... if this happens, we'd better back off
 664          * and stop holding the poor thing up
 665          */
 666         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 667         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 668
 669         timeout = 0x10000;
 670
 671         while (1) {
 672                 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
 673                         break;
 674
 675                 timeout--;
 676
 677                 if (timeout <= 0) {
 678                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 679                         break;
 680                 }
 681         }
 682
 683         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 684 }
 685
 686 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 687 {
 688         if (i2c_debug > 2)
 689                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 690
 691         if (i2c->slave != NULL)
 692                 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
 693
 694         if (i2c_debug > 2)
 695                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 696
 697         /*
 698          * If we have a master-mode message waiting,
 699          * kick it off now that the slave has completed.
 700          */
 701         if (i2c->msg)
 702                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 703 }
 704
 705 static int i2c_pxa_slave_reg(struct i2c_client *slave)
 706 {
 707         struct pxa_i2c *i2c = slave->adapter->algo_data;
 708
 709         if (i2c->slave)
 710                 return -EBUSY;
 711
 712         if (!i2c->reg_isar)
 713                 return -EAFNOSUPPORT;
 714
 715         i2c->slave = slave;
 716         i2c->slave_addr = slave->addr;
 717
 718         writel(i2c->slave_addr, _ISAR(i2c));
 719
 720         return 0;
 721 }
 722
 723 static int i2c_pxa_slave_unreg(struct i2c_client *slave)
 724 {
 725         struct pxa_i2c *i2c = slave->adapter->algo_data;
 726
 727         WARN_ON(!i2c->slave);
 728
 729         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 730         writel(i2c->slave_addr, _ISAR(i2c));
 731
 732         i2c->slave = NULL;
 733
 734         return 0;
 735 }
 736 #else
 737 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 738 {
 739         if (isr & ISR_BED) {
 740                 /* what should we do here? */
 741         } else {
 742                 writel(0, _IDBR(i2c));
 743                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 744         }
 745 }
 746
 747 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 748 {
 749         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 750 }
 751
 752 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 753 {
 754         int timeout;
 755
 756         /*
 757          * slave could interrupt in the middle of us generating a
 758          * start condition... if this happens, we'd better back off
 759          * and stop holding the poor thing up
 760          */
 761         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 762         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 763
 764         timeout = 0x10000;
 765
 766         while (1) {
 767                 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
 768                         break;
 769
 770                 timeout--;
 771
 772                 if (timeout <= 0) {
 773                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 774                         break;
 775                 }
 776         }
 777
 778         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 779 }
 780
 781 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 782 {
 783         if (i2c->msg)
 784                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 785 }
 786 #endif
 787
 788 /*
 789  * PXA I2C Master mode
 790  */
 791
 792 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 793 {
 794         u32 icr;
 795
 796         /*
 797          * Step 1: target slave address into IDBR
 798          */
 799         i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
 800         writel(i2c->req_slave_addr, _IDBR(i2c));
 801
 802         /*
 803          * Step 2: initiate the write.
 804          */
 805         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 806         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 807 }
 808
 809 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 810 {
 811         u32 icr;
 812
 813         /* Clear the START, STOP, ACK, TB and MA flags */
 814         icr = readl(_ICR(i2c));
 815         icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
 816         writel(icr, _ICR(i2c));
 817 }
 818
 819 /*
 820  * PXA I2C send master code
 821  * 1. Load master code to IDBR and send it.
 822  *    Note for HS mode, set ICR [GPIOEN].
 823  * 2. Wait until win arbitration.
 824  */
 825 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
 826 {
 827         u32 icr;
 828         long timeout;
 829
 830         spin_lock_irq(&i2c->lock);
 831         i2c->highmode_enter = true;
 832         writel(i2c->master_code, _IDBR(i2c));
 833
 834         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 835         icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
 836         writel(icr, _ICR(i2c));
 837
 838         spin_unlock_irq(&i2c->lock);
 839         timeout = wait_event_timeout(i2c->wait,
 840                         i2c->highmode_enter == false, HZ * 1);
 841
 842         i2c->highmode_enter = false;
 843
 844         return (timeout == 0) ? I2C_RETRY : 0;
 845 }
 846
 847 /*
 848  * i2c_pxa_master_complete - complete the message and wake up.
 849  */
 850 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 851 {
 852         i2c->msg_ptr = 0;
 853         i2c->msg = NULL;
 854         i2c->msg_idx ++;
 855         i2c->msg_num = 0;
 856         if (ret)
 857                 i2c->msg_idx = ret;
 858         if (!i2c->use_pio)
 859                 wake_up(&i2c->wait);
 860 }
 861
 862 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 863 {
 864         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 865
 866  again:
 867         /*
 868          * If ISR_ALD is set, we lost arbitration.
 869          */
 870         if (isr & ISR_ALD) {
 871                 /*
 872                  * Do we need to do anything here?  The PXA docs
 873                  * are vague about what happens.
 874                  */
 875                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 876
 877                 /*
 878                  * We ignore this error.  We seem to see spurious ALDs
 879                  * for seemingly no reason.  If we handle them as I think
 880                  * they should, we end up causing an I2C error, which
 881                  * is painful for some systems.
 882                  */
 883                 return; /* ignore */
 884         }
 885
 886         if ((isr & ISR_BED) &&
 887                 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
 888                         (isr & ISR_ACKNAK)))) {
 889                 int ret = BUS_ERROR;
 890
 891                 /*
 892                  * I2C bus error - either the device NAK'd us, or
 893                  * something more serious happened.  If we were NAK'd
 894                  * on the initial address phase, we can retry.
 895                  */
 896                 if (isr & ISR_ACKNAK) {
 897                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 898                                 ret = NO_SLAVE;
 899                         else
 900                                 ret = XFER_NAKED;
 901                 }
 902                 i2c_pxa_master_complete(i2c, ret);
 903         } else if (isr & ISR_RWM) {
 904                 /*
 905                  * Read mode.  We have just sent the address byte, and
 906                  * now we must initiate the transfer.
 907                  */
 908                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 909                     i2c->msg_idx == i2c->msg_num - 1)
 910                         icr |= ICR_STOP | ICR_ACKNAK;
 911
 912                 icr |= ICR_ALDIE | ICR_TB;
 913         } else if (i2c->msg_ptr < i2c->msg->len) {
 914                 /*
 915                  * Write mode.  Write the next data byte.
 916                  */
 917                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 918
 919                 icr |= ICR_ALDIE | ICR_TB;
 920
 921                 /*
 922                  * If this is the last byte of the last message or last byte
 923                  * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
 924                  */
 925                 if ((i2c->msg_ptr == i2c->msg->len) &&
 926                         ((i2c->msg->flags & I2C_M_STOP) ||
 927                         (i2c->msg_idx == i2c->msg_num - 1)))
 928                                 icr |= ICR_STOP;
 929
 930         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 931                 /*
 932                  * Next segment of the message.
 933                  */
 934                 i2c->msg_ptr = 0;
 935                 i2c->msg_idx ++;
 936                 i2c->msg++;
 937
 938                 /*
 939                  * If we aren't doing a repeated start and address,
 940                  * go back and try to send the next byte.  Note that
 941                  * we do not support switching the R/W direction here.
 942                  */
 943                 if (i2c->msg->flags & I2C_M_NOSTART)
 944                         goto again;
 945
 946                 /*
 947                  * Write the next address.
 948                  */
 949                 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
 950                 writel(i2c->req_slave_addr, _IDBR(i2c));
 951
 952                 /*
 953                  * And trigger a repeated start, and send the byte.
 954                  */
 955                 icr &= ~ICR_ALDIE;
 956                 icr |= ICR_START | ICR_TB;
 957         } else {
 958                 if (i2c->msg->len == 0)
 959                         icr |= ICR_MA;
 960                 i2c_pxa_master_complete(i2c, 0);
 961         }
 962
 963         i2c->icrlog[i2c->irqlogidx-1] = icr;
 964
 965         writel(icr, _ICR(i2c));
 966         show_state(i2c);
 967 }
 968
 969 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 970 {
 971         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 972
 973         /*
 974          * Read the byte.
 975          */
 976         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 977
 978         if (i2c->msg_ptr < i2c->msg->len) {
 979                 /*
 980                  * If this is the last byte of the last
 981                  * message, send a STOP.
 982                  */
 983                 if (i2c->msg_ptr == i2c->msg->len - 1)
 984                         icr |= ICR_STOP | ICR_ACKNAK;
 985
 986                 icr |= ICR_ALDIE | ICR_TB;
 987         } else {
 988                 i2c_pxa_master_complete(i2c, 0);
 989         }
 990
 991         i2c->icrlog[i2c->irqlogidx-1] = icr;
 992
 993         writel(icr, _ICR(i2c));
 994 }
 995
 996 #define VALID_INT_SOURCE        (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
 997                                 ISR_SAD | ISR_BED)
 998 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 999 {
1000         struct pxa_i2c *i2c = dev_id;
1001         u32 isr = readl(_ISR(i2c));
1002
1003         if (!(isr & VALID_INT_SOURCE))
1004                 return IRQ_NONE;
1005
1006         if (i2c_debug > 2 && 0) {
1007                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1008                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1009                 decode_ISR(isr);
1010         }
1011
1012         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1013                 i2c->isrlog[i2c->irqlogidx++] = isr;
1014
1015         show_state(i2c);
1016
1017         /*
1018          * Always clear all pending IRQs.
1019          */
1020         writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1021
1022         if (isr & ISR_SAD)
1023                 i2c_pxa_slave_start(i2c, isr);
1024         if (isr & ISR_SSD)
1025                 i2c_pxa_slave_stop(i2c);
1026
1027         if (i2c_pxa_is_slavemode(i2c)) {
1028                 if (isr & ISR_ITE)
1029                         i2c_pxa_slave_txempty(i2c, isr);
1030                 if (isr & ISR_IRF)
1031                         i2c_pxa_slave_rxfull(i2c, isr);
1032         } else if (i2c->msg && (!i2c->highmode_enter)) {
1033                 if (isr & ISR_ITE)
1034                         i2c_pxa_irq_txempty(i2c, isr);
1035                 if (isr & ISR_IRF)
1036                         i2c_pxa_irq_rxfull(i2c, isr);
1037         } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1038                 i2c->highmode_enter = false;
1039                 wake_up(&i2c->wait);
1040         } else {
1041                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1042         }
1043
1044         return IRQ_HANDLED;
1045 }
1046
1047 /*
1048  * We are protected by the adapter bus mutex.
1049  */
1050 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1051 {
1052         long timeout;
1053         int ret;
1054
1055         /*
1056          * Wait for the bus to become free.
1057          */
1058         ret = i2c_pxa_wait_bus_not_busy(i2c);
1059         if (ret) {
1060                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1061                 i2c_recover_bus(&i2c->adap);
1062                 goto out;
1063         }
1064
1065         /*
1066          * Set master mode.
1067          */
1068         ret = i2c_pxa_set_master(i2c);
1069         if (ret) {
1070                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1071                 goto out;
1072         }
1073
1074         if (i2c->high_mode) {
1075                 ret = i2c_pxa_send_mastercode(i2c);
1076                 if (ret) {
1077                         dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1078                         goto out;
1079                         }
1080         }
1081
1082         spin_lock_irq(&i2c->lock);
1083
1084         i2c->msg = msg;
1085         i2c->msg_num = num;
1086         i2c->msg_idx = 0;
1087         i2c->msg_ptr = 0;
1088         i2c->irqlogidx = 0;
1089
1090         i2c_pxa_start_message(i2c);
1091
1092         spin_unlock_irq(&i2c->lock);
1093
1094         /*
1095          * The rest of the processing occurs in the interrupt handler.
1096          */
1097         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1098         i2c_pxa_stop_message(i2c);
1099
1100         /*
1101          * We place the return code in i2c->msg_idx.
1102          */
1103         ret = i2c->msg_idx;
1104
1105         if (!timeout && i2c->msg_num) {
1106                 i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1107                 i2c_recover_bus(&i2c->adap);
1108                 ret = I2C_RETRY;
1109         }
1110
1111  out:
1112         return ret;
1113 }
1114
1115 static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1116                                  struct i2c_msg *msgs, int num,
1117                                  int (*xfer)(struct pxa_i2c *,
1118                                              struct i2c_msg *, int num))
1119 {
1120         int ret, i;
1121
1122         for (i = 0; ; ) {
1123                 ret = xfer(i2c, msgs, num);
1124                 if (ret != I2C_RETRY && ret != NO_SLAVE)
1125                         goto out;
1126                 if (++i >= i2c->adap.retries)
1127                         break;
1128
1129                 if (i2c_debug)
1130                         dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1131                 udelay(100);
1132         }
1133         if (ret != NO_SLAVE)
1134                 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1135         ret = -EREMOTEIO;
1136  out:
1137         i2c_pxa_set_slave(i2c, ret);
1138         return ret;
1139 }
1140
1141 static int i2c_pxa_xfer(struct i2c_adapter *adap,
1142                         struct i2c_msg msgs[], int num)
1143 {
1144         struct pxa_i2c *i2c = adap->algo_data;
1145
1146         return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1147 }
1148
1149 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1150 {
1151         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1152                 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1153 }
1154
1155 static const struct i2c_algorithm i2c_pxa_algorithm = {
1156         .master_xfer    = i2c_pxa_xfer,
1157         .functionality  = i2c_pxa_functionality,
1158 #ifdef CONFIG_I2C_PXA_SLAVE
1159         .reg_slave      = i2c_pxa_slave_reg,
1160         .unreg_slave    = i2c_pxa_slave_unreg,
1161 #endif
1162 };
1163
1164 /* Non-interrupt mode support */
1165 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1166 {
1167         /* make timeout the same as for interrupt based functions */
1168         long timeout = 2 * DEF_TIMEOUT;
1169
1170         /*
1171          * Wait for the bus to become free.
1172          */
1173         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1174                 udelay(1000);
1175
1176         if (timeout < 0) {
1177                 show_state(i2c);
1178                 dev_err(&i2c->adap.dev,
1179                         "i2c_pxa: timeout waiting for bus free (set_master)\n");
1180                 return I2C_RETRY;
1181         }
1182
1183         /*
1184          * Set master mode.
1185          */
1186         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1187
1188         return 0;
1189 }
1190
1191 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1192                                struct i2c_msg *msg, int num)
1193 {
1194         unsigned long timeout = 500000; /* 5 seconds */
1195         int ret = 0;
1196
1197         ret = i2c_pxa_pio_set_master(i2c);
1198         if (ret)
1199                 goto out;
1200
1201         i2c->msg = msg;
1202         i2c->msg_num = num;
1203         i2c->msg_idx = 0;
1204         i2c->msg_ptr = 0;
1205         i2c->irqlogidx = 0;
1206
1207         i2c_pxa_start_message(i2c);
1208
1209         while (i2c->msg_num > 0 && --timeout) {
1210                 i2c_pxa_handler(0, i2c);
1211                 udelay(10);
1212         }
1213
1214         i2c_pxa_stop_message(i2c);
1215
1216         /*
1217          * We place the return code in i2c->msg_idx.
1218          */
1219         ret = i2c->msg_idx;
1220
1221 out:
1222         if (timeout == 0) {
1223                 i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1224                 ret = I2C_RETRY;
1225         }
1226
1227         return ret;
1228 }
1229
1230 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1231                             struct i2c_msg msgs[], int num)
1232 {
1233         struct pxa_i2c *i2c = adap->algo_data;
1234
1235         /* If the I2C controller is disabled we need to reset it
1236           (probably due to a suspend/resume destroying state). We do
1237           this here as we can then avoid worrying about resuming the
1238           controller before its users. */
1239         if (!(readl(_ICR(i2c)) & ICR_IUE))
1240                 i2c_pxa_reset(i2c);
1241
1242         return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1243 }
1244
1245 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1246         .master_xfer    = i2c_pxa_pio_xfer,
1247         .functionality  = i2c_pxa_functionality,
1248 #ifdef CONFIG_I2C_PXA_SLAVE
1249         .reg_slave      = i2c_pxa_slave_reg,
1250         .unreg_slave    = i2c_pxa_slave_unreg,
1251 #endif
1252 };
1253
1254 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1255                             enum pxa_i2c_types *i2c_types)
1256 {
1257         struct device_node *np = pdev->dev.of_node;
1258         const struct of_device_id *of_id =
1259                         of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1260
1261         if (!of_id)
1262                 return 1;
1263
1264         /* For device tree we always use the dynamic or alias-assigned ID */
1265         i2c->adap.nr = -1;
1266
1267         if (of_get_property(np, "mrvl,i2c-polling", NULL))
1268                 i2c->use_pio = 1;
1269         if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1270                 i2c->fast_mode = 1;
1271
1272         *i2c_types = (enum pxa_i2c_types)(of_id->data);
1273
1274         return 0;
1275 }
1276
1277 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1278                                struct pxa_i2c *i2c,
1279                                enum pxa_i2c_types *i2c_types)
1280 {
1281         struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1282         const struct platform_device_id *id = platform_get_device_id(pdev);
1283
1284         *i2c_types = id->driver_data;
1285         if (plat) {
1286                 i2c->use_pio = plat->use_pio;
1287                 i2c->fast_mode = plat->fast_mode;
1288                 i2c->high_mode = plat->high_mode;
1289                 i2c->master_code = plat->master_code;
1290                 if (!i2c->master_code)
1291                         i2c->master_code = 0xe;
1292                 i2c->rate = plat->rate;
1293         }
1294         return 0;
1295 }
1296
1297 static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1298 {
1299         struct pxa_i2c *i2c = adap->algo_data;
1300         u32 ibmr = readl(_IBMR(i2c));
1301
1302         /*
1303          * Program the GPIOs to reflect the current I2C bus state while
1304          * we transition to recovery; this avoids glitching the bus.
1305          */
1306         gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1307         gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1308
1309         WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
1310 }
1311
1312 static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1313 {
1314         struct pxa_i2c *i2c = adap->algo_data;
1315         u32 isr;
1316
1317         /*
1318          * The bus should now be free. Clear up the I2C controller before
1319          * handing control of the bus back to avoid the bus changing state.
1320          */
1321         isr = readl(_ISR(i2c));
1322         if (isr & (ISR_UB | ISR_IBB)) {
1323                 dev_dbg(&i2c->adap.dev,
1324                         "recovery: resetting controller, ISR=0x%08x\n", isr);
1325                 i2c_pxa_do_reset(i2c);
1326         }
1327
1328         WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
1329
1330         dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1331                 readl(_IBMR(i2c)), readl(_ISR(i2c)));
1332
1333         i2c_pxa_enable(i2c);
1334 }
1335
1336 static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1337 {
1338         struct i2c_bus_recovery_info *bri = &i2c->recovery;
1339         struct device *dev = i2c->adap.dev.parent;
1340
1341         /*
1342          * When slave mode is enabled, we are not the only master on the bus.
1343          * Bus recovery can only be performed when we are the master, which
1344          * we can't be certain of. Therefore, when slave mode is enabled, do
1345          * not configure bus recovery.
1346          */
1347         if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1348                 return 0;
1349
1350         i2c->pinctrl = devm_pinctrl_get(dev);
1351         if (PTR_ERR(i2c->pinctrl) == -ENODEV)
1352                 i2c->pinctrl = NULL;
1353         if (IS_ERR(i2c->pinctrl))
1354                 return PTR_ERR(i2c->pinctrl);
1355
1356         if (!i2c->pinctrl)
1357                 return 0;
1358
1359         i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
1360                                                     PINCTRL_STATE_DEFAULT);
1361         i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
1362
1363         if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) {
1364                 dev_info(dev, "missing pinmux recovery information: %ld %ld\n",
1365                          PTR_ERR(i2c->pinctrl_default),
1366                          PTR_ERR(i2c->pinctrl_recovery));
1367                 return 0;
1368         }
1369
1370         /*
1371          * Claiming GPIOs can influence the pinmux state, and may glitch the
1372          * I2C bus. Do this carefully.
1373          */
1374         bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1375         if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER))
1376                 return -EPROBE_DEFER;
1377         if (IS_ERR(bri->scl_gpiod)) {
1378                 dev_info(dev, "missing scl gpio recovery information: %pe\n",
1379                          bri->scl_gpiod);
1380                 return 0;
1381         }
1382
1383         /*
1384          * We have SCL. Pull SCL low and wait a bit so that SDA glitches
1385          * have no effect.
1386          */
1387         gpiod_direction_output(bri->scl_gpiod, 0);
1388         udelay(10);
1389         bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN);
1390
1391         /* Wait a bit in case of a SDA glitch, and then release SCL. */
1392         udelay(10);
1393         gpiod_direction_output(bri->scl_gpiod, 1);
1394
1395         if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER))
1396                 return -EPROBE_DEFER;
1397
1398         if (IS_ERR(bri->sda_gpiod)) {
1399                 dev_info(dev, "missing sda gpio recovery information: %pe\n",
1400                          bri->sda_gpiod);
1401                 return 0;
1402         }
1403
1404         bri->prepare_recovery = i2c_pxa_prepare_recovery;
1405         bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1406         bri->recover_bus = i2c_generic_scl_recovery;
1407
1408         i2c->adap.bus_recovery_info = bri;
1409
1410         /*
1411          * Claiming GPIOs can change the pinmux state, which confuses the
1412          * pinctrl since pinctrl's idea of the current setting is unaffected
1413          * by the pinmux change caused by claiming the GPIO. Work around that
1414          * by switching pinctrl to the GPIO state here. We do it this way to
1415          * avoid glitching the I2C bus.
1416          */
1417         pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
1418
1419         return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
1420 }
1421
1422 static int i2c_pxa_probe(struct platform_device *dev)
1423 {
1424         struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1425         enum pxa_i2c_types i2c_type;
1426         struct pxa_i2c *i2c;
1427         struct resource *res = NULL;
1428         int ret, irq;
1429
1430         i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1431         if (!i2c)
1432                 return -ENOMEM;
1433
1434         /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1435         i2c->adap.nr = dev->id;
1436         i2c->adap.owner   = THIS_MODULE;
1437         i2c->adap.retries = 5;
1438         i2c->adap.algo_data = i2c;
1439         i2c->adap.dev.parent = &dev->dev;
1440 #ifdef CONFIG_OF
1441         i2c->adap.dev.of_node = dev->dev.of_node;
1442 #endif
1443
1444         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1445         i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1446         if (IS_ERR(i2c->reg_base))
1447                 return PTR_ERR(i2c->reg_base);
1448
1449         irq = platform_get_irq(dev, 0);
1450         if (irq < 0)
1451                 return irq;
1452
1453         ret = i2c_pxa_init_recovery(i2c);
1454         if (ret)
1455                 return ret;
1456
1457         ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1458         if (ret > 0)
1459                 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1460         if (ret < 0)
1461                 return ret;
1462
1463         spin_lock_init(&i2c->lock);
1464         init_waitqueue_head(&i2c->wait);
1465
1466         strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1467
1468         i2c->clk = devm_clk_get(&dev->dev, NULL);
1469         if (IS_ERR(i2c->clk)) {
1470                 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1471                 return PTR_ERR(i2c->clk);
1472         }
1473
1474         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1475         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1476         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1477         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1478         i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1479         i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1480
1481         if (i2c_type != REGS_CE4100)
1482                 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1483
1484         if (i2c_type == REGS_PXA910) {
1485                 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1486                 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1487         }
1488
1489         i2c->iobase = res->start;
1490         i2c->iosize = resource_size(res);
1491
1492         i2c->irq = irq;
1493
1494         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1495         i2c->highmode_enter = false;
1496
1497         if (plat) {
1498                 i2c->adap.class = plat->class;
1499         }
1500
1501         if (i2c->high_mode) {
1502                 if (i2c->rate) {
1503                         clk_set_rate(i2c->clk, i2c->rate);
1504                         pr_info("i2c: <%s> set rate to %ld\n",
1505                                 i2c->adap.name, clk_get_rate(i2c->clk));
1506                 } else
1507                         pr_warn("i2c: <%s> clock rate not set\n",
1508                                 i2c->adap.name);
1509         }
1510
1511         clk_prepare_enable(i2c->clk);
1512
1513         if (i2c->use_pio) {
1514                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1515         } else {
1516                 i2c->adap.algo = &i2c_pxa_algorithm;
1517                 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1518                                 IRQF_SHARED | IRQF_NO_SUSPEND,
1519                                 dev_name(&dev->dev), i2c);
1520                 if (ret) {
1521                         dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1522                         goto ereqirq;
1523                 }
1524         }
1525
1526         i2c_pxa_reset(i2c);
1527
1528         ret = i2c_add_numbered_adapter(&i2c->adap);
1529         if (ret < 0)
1530                 goto ereqirq;
1531
1532         platform_set_drvdata(dev, i2c);
1533
1534 #ifdef CONFIG_I2C_PXA_SLAVE
1535         dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1536                 i2c->slave_addr);
1537 #else
1538         dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1539 #endif
1540         return 0;
1541
1542 ereqirq:
1543         clk_disable_unprepare(i2c->clk);
1544         return ret;
1545 }
1546
1547 static int i2c_pxa_remove(struct platform_device *dev)
1548 {
1549         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1550
1551         i2c_del_adapter(&i2c->adap);
1552
1553         clk_disable_unprepare(i2c->clk);
1554
1555         return 0;
1556 }
1557
1558 #ifdef CONFIG_PM
1559 static int i2c_pxa_suspend_noirq(struct device *dev)
1560 {
1561         struct pxa_i2c *i2c = dev_get_drvdata(dev);
1562
1563         clk_disable(i2c->clk);
1564
1565         return 0;
1566 }
1567
1568 static int i2c_pxa_resume_noirq(struct device *dev)
1569 {
1570         struct pxa_i2c *i2c = dev_get_drvdata(dev);
1571
1572         clk_enable(i2c->clk);
1573         i2c_pxa_reset(i2c);
1574
1575         return 0;
1576 }
1577
1578 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1579         .suspend_noirq = i2c_pxa_suspend_noirq,
1580         .resume_noirq = i2c_pxa_resume_noirq,
1581 };
1582
1583 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1584 #else
1585 #define I2C_PXA_DEV_PM_OPS NULL
1586 #endif
1587
1588 static struct platform_driver i2c_pxa_driver = {
1589         .probe          = i2c_pxa_probe,
1590         .remove         = i2c_pxa_remove,
1591         .driver         = {
1592                 .name   = "pxa2xx-i2c",
1593                 .pm     = I2C_PXA_DEV_PM_OPS,
1594                 .of_match_table = i2c_pxa_dt_ids,
1595         },
1596         .id_table       = i2c_pxa_id_table,
1597 };
1598
1599 static int __init i2c_adap_pxa_init(void)
1600 {
1601         return platform_driver_register(&i2c_pxa_driver);
1602 }
1603
1604 static void __exit i2c_adap_pxa_exit(void)
1605 {
1606         platform_driver_unregister(&i2c_pxa_driver);
1607 }
1608
1609 MODULE_LICENSE("GPL");
1610 MODULE_ALIAS("platform:pxa2xx-i2c");
1611
1612 subsys_initcall(i2c_adap_pxa_init);
1613 module_exit(i2c_adap_pxa_exit);