2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
3 Philip Edelbrock <phil@netroedge.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
19 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
20 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
24 Note: we assume there can only be one device, with one or more
26 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
27 For devices supporting multiple ports the i2c_adapter should provide
28 an i2c_algorithm to access them.
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/pci.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/stddef.h>
37 #include <linux/ioport.h>
38 #include <linux/i2c.h>
39 #include <linux/slab.h>
40 #include <linux/dmi.h>
41 #include <linux/acpi.h>
43 #include <linux/mutex.h>
46 /* PIIX4 SMBus address offsets */
47 #define SMBHSTSTS (0 + piix4_smba)
48 #define SMBHSLVSTS (1 + piix4_smba)
49 #define SMBHSTCNT (2 + piix4_smba)
50 #define SMBHSTCMD (3 + piix4_smba)
51 #define SMBHSTADD (4 + piix4_smba)
52 #define SMBHSTDAT0 (5 + piix4_smba)
53 #define SMBHSTDAT1 (6 + piix4_smba)
54 #define SMBBLKDAT (7 + piix4_smba)
55 #define SMBSLVCNT (8 + piix4_smba)
56 #define SMBSHDWCMD (9 + piix4_smba)
57 #define SMBSLVEVT (0xA + piix4_smba)
58 #define SMBSLVDAT (0xC + piix4_smba)
60 /* count for request_region */
63 /* PCI Address Constants */
65 #define SMBHSTCFG 0x0D2
67 #define SMBSHDW1 0x0D4
68 #define SMBSHDW2 0x0D5
72 #define MAX_TIMEOUT 500
76 #define PIIX4_QUICK 0x00
77 #define PIIX4_BYTE 0x04
78 #define PIIX4_BYTE_DATA 0x08
79 #define PIIX4_WORD_DATA 0x0C
80 #define PIIX4_BLOCK_DATA 0x14
82 /* Multi-port constants */
83 #define PIIX4_MAX_ADAPTERS 4
86 #define SB800_PIIX4_SMB_IDX 0xcd6
88 #define KERNCZ_IMC_IDX 0x3e
89 #define KERNCZ_IMC_DATA 0x3f
92 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
93 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
94 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
96 #define SB800_PIIX4_PORT_IDX 0x2c
97 #define SB800_PIIX4_PORT_IDX_ALT 0x2e
98 #define SB800_PIIX4_PORT_IDX_SEL 0x2f
99 #define SB800_PIIX4_PORT_IDX_MASK 0x06
100 #define SB800_PIIX4_PORT_IDX_SHIFT 1
102 /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
103 #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
104 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
105 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
107 /* insmod parameters */
109 /* If force is set to anything different from 0, we forcibly enable the
112 module_param (force, int, 0);
113 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
115 /* If force_addr is set to anything different from 0, we forcibly enable
116 the PIIX4 at the given address. VERY DANGEROUS! */
117 static int force_addr;
118 module_param_hw(force_addr, int, ioport, 0);
119 MODULE_PARM_DESC(force_addr,
120 "Forcibly enable the PIIX4 at the given address. "
121 "EXTREMELY DANGEROUS!");
123 static int srvrworks_csb5_delay;
124 static struct pci_driver piix4_driver;
126 static const struct dmi_system_id piix4_dmi_blacklist[] = {
128 .ident = "Sapphire AM2RD790",
130 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
131 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
135 .ident = "DFI Lanparty UT 790FX",
137 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
138 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
144 /* The IBM entry is in a separate table because we only check it
145 on Intel-based systems */
146 static const struct dmi_system_id piix4_dmi_ibm[] = {
149 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
156 * piix4_mutex_sb800 protects piix4_port_sel_sb800 and the pair
157 * of I/O ports at SB800_PIIX4_SMB_IDX.
159 static DEFINE_MUTEX(piix4_mutex_sb800);
160 static u8 piix4_port_sel_sb800;
161 static u8 piix4_port_mask_sb800;
162 static u8 piix4_port_shift_sb800;
163 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
164 " port 0", " port 2", " port 3", " port 4"
166 static const char *piix4_aux_port_name_sb800 = " port 1";
168 struct i2c_piix4_adapdata {
174 u8 port; /* Port number, shifted */
177 static int piix4_setup(struct pci_dev *PIIX4_dev,
178 const struct pci_device_id *id)
181 unsigned short piix4_smba;
183 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
184 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
185 srvrworks_csb5_delay = 1;
187 /* On some motherboards, it was reported that accessing the SMBus
188 caused severe hardware problems */
189 if (dmi_check_system(piix4_dmi_blacklist)) {
190 dev_err(&PIIX4_dev->dev,
191 "Accessing the SMBus on this system is unsafe!\n");
195 /* Don't access SMBus on IBM systems which get corrupted eeproms */
196 if (dmi_check_system(piix4_dmi_ibm) &&
197 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
198 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
199 "may corrupt your serial eeprom! Refusing to load "
204 /* Determine the address of the SMBus areas */
206 piix4_smba = force_addr & 0xfff0;
209 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
210 piix4_smba &= 0xfff0;
211 if(piix4_smba == 0) {
212 dev_err(&PIIX4_dev->dev, "SMBus base address "
213 "uninitialized - upgrade BIOS or use "
214 "force_addr=0xaddr\n");
219 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
222 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
223 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
228 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
230 /* If force_addr is set, we program the new address here. Just to make
231 sure, we disable the PIIX4 first. */
233 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
234 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
235 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
236 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
237 "new address %04x!\n", piix4_smba);
238 } else if ((temp & 1) == 0) {
240 /* This should never need to be done, but has been
241 * noted that many Dell machines have the SMBus
242 * interface on the PIIX4 disabled!? NOTE: This assumes
243 * I/O space and other allocations WERE done by the
244 * Bios! Don't complain if your hardware does weird
245 * things after enabling this. :') Check for Bios
246 * updates before resorting to this.
248 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
250 dev_notice(&PIIX4_dev->dev,
251 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
253 dev_err(&PIIX4_dev->dev,
254 "SMBus Host Controller not enabled!\n");
255 release_region(piix4_smba, SMBIOSIZE);
260 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
261 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
262 else if ((temp & 0x0E) == 0)
263 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
265 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
266 "(or code out of date)!\n");
268 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
269 dev_info(&PIIX4_dev->dev,
270 "SMBus Host Controller at 0x%x, revision %d\n",
276 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
277 const struct pci_device_id *id, u8 aux)
279 unsigned short piix4_smba;
280 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
281 u8 i2ccfg, i2ccfg_offset = 0x10;
283 /* SB800 and later SMBus does not support forcing address */
284 if (force || force_addr) {
285 dev_err(&PIIX4_dev->dev, "SMBus does not support "
286 "forcing address!\n");
290 /* Determine the address of the SMBus areas */
291 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
292 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
293 PIIX4_dev->revision >= 0x41) ||
294 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
295 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
296 PIIX4_dev->revision >= 0x49))
299 smb_en = (aux) ? 0x28 : 0x2c;
301 mutex_lock(&piix4_mutex_sb800);
302 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
303 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
304 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
305 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
306 mutex_unlock(&piix4_mutex_sb800);
309 smb_en_status = smba_en_lo & 0x10;
310 piix4_smba = smba_en_hi << 8;
314 smb_en_status = smba_en_lo & 0x01;
315 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
318 if (!smb_en_status) {
319 dev_err(&PIIX4_dev->dev,
320 "SMBus Host Controller not enabled!\n");
324 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
327 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
328 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
333 /* Aux SMBus does not support IRQ information */
335 dev_info(&PIIX4_dev->dev,
336 "Auxiliary SMBus Host Controller at 0x%x\n",
341 /* Request the SMBus I2C bus config region */
342 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
343 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
344 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
345 release_region(piix4_smba, SMBIOSIZE);
348 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
349 release_region(piix4_smba + i2ccfg_offset, 1);
352 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
354 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
356 dev_info(&PIIX4_dev->dev,
357 "SMBus Host Controller at 0x%x, revision %d\n",
358 piix4_smba, i2ccfg >> 4);
360 /* Find which register is used for port selection */
361 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) {
362 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
363 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
364 PIIX4_dev->revision >= 0x1F)) {
365 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
366 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
367 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
369 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
370 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
371 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
374 mutex_lock(&piix4_mutex_sb800);
375 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
376 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
377 piix4_port_sel_sb800 = (port_sel & 0x01) ?
378 SB800_PIIX4_PORT_IDX_ALT :
379 SB800_PIIX4_PORT_IDX;
380 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
381 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
382 mutex_unlock(&piix4_mutex_sb800);
385 dev_info(&PIIX4_dev->dev,
386 "Using register 0x%02x for SMBus port selection\n",
387 (unsigned int)piix4_port_sel_sb800);
392 static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
393 const struct pci_device_id *id,
394 unsigned short base_reg_addr)
396 /* Set up auxiliary SMBus controllers found on some
397 * AMD chipsets e.g. SP5100 (SB700 derivative) */
399 unsigned short piix4_smba;
401 /* Read address of auxiliary SMBus controller */
402 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
403 if ((piix4_smba & 1) == 0) {
404 dev_dbg(&PIIX4_dev->dev,
405 "Auxiliary SMBus controller not enabled\n");
409 piix4_smba &= 0xfff0;
410 if (piix4_smba == 0) {
411 dev_dbg(&PIIX4_dev->dev,
412 "Auxiliary SMBus base address uninitialized\n");
416 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
419 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
420 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
421 "already in use!\n", piix4_smba);
425 dev_info(&PIIX4_dev->dev,
426 "Auxiliary SMBus Host Controller at 0x%x\n",
432 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
434 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
435 unsigned short piix4_smba = adapdata->smba;
440 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
441 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
442 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
445 /* Make sure the SMBus host is ready to start transmitting */
446 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
447 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
448 "Resetting...\n", temp);
449 outb_p(temp, SMBHSTSTS);
450 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
451 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
454 dev_dbg(&piix4_adapter->dev, "Successful!\n");
458 /* start the transaction by setting bit 6 */
459 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
461 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
462 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
467 while ((++timeout < MAX_TIMEOUT) &&
468 ((temp = inb_p(SMBHSTSTS)) & 0x01))
471 /* If the SMBus is still busy, we give up */
472 if (timeout == MAX_TIMEOUT) {
473 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
479 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
484 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
485 "locked until next hard reset. (sorry!)\n");
486 /* Clock stops and slave is stuck in mid-transmission */
491 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
494 if (inb_p(SMBHSTSTS) != 0x00)
495 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
497 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
498 dev_err(&piix4_adapter->dev, "Failed reset at end of "
499 "transaction (%02x)\n", temp);
501 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
502 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
503 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
508 /* Return negative errno on error. */
509 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
510 unsigned short flags, char read_write,
511 u8 command, int size, union i2c_smbus_data * data)
513 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
514 unsigned short piix4_smba = adapdata->smba;
519 case I2C_SMBUS_QUICK:
520 outb_p((addr << 1) | read_write,
525 outb_p((addr << 1) | read_write,
527 if (read_write == I2C_SMBUS_WRITE)
528 outb_p(command, SMBHSTCMD);
531 case I2C_SMBUS_BYTE_DATA:
532 outb_p((addr << 1) | read_write,
534 outb_p(command, SMBHSTCMD);
535 if (read_write == I2C_SMBUS_WRITE)
536 outb_p(data->byte, SMBHSTDAT0);
537 size = PIIX4_BYTE_DATA;
539 case I2C_SMBUS_WORD_DATA:
540 outb_p((addr << 1) | read_write,
542 outb_p(command, SMBHSTCMD);
543 if (read_write == I2C_SMBUS_WRITE) {
544 outb_p(data->word & 0xff, SMBHSTDAT0);
545 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
547 size = PIIX4_WORD_DATA;
549 case I2C_SMBUS_BLOCK_DATA:
550 outb_p((addr << 1) | read_write,
552 outb_p(command, SMBHSTCMD);
553 if (read_write == I2C_SMBUS_WRITE) {
554 len = data->block[0];
555 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
557 outb_p(len, SMBHSTDAT0);
558 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
559 for (i = 1; i <= len; i++)
560 outb_p(data->block[i], SMBBLKDAT);
562 size = PIIX4_BLOCK_DATA;
565 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
569 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
571 status = piix4_transaction(adap);
575 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
581 case PIIX4_BYTE_DATA:
582 data->byte = inb_p(SMBHSTDAT0);
584 case PIIX4_WORD_DATA:
585 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
587 case PIIX4_BLOCK_DATA:
588 data->block[0] = inb_p(SMBHSTDAT0);
589 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
591 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
592 for (i = 1; i <= data->block[0]; i++)
593 data->block[i] = inb_p(SMBBLKDAT);
599 static uint8_t piix4_imc_read(uint8_t idx)
601 outb_p(idx, KERNCZ_IMC_IDX);
602 return inb_p(KERNCZ_IMC_DATA);
605 static void piix4_imc_write(uint8_t idx, uint8_t value)
607 outb_p(idx, KERNCZ_IMC_IDX);
608 outb_p(value, KERNCZ_IMC_DATA);
611 static int piix4_imc_sleep(void)
613 int timeout = MAX_TIMEOUT;
615 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
618 /* clear response register */
619 piix4_imc_write(0x82, 0x00);
620 /* request ownership flag */
621 piix4_imc_write(0x83, 0xB4);
622 /* kick off IMC Mailbox command 96 */
623 piix4_imc_write(0x80, 0x96);
626 if (piix4_imc_read(0x82) == 0xfa) {
627 release_region(KERNCZ_IMC_IDX, 2);
630 usleep_range(1000, 2000);
633 release_region(KERNCZ_IMC_IDX, 2);
637 static void piix4_imc_wakeup(void)
639 int timeout = MAX_TIMEOUT;
641 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
644 /* clear response register */
645 piix4_imc_write(0x82, 0x00);
646 /* release ownership flag */
647 piix4_imc_write(0x83, 0xB5);
648 /* kick off IMC Mailbox command 96 */
649 piix4_imc_write(0x80, 0x96);
652 if (piix4_imc_read(0x82) == 0xfa)
654 usleep_range(1000, 2000);
657 release_region(KERNCZ_IMC_IDX, 2);
661 * Handles access to multiple SMBus ports on the SB800.
662 * The port is selected by bits 2:1 of the smb_en register (0x2c).
663 * Returns negative errno on error.
665 * Note: The selected port must be returned to the initial selection to avoid
666 * problems on certain systems.
668 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
669 unsigned short flags, char read_write,
670 u8 command, int size, union i2c_smbus_data *data)
672 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
673 unsigned short piix4_smba = adapdata->smba;
674 int retries = MAX_TIMEOUT;
680 mutex_lock(&piix4_mutex_sb800);
682 /* Request the SMBUS semaphore, avoid conflicts with the IMC */
683 smbslvcnt = inb_p(SMBSLVCNT);
685 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
687 /* Check the semaphore status */
688 smbslvcnt = inb_p(SMBSLVCNT);
689 if (smbslvcnt & 0x10)
692 usleep_range(1000, 2000);
694 /* SMBus is still owned by the IMC, we give up */
696 mutex_unlock(&piix4_mutex_sb800);
701 * Notify the IMC (Integrated Micro Controller) if required.
702 * Among other responsibilities, the IMC is in charge of monitoring
703 * the System fans and temperature sensors, and act accordingly.
704 * All this is done through SMBus and can/will collide
705 * with our transactions if they are long (BLOCK_DATA).
706 * Therefore we need to request the ownership flag during those
709 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
712 ret = piix4_imc_sleep();
716 "IMC base address index region 0x%x already in use.\n",
721 "Failed to communicate with the IMC.\n");
727 /* If IMC communication fails do not retry */
730 "Continuing without IMC notification.\n");
731 adapdata->notify_imc = false;
735 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
736 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
738 port = adapdata->port;
739 if ((smba_en_lo & piix4_port_mask_sb800) != port)
740 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
741 SB800_PIIX4_SMB_IDX + 1);
743 retval = piix4_access(adap, addr, flags, read_write,
744 command, size, data);
746 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
748 /* Release the semaphore */
749 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
751 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
754 mutex_unlock(&piix4_mutex_sb800);
759 static u32 piix4_func(struct i2c_adapter *adapter)
761 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
762 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
763 I2C_FUNC_SMBUS_BLOCK_DATA;
766 static const struct i2c_algorithm smbus_algorithm = {
767 .smbus_xfer = piix4_access,
768 .functionality = piix4_func,
771 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
772 .smbus_xfer = piix4_access_sb800,
773 .functionality = piix4_func,
776 static const struct pci_device_id piix4_ids[] = {
777 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
778 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
779 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
780 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
781 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
782 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
783 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
784 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
785 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
786 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
787 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
788 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
789 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
790 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
791 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
792 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
793 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
794 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
795 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
799 MODULE_DEVICE_TABLE (pci, piix4_ids);
801 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
802 static struct i2c_adapter *piix4_aux_adapter;
804 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
805 bool sb800_main, u8 port, bool notify_imc,
806 const char *name, struct i2c_adapter **padap)
808 struct i2c_adapter *adap;
809 struct i2c_piix4_adapdata *adapdata;
812 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
814 release_region(smba, SMBIOSIZE);
818 adap->owner = THIS_MODULE;
819 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
820 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
823 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
824 if (adapdata == NULL) {
826 release_region(smba, SMBIOSIZE);
830 adapdata->smba = smba;
831 adapdata->sb800_main = sb800_main;
832 adapdata->port = port << piix4_port_shift_sb800;
833 adapdata->notify_imc = notify_imc;
835 /* set up the sysfs linkage to our parent device */
836 adap->dev.parent = &dev->dev;
838 snprintf(adap->name, sizeof(adap->name),
839 "SMBus PIIX4 adapter%s at %04x", name, smba);
841 i2c_set_adapdata(adap, adapdata);
843 retval = i2c_add_adapter(adap);
847 release_region(smba, SMBIOSIZE);
855 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
858 struct i2c_piix4_adapdata *adapdata;
862 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) {
863 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
864 piix4_main_port_names_sb800[port],
865 &piix4_main_adapters[port]);
874 "Error setting up SB800 adapters. Unregistering!\n");
875 while (--port >= 0) {
876 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
877 if (adapdata->smba) {
878 i2c_del_adapter(piix4_main_adapters[port]);
880 kfree(piix4_main_adapters[port]);
881 piix4_main_adapters[port] = NULL;
888 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
891 bool is_sb800 = false;
893 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
894 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
895 dev->revision >= 0x40) ||
896 dev->vendor == PCI_VENDOR_ID_AMD) {
897 bool notify_imc = false;
900 if (!request_region(SB800_PIIX4_SMB_IDX, 2, "smba_idx")) {
902 "SMBus base address index region 0x%x already in use!\n",
903 SB800_PIIX4_SMB_IDX);
907 if (dev->vendor == PCI_VENDOR_ID_AMD &&
908 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
912 * Detect if IMC is active or not, this method is
913 * described on coreboot's AMD IMC notes
915 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
921 /* base address location etc changed in SB800 */
922 retval = piix4_setup_sb800(dev, id, 0);
924 release_region(SB800_PIIX4_SMB_IDX, 2);
929 * Try to register multiplexed main SMBus adapter,
930 * give up if we can't
932 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
934 release_region(SB800_PIIX4_SMB_IDX, 2);
938 retval = piix4_setup(dev, id);
942 /* Try to register main SMBus adapter, give up if we can't */
943 retval = piix4_add_adapter(dev, retval, false, 0, false, "",
944 &piix4_main_adapters[0]);
949 /* Check for auxiliary SMBus on some AMD chipsets */
952 if (dev->vendor == PCI_VENDOR_ID_ATI &&
953 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
954 if (dev->revision < 0x40) {
955 retval = piix4_setup_aux(dev, id, 0x58);
957 /* SB800 added aux bus too */
958 retval = piix4_setup_sb800(dev, id, 1);
962 if (dev->vendor == PCI_VENDOR_ID_AMD &&
963 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
964 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
965 retval = piix4_setup_sb800(dev, id, 1);
969 /* Try to add the aux adapter if it exists,
970 * piix4_add_adapter will clean up if this fails */
971 piix4_add_adapter(dev, retval, false, 0, false,
972 is_sb800 ? piix4_aux_port_name_sb800 : "",
979 static void piix4_adap_remove(struct i2c_adapter *adap)
981 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
983 if (adapdata->smba) {
984 i2c_del_adapter(adap);
985 if (adapdata->port == (0 << 1)) {
986 release_region(adapdata->smba, SMBIOSIZE);
987 if (adapdata->sb800_main)
988 release_region(SB800_PIIX4_SMB_IDX, 2);
995 static void piix4_remove(struct pci_dev *dev)
997 int port = PIIX4_MAX_ADAPTERS;
999 while (--port >= 0) {
1000 if (piix4_main_adapters[port]) {
1001 piix4_adap_remove(piix4_main_adapters[port]);
1002 piix4_main_adapters[port] = NULL;
1006 if (piix4_aux_adapter) {
1007 piix4_adap_remove(piix4_aux_adapter);
1008 piix4_aux_adapter = NULL;
1012 static struct pci_driver piix4_driver = {
1013 .name = "piix4_smbus",
1014 .id_table = piix4_ids,
1015 .probe = piix4_probe,
1016 .remove = piix4_remove,
1019 module_pci_driver(piix4_driver);
1021 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
1022 "Philip Edelbrock <phil@netroedge.com>");
1023 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1024 MODULE_LICENSE("GPL");