1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/project/i2c/overview)
6 * Peter Korsgaard <peter@korsgaard.com>
8 * Support for the GRLIB port of the controller by
9 * Andreas Larsson <andreas@gaisler.com>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/interrupt.h>
21 #include <linux/wait.h>
22 #include <linux/platform_data/i2c-ocores.h>
23 #include <linux/slab.h>
25 #include <linux/log2.h>
26 #include <linux/spinlock.h>
27 #include <linux/jiffies.h>
30 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
31 * can't run in parallel.
39 wait_queue_head_t wait;
40 struct i2c_adapter adap;
44 int state; /* see STATE_ */
45 spinlock_t process_lock;
49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
50 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
54 #define OCI2C_PRELOW 0
55 #define OCI2C_PREHIGH 1
56 #define OCI2C_CONTROL 2
58 #define OCI2C_CMD 4 /* write only */
59 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
61 #define OCI2C_CTRL_IEN 0x40
62 #define OCI2C_CTRL_EN 0x80
64 #define OCI2C_CMD_START 0x91
65 #define OCI2C_CMD_STOP 0x41
66 #define OCI2C_CMD_READ 0x21
67 #define OCI2C_CMD_WRITE 0x11
68 #define OCI2C_CMD_READ_ACK 0x21
69 #define OCI2C_CMD_READ_NACK 0x29
70 #define OCI2C_CMD_IACK 0x01
72 #define OCI2C_STAT_IF 0x01
73 #define OCI2C_STAT_TIP 0x02
74 #define OCI2C_STAT_ARBLOST 0x20
75 #define OCI2C_STAT_BUSY 0x40
76 #define OCI2C_STAT_NACK 0x80
86 #define TYPE_SIFIVE_REV0 2
88 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
90 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
92 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
95 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
97 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
100 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
102 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
105 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
107 iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
110 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
112 iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
115 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
117 return ioread8(i2c->base + (reg << i2c->reg_shift));
120 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
122 return ioread16(i2c->base + (reg << i2c->reg_shift));
125 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
127 return ioread32(i2c->base + (reg << i2c->reg_shift));
130 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
132 return ioread16be(i2c->base + (reg << i2c->reg_shift));
135 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
137 return ioread32be(i2c->base + (reg << i2c->reg_shift));
140 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
142 outb(value, i2c->iobase + reg);
145 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
147 return inb(i2c->iobase + reg);
150 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
152 i2c->setreg(i2c, reg, value);
155 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
157 return i2c->getreg(i2c, reg);
160 static void ocores_process(struct ocores_i2c *i2c, u8 stat)
162 struct i2c_msg *msg = i2c->msg;
166 * If we spin here is because we are in timeout, so we are going
167 * to be in STATE_ERROR. See ocores_process_timeout()
169 spin_lock_irqsave(&i2c->process_lock, flags);
171 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
172 /* stop has been sent */
173 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
179 if (stat & OCI2C_STAT_ARBLOST) {
180 i2c->state = STATE_ERROR;
181 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
185 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
187 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
189 if (stat & OCI2C_STAT_NACK) {
190 i2c->state = STATE_ERROR;
191 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
195 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
199 if (i2c->pos == msg->len) {
205 if (i2c->nmsgs) { /* end? */
207 if (!(msg->flags & I2C_M_NOSTART)) {
208 u8 addr = i2c_8bit_addr_from_msg(msg);
210 i2c->state = STATE_START;
212 oc_setreg(i2c, OCI2C_DATA, addr);
213 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
216 i2c->state = (msg->flags & I2C_M_RD)
217 ? STATE_READ : STATE_WRITE;
219 i2c->state = STATE_DONE;
220 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
225 if (i2c->state == STATE_READ) {
226 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
227 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
229 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
230 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
234 spin_unlock_irqrestore(&i2c->process_lock, flags);
237 static irqreturn_t ocores_isr(int irq, void *dev_id)
239 struct ocores_i2c *i2c = dev_id;
240 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
242 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
243 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
245 } else if (!(stat & OCI2C_STAT_IF)) {
248 ocores_process(i2c, stat);
254 * Process timeout event
255 * @i2c: ocores I2C device instance
257 static void ocores_process_timeout(struct ocores_i2c *i2c)
261 spin_lock_irqsave(&i2c->process_lock, flags);
262 i2c->state = STATE_ERROR;
263 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
264 spin_unlock_irqrestore(&i2c->process_lock, flags);
268 * Wait until something change in a given register
269 * @i2c: ocores I2C device instance
270 * @reg: register to query
271 * @mask: bitmask to apply on register value
272 * @val: expected result
273 * @timeout: timeout in jiffies
275 * Timeout is necessary to avoid to stay here forever when the chip
276 * does not answer correctly.
278 * Return: 0 on success, -ETIMEDOUT on timeout
280 static int ocores_wait(struct ocores_i2c *i2c,
281 int reg, u8 mask, u8 val,
282 const unsigned long timeout)
286 j = jiffies + timeout;
288 u8 status = oc_getreg(i2c, reg);
290 if ((status & mask) == val)
293 if (time_after(jiffies, j))
300 * Wait until is possible to process some data
301 * @i2c: ocores I2C device instance
303 * Used when the device is in polling mode (interrupts disabled).
305 * Return: 0 on success, -ETIMEDOUT on timeout
307 static int ocores_poll_wait(struct ocores_i2c *i2c)
312 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
313 /* transfer is over */
314 mask = OCI2C_STAT_BUSY;
316 /* on going transfer */
317 mask = OCI2C_STAT_TIP;
319 * We wait for the data to be transferred (8bit),
320 * then we start polling on the ACK/NACK bit
322 udelay((8 * 1000) / i2c->bus_clock_khz);
326 * once we are here we expect to get the expected result immediately
327 * so if after 1ms we timeout then something is broken.
329 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
331 dev_warn(i2c->adap.dev.parent,
332 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
338 * It handles an IRQ-less transfer
339 * @i2c: ocores I2C device instance
341 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
342 * (only that IRQ are not produced). This means that we can re-use entirely
343 * ocores_isr(), we just add our polling code around it.
345 * It can run in atomic context
347 * Return: 0 on success, -ETIMEDOUT on timeout
349 static int ocores_process_polling(struct ocores_i2c *i2c)
355 err = ocores_poll_wait(i2c);
359 ret = ocores_isr(-1, i2c);
361 break; /* all messages have been transferred */
363 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
364 if (i2c->state == STATE_DONE)
372 static int ocores_xfer_core(struct ocores_i2c *i2c,
373 struct i2c_msg *msgs, int num,
379 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
381 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
383 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
388 i2c->state = STATE_START;
390 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
391 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
394 ret = ocores_process_polling(i2c);
396 if (wait_event_timeout(i2c->wait,
397 (i2c->state == STATE_ERROR) ||
398 (i2c->state == STATE_DONE), HZ) == 0)
402 ocores_process_timeout(i2c);
406 return (i2c->state == STATE_DONE) ? num : -EIO;
409 static int ocores_xfer_polling(struct i2c_adapter *adap,
410 struct i2c_msg *msgs, int num)
412 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
415 static int ocores_xfer(struct i2c_adapter *adap,
416 struct i2c_msg *msgs, int num)
418 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
421 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
425 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
427 /* make sure the device is disabled */
428 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
429 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
431 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
432 prescale = clamp(prescale, 0, 0xffff);
434 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
435 if (abs(diff) > i2c->bus_clock_khz / 10) {
437 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
438 i2c->ip_clock_khz, i2c->bus_clock_khz);
442 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
443 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
445 /* Init the device */
446 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
447 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
453 static u32 ocores_func(struct i2c_adapter *adap)
455 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
458 static struct i2c_algorithm ocores_algorithm = {
459 .master_xfer = ocores_xfer,
460 .master_xfer_atomic = ocores_xfer_polling,
461 .functionality = ocores_func,
464 static const struct i2c_adapter ocores_adapter = {
465 .owner = THIS_MODULE,
466 .name = "i2c-ocores",
467 .class = I2C_CLASS_DEPRECATED,
468 .algo = &ocores_algorithm,
471 static const struct of_device_id ocores_i2c_match[] = {
473 .compatible = "opencores,i2c-ocores",
474 .data = (void *)TYPE_OCORES,
477 .compatible = "aeroflexgaisler,i2cmst",
478 .data = (void *)TYPE_GRLIB,
481 .compatible = "sifive,fu540-c000-i2c",
482 .data = (void *)TYPE_SIFIVE_REV0,
485 .compatible = "sifive,i2c0",
486 .data = (void *)TYPE_SIFIVE_REV0,
490 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
494 * Read and write functions for the GRLIB port of the controller. Registers are
495 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
496 * register. The subsequent registers have their offsets decreased accordingly.
498 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
503 if (reg != OCI2C_PRELOW)
505 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
506 if (reg == OCI2C_PREHIGH)
507 return (u8)(rd >> 8);
512 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
517 if (reg != OCI2C_PRELOW)
519 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
520 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
521 if (reg == OCI2C_PRELOW)
522 wr = (curr & 0xff00) | value;
524 wr = (((u32)value) << 8) | (curr & 0xff);
528 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
531 static int ocores_i2c_of_probe(struct platform_device *pdev,
532 struct ocores_i2c *i2c)
534 struct device_node *np = pdev->dev.of_node;
535 const struct of_device_id *match;
538 bool clock_frequency_present;
540 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
541 /* no 'reg-shift', check for deprecated 'regstep' */
542 if (!of_property_read_u32(np, "regstep", &val)) {
543 if (!is_power_of_2(val)) {
544 dev_err(&pdev->dev, "invalid regstep %d\n",
548 i2c->reg_shift = ilog2(val);
550 "regstep property deprecated, use reg-shift\n");
554 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
556 i2c->bus_clock_khz = 100;
558 i2c->clk = devm_clk_get(&pdev->dev, NULL);
560 if (!IS_ERR(i2c->clk)) {
561 int ret = clk_prepare_enable(i2c->clk);
565 "clk_prepare_enable failed: %d\n", ret);
568 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
569 if (clock_frequency_present)
570 i2c->bus_clock_khz = clock_frequency / 1000;
573 if (i2c->ip_clock_khz == 0) {
574 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
576 if (!clock_frequency_present) {
578 "Missing required parameter 'opencores,ip-clock-frequency'\n");
579 clk_disable_unprepare(i2c->clk);
582 i2c->ip_clock_khz = clock_frequency / 1000;
584 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
586 i2c->ip_clock_khz = val / 1000;
587 if (clock_frequency_present)
588 i2c->bus_clock_khz = clock_frequency / 1000;
592 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
595 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
596 if (match && (long)match->data == TYPE_GRLIB) {
597 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
598 i2c->setreg = oc_setreg_grlib;
599 i2c->getreg = oc_getreg_grlib;
605 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
608 static int ocores_i2c_probe(struct platform_device *pdev)
610 struct ocores_i2c *i2c;
611 struct ocores_i2c_platform_data *pdata;
612 const struct of_device_id *match;
613 struct resource *res;
618 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
622 spin_lock_init(&i2c->process_lock);
624 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 i2c->base = devm_ioremap_resource(&pdev->dev, res);
627 if (IS_ERR(i2c->base))
628 return PTR_ERR(i2c->base);
630 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
633 i2c->iobase = res->start;
634 if (!devm_request_region(&pdev->dev, res->start,
637 dev_err(&pdev->dev, "Can't get I/O resource.\n");
640 i2c->setreg = oc_setreg_io_8;
641 i2c->getreg = oc_getreg_io_8;
644 pdata = dev_get_platdata(&pdev->dev);
646 i2c->reg_shift = pdata->reg_shift;
647 i2c->reg_io_width = pdata->reg_io_width;
648 i2c->ip_clock_khz = pdata->clock_khz;
650 i2c->bus_clock_khz = pdata->bus_khz;
652 i2c->bus_clock_khz = 100;
654 ret = ocores_i2c_of_probe(pdev, i2c);
659 if (i2c->reg_io_width == 0)
660 i2c->reg_io_width = 1; /* Set to default value */
662 if (!i2c->setreg || !i2c->getreg) {
663 bool be = pdata ? pdata->big_endian :
664 of_device_is_big_endian(pdev->dev.of_node);
666 switch (i2c->reg_io_width) {
668 i2c->setreg = oc_setreg_8;
669 i2c->getreg = oc_getreg_8;
673 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
674 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
678 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
679 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
683 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
690 init_waitqueue_head(&i2c->wait);
692 irq = platform_get_irq(pdev, 0);
694 ocores_algorithm.master_xfer = ocores_xfer_polling;
697 * Set in OCORES_FLAG_BROKEN_IRQ to enable workaround for
698 * FU540-C000 SoC in polling mode.
700 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
701 if (match && (long)match->data == TYPE_SIFIVE_REV0)
702 i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
708 if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
709 ret = devm_request_any_context_irq(&pdev->dev, irq,
713 dev_err(&pdev->dev, "Cannot claim IRQ\n");
718 ret = ocores_init(&pdev->dev, i2c);
722 /* hook up driver to tree */
723 platform_set_drvdata(pdev, i2c);
724 i2c->adap = ocores_adapter;
725 i2c_set_adapdata(&i2c->adap, i2c);
726 i2c->adap.dev.parent = &pdev->dev;
727 i2c->adap.dev.of_node = pdev->dev.of_node;
729 /* add i2c adapter to i2c tree */
730 ret = i2c_add_adapter(&i2c->adap);
734 /* add in known devices to the bus */
736 for (i = 0; i < pdata->num_devices; i++)
737 i2c_new_client_device(&i2c->adap, pdata->devices + i);
743 clk_disable_unprepare(i2c->clk);
747 static int ocores_i2c_remove(struct platform_device *pdev)
749 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
750 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
752 /* disable i2c logic */
753 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
754 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
756 /* remove adapter & data */
757 i2c_del_adapter(&i2c->adap);
759 if (!IS_ERR(i2c->clk))
760 clk_disable_unprepare(i2c->clk);
765 #ifdef CONFIG_PM_SLEEP
766 static int ocores_i2c_suspend(struct device *dev)
768 struct ocores_i2c *i2c = dev_get_drvdata(dev);
769 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
771 /* make sure the device is disabled */
772 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
773 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
775 if (!IS_ERR(i2c->clk))
776 clk_disable_unprepare(i2c->clk);
780 static int ocores_i2c_resume(struct device *dev)
782 struct ocores_i2c *i2c = dev_get_drvdata(dev);
784 if (!IS_ERR(i2c->clk)) {
786 int ret = clk_prepare_enable(i2c->clk);
790 "clk_prepare_enable failed: %d\n", ret);
793 rate = clk_get_rate(i2c->clk) / 1000;
795 i2c->ip_clock_khz = rate;
797 return ocores_init(dev, i2c);
800 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
801 #define OCORES_I2C_PM (&ocores_i2c_pm)
803 #define OCORES_I2C_PM NULL
806 static struct platform_driver ocores_i2c_driver = {
807 .probe = ocores_i2c_probe,
808 .remove = ocores_i2c_remove,
810 .name = "ocores-i2c",
811 .of_match_table = ocores_i2c_match,
816 module_platform_driver(ocores_i2c_driver);
818 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
819 MODULE_DESCRIPTION("OpenCores I2C bus driver");
820 MODULE_LICENSE("GPL");
821 MODULE_ALIAS("platform:ocores-i2c");