drivers/i2c/busses/i2c-npcm7xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nuvoton NPCM7xx I2C Controller driver
   4  *
   5  * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/errno.h>
  11 #include <linux/i2c.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/irq.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22
  23 enum i2c_mode {
  24         I2C_MASTER,
  25         I2C_SLAVE,
  26 };
  27
  28 /*
  29  * External I2C Interface driver xfer indication values, which indicate status
  30  * of the bus.
  31  */
  32 enum i2c_state_ind {
  33         I2C_NO_STATUS_IND = 0,
  34         I2C_SLAVE_RCV_IND,
  35         I2C_SLAVE_XMIT_IND,
  36         I2C_SLAVE_XMIT_MISSING_DATA_IND,
  37         I2C_SLAVE_RESTART_IND,
  38         I2C_SLAVE_DONE_IND,
  39         I2C_MASTER_DONE_IND,
  40         I2C_NACK_IND,
  41         I2C_BUS_ERR_IND,
  42         I2C_WAKE_UP_IND,
  43         I2C_BLOCK_BYTES_ERR_IND,
  44         I2C_SLAVE_RCV_MISSING_DATA_IND,
  45 };
  46
  47 /*
  48  * Operation type values (used to define the operation currently running)
  49  * module is interrupt driven, on each interrupt the current operation is
  50  * checked to see if the module is currently reading or writing.
  51  */
  52 enum i2c_oper {
  53         I2C_NO_OPER = 0,
  54         I2C_WRITE_OPER,
  55         I2C_READ_OPER,
  56 };
  57
  58 /* I2C Bank (module had 2 banks of registers) */
  59 enum i2c_bank {
  60         I2C_BANK_0 = 0,
  61         I2C_BANK_1,
  62 };
  63
  64 /* Internal I2C states values (for the I2C module state machine). */
  65 enum i2c_state {
  66         I2C_DISABLE = 0,
  67         I2C_IDLE,
  68         I2C_MASTER_START,
  69         I2C_SLAVE_MATCH,
  70         I2C_OPER_STARTED,
  71         I2C_STOP_PENDING,
  72 };
  73
  74 #if IS_ENABLED(CONFIG_I2C_SLAVE)
  75 /* Module supports setting multiple own slave addresses */
  76 enum i2c_addr {
  77         I2C_SLAVE_ADDR1 = 0,
  78         I2C_SLAVE_ADDR2,
  79         I2C_SLAVE_ADDR3,
  80         I2C_SLAVE_ADDR4,
  81         I2C_SLAVE_ADDR5,
  82         I2C_SLAVE_ADDR6,
  83         I2C_SLAVE_ADDR7,
  84         I2C_SLAVE_ADDR8,
  85         I2C_SLAVE_ADDR9,
  86         I2C_SLAVE_ADDR10,
  87         I2C_GC_ADDR,
  88         I2C_ARP_ADDR,
  89 };
  90 #endif
  91
  92 /* init register and default value required to enable module */
  93 #define NPCM_I2CSEGCTL                  0xE4
  94 #define NPCM_I2CSEGCTL_INIT_VAL         0x0333F000
  95
  96 /* Common regs */
  97 #define NPCM_I2CSDA                     0x00
  98 #define NPCM_I2CST                      0x02
  99 #define NPCM_I2CCST                     0x04
 100 #define NPCM_I2CCTL1                    0x06
 101 #define NPCM_I2CADDR1                   0x08
 102 #define NPCM_I2CCTL2                    0x0A
 103 #define NPCM_I2CADDR2                   0x0C
 104 #define NPCM_I2CCTL3                    0x0E
 105 #define NPCM_I2CCST2                    0x18
 106 #define NPCM_I2CCST3                    0x19
 107 #define I2C_VER                         0x1F
 108
 109 /*BANK0 regs*/
 110 #define NPCM_I2CADDR3                   0x10
 111 #define NPCM_I2CADDR7                   0x11
 112 #define NPCM_I2CADDR4                   0x12
 113 #define NPCM_I2CADDR8                   0x13
 114 #define NPCM_I2CADDR5                   0x14
 115 #define NPCM_I2CADDR9                   0x15
 116 #define NPCM_I2CADDR6                   0x16
 117 #define NPCM_I2CADDR10                  0x17
 118
 119 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 120 /*
 121  * npcm_i2caddr array:
 122  * The module supports having multiple own slave addresses.
 123  * Since the addr regs are sprinkled all over the address space,
 124  * use this array to get the address or each register.
 125  */
 126 #define I2C_NUM_OWN_ADDR 2
 127 #define I2C_NUM_OWN_ADDR_SUPPORTED 2
 128
 129 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
 130         NPCM_I2CADDR1, NPCM_I2CADDR2,
 131 };
 132 #endif
 133
 134 #define NPCM_I2CCTL4                    0x1A
 135 #define NPCM_I2CCTL5                    0x1B
 136 #define NPCM_I2CSCLLT                   0x1C /* SCL Low Time */
 137 #define NPCM_I2CFIF_CTL                 0x1D /* FIFO Control */
 138 #define NPCM_I2CSCLHT                   0x1E /* SCL High Time */
 139
 140 /* BANK 1 regs */
 141 #define NPCM_I2CFIF_CTS                 0x10 /* Both FIFOs Control and Status */
 142 #define NPCM_I2CTXF_CTL                 0x12 /* Tx-FIFO Control */
 143 #define NPCM_I2CT_OUT                   0x14 /* Bus T.O. */
 144 #define NPCM_I2CPEC                     0x16 /* PEC Data */
 145 #define NPCM_I2CTXF_STS                 0x1A /* Tx-FIFO Status */
 146 #define NPCM_I2CRXF_STS                 0x1C /* Rx-FIFO Status */
 147 #define NPCM_I2CRXF_CTL                 0x1E /* Rx-FIFO Control */
 148
 149 /* NPCM_I2CST reg fields */
 150 #define NPCM_I2CST_XMIT                 BIT(0)
 151 #define NPCM_I2CST_MASTER               BIT(1)
 152 #define NPCM_I2CST_NMATCH               BIT(2)
 153 #define NPCM_I2CST_STASTR               BIT(3)
 154 #define NPCM_I2CST_NEGACK               BIT(4)
 155 #define NPCM_I2CST_BER                  BIT(5)
 156 #define NPCM_I2CST_SDAST                BIT(6)
 157 #define NPCM_I2CST_SLVSTP               BIT(7)
 158
 159 /* NPCM_I2CCST reg fields */
 160 #define NPCM_I2CCST_BUSY                BIT(0)
 161 #define NPCM_I2CCST_BB                  BIT(1)
 162 #define NPCM_I2CCST_MATCH               BIT(2)
 163 #define NPCM_I2CCST_GCMATCH             BIT(3)
 164 #define NPCM_I2CCST_TSDA                BIT(4)
 165 #define NPCM_I2CCST_TGSCL               BIT(5)
 166 #define NPCM_I2CCST_MATCHAF             BIT(6)
 167 #define NPCM_I2CCST_ARPMATCH            BIT(7)
 168
 169 /* NPCM_I2CCTL1 reg fields */
 170 #define NPCM_I2CCTL1_START              BIT(0)
 171 #define NPCM_I2CCTL1_STOP               BIT(1)
 172 #define NPCM_I2CCTL1_INTEN              BIT(2)
 173 #define NPCM_I2CCTL1_EOBINTE            BIT(3)
 174 #define NPCM_I2CCTL1_ACK                BIT(4)
 175 #define NPCM_I2CCTL1_GCMEN              BIT(5)
 176 #define NPCM_I2CCTL1_NMINTE             BIT(6)
 177 #define NPCM_I2CCTL1_STASTRE            BIT(7)
 178
 179 /* RW1S fields (inside a RW reg): */
 180 #define NPCM_I2CCTL1_RWS   \
 181         (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
 182
 183 /* npcm_i2caddr reg fields */
 184 #define NPCM_I2CADDR_A                  GENMASK(6, 0)
 185 #define NPCM_I2CADDR_SAEN               BIT(7)
 186
 187 /* NPCM_I2CCTL2 reg fields */
 188 #define I2CCTL2_ENABLE                  BIT(0)
 189 #define I2CCTL2_SCLFRQ6_0               GENMASK(7, 1)
 190
 191 /* NPCM_I2CCTL3 reg fields */
 192 #define I2CCTL3_SCLFRQ8_7               GENMASK(1, 0)
 193 #define I2CCTL3_ARPMEN                  BIT(2)
 194 #define I2CCTL3_IDL_START               BIT(3)
 195 #define I2CCTL3_400K_MODE               BIT(4)
 196 #define I2CCTL3_BNK_SEL                 BIT(5)
 197 #define I2CCTL3_SDA_LVL                 BIT(6)
 198 #define I2CCTL3_SCL_LVL                 BIT(7)
 199
 200 /* NPCM_I2CCST2 reg fields */
 201 #define NPCM_I2CCST2_MATCHA1F           BIT(0)
 202 #define NPCM_I2CCST2_MATCHA2F           BIT(1)
 203 #define NPCM_I2CCST2_MATCHA3F           BIT(2)
 204 #define NPCM_I2CCST2_MATCHA4F           BIT(3)
 205 #define NPCM_I2CCST2_MATCHA5F           BIT(4)
 206 #define NPCM_I2CCST2_MATCHA6F           BIT(5)
 207 #define NPCM_I2CCST2_MATCHA7F           BIT(5)
 208 #define NPCM_I2CCST2_INTSTS             BIT(7)
 209
 210 /* NPCM_I2CCST3 reg fields */
 211 #define NPCM_I2CCST3_MATCHA8F           BIT(0)
 212 #define NPCM_I2CCST3_MATCHA9F           BIT(1)
 213 #define NPCM_I2CCST3_MATCHA10F          BIT(2)
 214 #define NPCM_I2CCST3_EO_BUSY            BIT(7)
 215
 216 /* NPCM_I2CCTL4 reg fields */
 217 #define I2CCTL4_HLDT                    GENMASK(5, 0)
 218 #define I2CCTL4_LVL_WE                  BIT(7)
 219
 220 /* NPCM_I2CCTL5 reg fields */
 221 #define I2CCTL5_DBNCT                   GENMASK(3, 0)
 222
 223 /* NPCM_I2CFIF_CTS reg fields */
 224 #define NPCM_I2CFIF_CTS_RXF_TXE         BIT(1)
 225 #define NPCM_I2CFIF_CTS_RFTE_IE         BIT(3)
 226 #define NPCM_I2CFIF_CTS_CLR_FIFO        BIT(6)
 227 #define NPCM_I2CFIF_CTS_SLVRSTR         BIT(7)
 228
 229 /* NPCM_I2CTXF_CTL reg fields */
 230 #define NPCM_I2CTXF_CTL_TX_THR          GENMASK(4, 0)
 231 #define NPCM_I2CTXF_CTL_THR_TXIE        BIT(6)
 232
 233 /* NPCM_I2CT_OUT reg fields */
 234 #define NPCM_I2CT_OUT_TO_CKDIV          GENMASK(5, 0)
 235 #define NPCM_I2CT_OUT_T_OUTIE           BIT(6)
 236 #define NPCM_I2CT_OUT_T_OUTST           BIT(7)
 237
 238 /* NPCM_I2CTXF_STS reg fields */
 239 #define NPCM_I2CTXF_STS_TX_BYTES        GENMASK(4, 0)
 240 #define NPCM_I2CTXF_STS_TX_THST         BIT(6)
 241
 242 /* NPCM_I2CRXF_STS reg fields */
 243 #define NPCM_I2CRXF_STS_RX_BYTES        GENMASK(4, 0)
 244 #define NPCM_I2CRXF_STS_RX_THST         BIT(6)
 245
 246 /* NPCM_I2CFIF_CTL reg fields */
 247 #define NPCM_I2CFIF_CTL_FIFO_EN         BIT(4)
 248
 249 /* NPCM_I2CRXF_CTL reg fields */
 250 #define NPCM_I2CRXF_CTL_RX_THR          GENMASK(4, 0)
 251 #define NPCM_I2CRXF_CTL_LAST_PEC        BIT(5)
 252 #define NPCM_I2CRXF_CTL_THR_RXIE        BIT(6)
 253
 254 #define I2C_HW_FIFO_SIZE                16
 255
 256 /* I2C_VER reg fields */
 257 #define I2C_VER_VERSION                 GENMASK(6, 0)
 258 #define I2C_VER_FIFO_EN                 BIT(7)
 259
 260 /* stall/stuck timeout in us */
 261 #define DEFAULT_STALL_COUNT             25
 262
 263 /* SCLFRQ field position */
 264 #define SCLFRQ_0_TO_6                   GENMASK(6, 0)
 265 #define SCLFRQ_7_TO_8                   GENMASK(8, 7)
 266
 267 /* supported clk settings. values in Hz. */
 268 #define I2C_FREQ_MIN_HZ                 10000
 269 #define I2C_FREQ_MAX_HZ                 I2C_MAX_FAST_MODE_PLUS_FREQ
 270
 271 /* Status of one I2C module */
 272 struct npcm_i2c {
 273         struct i2c_adapter adap;
 274         struct device *dev;
 275         unsigned char __iomem *reg;
 276         spinlock_t lock;   /* IRQ synchronization */
 277         struct completion cmd_complete;
 278         int cmd_err;
 279         struct i2c_msg *msgs;
 280         int msgs_num;
 281         int num;
 282         u32 apb_clk;
 283         struct i2c_bus_recovery_info rinfo;
 284         enum i2c_state state;
 285         enum i2c_oper operation;
 286         enum i2c_mode master_or_slave;
 287         enum i2c_state_ind stop_ind;
 288         u8 dest_addr;
 289         u8 *rd_buf;
 290         u16 rd_size;
 291         u16 rd_ind;
 292         u8 *wr_buf;
 293         u16 wr_size;
 294         u16 wr_ind;
 295         bool fifo_use;
 296         u16 PEC_mask; /* PEC bit mask per slave address */
 297         bool PEC_use;
 298         bool read_block_use;
 299         unsigned long int_time_stamp;
 300         unsigned long bus_freq; /* in Hz */
 301 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 302         u8 own_slave_addr;
 303         struct i2c_client *slave;
 304         int slv_rd_size;
 305         int slv_rd_ind;
 306         int slv_wr_size;
 307         int slv_wr_ind;
 308         u8 slv_rd_buf[I2C_HW_FIFO_SIZE];
 309         u8 slv_wr_buf[I2C_HW_FIFO_SIZE];
 310 #endif
 311         struct dentry *debugfs; /* debugfs device directory */
 312         u64 ber_cnt;
 313         u64 rec_succ_cnt;
 314         u64 rec_fail_cnt;
 315         u64 nack_cnt;
 316         u64 timeout_cnt;
 317 };
 318
 319 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
 320                                         enum i2c_bank bank)
 321 {
 322         u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 323
 324         if (bank == I2C_BANK_0)
 325                 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
 326         else
 327                 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
 328         iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 329 }
 330
 331 static void npcm_i2c_init_params(struct npcm_i2c *bus)
 332 {
 333         bus->stop_ind = I2C_NO_STATUS_IND;
 334         bus->rd_size = 0;
 335         bus->wr_size = 0;
 336         bus->rd_ind = 0;
 337         bus->wr_ind = 0;
 338         bus->read_block_use = false;
 339         bus->int_time_stamp = 0;
 340         bus->PEC_use = false;
 341         bus->PEC_mask = 0;
 342 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 343         if (bus->slave)
 344                 bus->master_or_slave = I2C_SLAVE;
 345 #endif
 346 }
 347
 348 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
 349 {
 350         iowrite8(data, bus->reg + NPCM_I2CSDA);
 351 }
 352
 353 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
 354 {
 355         return ioread8(bus->reg + NPCM_I2CSDA);
 356 }
 357
 358 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
 359 {
 360         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 361
 362         return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 363 }
 364
 365 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
 366 {
 367         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 368
 369         return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 370 }
 371
 372 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
 373 {
 374         if (bus->operation == I2C_READ_OPER)
 375                 return bus->rd_ind;
 376         if (bus->operation == I2C_WRITE_OPER)
 377                 return bus->wr_ind;
 378         return 0;
 379 }
 380
 381 /* quick protocol (just address) */
 382 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
 383 {
 384         return bus->wr_size == 0 && bus->rd_size == 0;
 385 }
 386
 387 static void npcm_i2c_disable(struct npcm_i2c *bus)
 388 {
 389         u8 i2cctl2;
 390
 391 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 392         int i;
 393
 394         /* Slave addresses removal */
 395         for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
 396                 iowrite8(0, bus->reg + npcm_i2caddr[i]);
 397
 398 #endif
 399         /* Disable module */
 400         i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 401         i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
 402         iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 403
 404         bus->state = I2C_DISABLE;
 405 }
 406
 407 static void npcm_i2c_enable(struct npcm_i2c *bus)
 408 {
 409         u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 410
 411         i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
 412         iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 413         bus->state = I2C_IDLE;
 414 }
 415
 416 /* enable\disable end of busy (EOB) interrupts */
 417 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
 418 {
 419         u8 val;
 420
 421         /* Clear EO_BUSY pending bit: */
 422         val = ioread8(bus->reg + NPCM_I2CCST3);
 423         val = val | NPCM_I2CCST3_EO_BUSY;
 424         iowrite8(val, bus->reg + NPCM_I2CCST3);
 425
 426         val = ioread8(bus->reg + NPCM_I2CCTL1);
 427         val &= ~NPCM_I2CCTL1_RWS;
 428         if (enable)
 429                 val |= NPCM_I2CCTL1_EOBINTE;
 430         else
 431                 val &= ~NPCM_I2CCTL1_EOBINTE;
 432         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 433 }
 434
 435 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
 436 {
 437         u8 tx_fifo_sts;
 438
 439         tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
 440         /* check if TX FIFO is not empty */
 441         if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0)
 442                 return false;
 443
 444         /* check if TX FIFO status bit is set: */
 445         return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
 446 }
 447
 448 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
 449 {
 450         u8 rx_fifo_sts;
 451
 452         rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
 453         /* check if RX FIFO is not empty: */
 454         if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0)
 455                 return false;
 456
 457         /* check if rx fifo full status is set: */
 458         return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
 459 }
 460
 461 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
 462 {
 463         u8 val;
 464
 465         val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
 466         val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
 467         iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
 468 }
 469
 470 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
 471 {
 472         u8 val;
 473
 474         val = ioread8(bus->reg + NPCM_I2CTXF_STS);
 475         val = val | NPCM_I2CTXF_STS_TX_THST;
 476         iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
 477 }
 478
 479 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
 480 {
 481         u8 val;
 482
 483         val = ioread8(bus->reg + NPCM_I2CRXF_STS);
 484         val = val | NPCM_I2CRXF_STS_RX_THST;
 485         iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
 486 }
 487
 488 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
 489 {
 490         u8 val;
 491
 492         val = ioread8(bus->reg + NPCM_I2CCTL1);
 493         val &= ~NPCM_I2CCTL1_RWS;
 494         if (enable)
 495                 val |= NPCM_I2CCTL1_INTEN;
 496         else
 497                 val &= ~NPCM_I2CCTL1_INTEN;
 498         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 499 }
 500
 501 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
 502 {
 503         u8 val;
 504
 505         val = ioread8(bus->reg + NPCM_I2CCTL1);
 506         val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
 507         val |= NPCM_I2CCTL1_START;
 508         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 509 }
 510
 511 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
 512 {
 513         u8 val;
 514
 515         /*
 516          * override HW issue: I2C may fail to supply stop condition in Master
 517          * Write operation.
 518          * Need to delay at least 5 us from the last int, before issueing a stop
 519          */
 520         udelay(10); /* function called from interrupt, can't sleep */
 521         val = ioread8(bus->reg + NPCM_I2CCTL1);
 522         val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
 523         val |= NPCM_I2CCTL1_STOP;
 524         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 525
 526         if (!bus->fifo_use)
 527                 return;
 528
 529         npcm_i2c_select_bank(bus, I2C_BANK_1);
 530
 531         if (bus->operation == I2C_READ_OPER)
 532                 npcm_i2c_clear_rx_fifo(bus);
 533         else
 534                 npcm_i2c_clear_tx_fifo(bus);
 535         npcm_i2c_clear_fifo_int(bus);
 536         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 537 }
 538
 539 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
 540 {
 541         u8 val;
 542
 543         val = ioread8(bus->reg + NPCM_I2CCTL1);
 544         val &= ~NPCM_I2CCTL1_RWS;
 545         if (stall)
 546                 val |= NPCM_I2CCTL1_STASTRE;
 547         else
 548                 val &= ~NPCM_I2CCTL1_STASTRE;
 549         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 550 }
 551
 552 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
 553 {
 554         u8 val;
 555
 556         val = ioread8(bus->reg + NPCM_I2CCTL1);
 557         val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
 558         val |= NPCM_I2CCTL1_ACK;
 559         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 560 }
 561
 562 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
 563 {
 564         u8 val;
 565
 566         /* Clear NEGACK, STASTR and BER bits */
 567         val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
 568         iowrite8(val, bus->reg + NPCM_I2CST);
 569 }
 570
 571 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 572 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
 573 {
 574         u8 i2cctl1;
 575
 576         /* enable interrupt on slave match: */
 577         i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 578         i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 579         if (enable)
 580                 i2cctl1 |= NPCM_I2CCTL1_NMINTE;
 581         else
 582                 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
 583         iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 584 }
 585
 586 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
 587                                  u8 addr, bool enable)
 588 {
 589         u8 i2cctl1;
 590         u8 i2cctl3;
 591         u8 sa_reg;
 592
 593         sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
 594         if (addr_type == I2C_GC_ADDR) {
 595                 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 596                 if (enable)
 597                         i2cctl1 |= NPCM_I2CCTL1_GCMEN;
 598                 else
 599                         i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
 600                 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 601                 return 0;
 602         } else if (addr_type == I2C_ARP_ADDR) {
 603                 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 604                 if (enable)
 605                         i2cctl3 |= I2CCTL3_ARPMEN;
 606                 else
 607                         i2cctl3 &= ~I2CCTL3_ARPMEN;
 608                 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 609                 return 0;
 610         }
 611         if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
 612                 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
 613
 614         if (addr_type >= I2C_ARP_ADDR)
 615                 return -EFAULT;
 616
 617         /* Set and enable the address */
 618         iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
 619         npcm_i2c_slave_int_enable(bus, enable);
 620
 621         return 0;
 622 }
 623 #endif
 624
 625 static void npcm_i2c_reset(struct npcm_i2c *bus)
 626 {
 627         /*
 628          * Save I2CCTL1 relevant bits. It is being cleared when the module
 629          *  is disabled.
 630          */
 631         u8 i2cctl1;
 632 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 633         u8 addr;
 634 #endif
 635
 636         i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 637
 638         npcm_i2c_disable(bus);
 639         npcm_i2c_enable(bus);
 640
 641         /* Restore NPCM_I2CCTL1 Status */
 642         i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 643         iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 644
 645         /* Clear BB (BUS BUSY) bit */
 646         iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
 647         iowrite8(0xFF, bus->reg + NPCM_I2CST);
 648
 649         /* Clear and disable EOB */
 650         npcm_i2c_eob_int(bus, false);
 651
 652         /* Clear all fifo bits: */
 653         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
 654
 655 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 656         if (bus->slave) {
 657                 addr = bus->slave->addr;
 658                 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
 659         }
 660 #endif
 661
 662         /* clear status bits for spurious interrupts */
 663         npcm_i2c_clear_master_status(bus);
 664
 665         bus->state = I2C_IDLE;
 666 }
 667
 668 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
 669 {
 670         return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
 671 }
 672
 673 static void npcm_i2c_callback(struct npcm_i2c *bus,
 674                               enum i2c_state_ind op_status, u16 info)
 675 {
 676         struct i2c_msg *msgs;
 677         int msgs_num;
 678
 679         msgs = bus->msgs;
 680         msgs_num = bus->msgs_num;
 681         /*
 682          * check that transaction was not timed-out, and msgs still
 683          * holds a valid value.
 684          */
 685         if (!msgs)
 686                 return;
 687
 688         if (completion_done(&bus->cmd_complete))
 689                 return;
 690
 691         switch (op_status) {
 692         case I2C_MASTER_DONE_IND:
 693                 bus->cmd_err = bus->msgs_num;
 694                 fallthrough;
 695         case I2C_BLOCK_BYTES_ERR_IND:
 696                 /* Master tx finished and all transmit bytes were sent */
 697                 if (bus->msgs) {
 698                         if (msgs[0].flags & I2C_M_RD)
 699                                 msgs[0].len = info;
 700                         else if (msgs_num == 2 &&
 701                                  msgs[1].flags & I2C_M_RD)
 702                                 msgs[1].len = info;
 703                 }
 704                 if (completion_done(&bus->cmd_complete) == false)
 705                         complete(&bus->cmd_complete);
 706         break;
 707
 708         case I2C_NACK_IND:
 709                 /* MASTER transmit got a NACK before tx all bytes */
 710                 bus->cmd_err = -ENXIO;
 711                 if (bus->master_or_slave == I2C_MASTER)
 712                         complete(&bus->cmd_complete);
 713
 714                 break;
 715         case I2C_BUS_ERR_IND:
 716                 /* Bus error */
 717                 bus->cmd_err = -EAGAIN;
 718                 if (bus->master_or_slave == I2C_MASTER)
 719                         complete(&bus->cmd_complete);
 720
 721                 break;
 722         case I2C_WAKE_UP_IND:
 723                 /* I2C wake up */
 724                 break;
 725         default:
 726                 break;
 727         }
 728
 729         bus->operation = I2C_NO_OPER;
 730 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 731         if (bus->slave)
 732                 bus->master_or_slave = I2C_SLAVE;
 733 #endif
 734 }
 735
 736 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
 737 {
 738         if (bus->operation == I2C_WRITE_OPER)
 739                 return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
 740                                  ioread8(bus->reg + NPCM_I2CTXF_STS));
 741         if (bus->operation == I2C_READ_OPER)
 742                 return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES,
 743                                  ioread8(bus->reg + NPCM_I2CRXF_STS));
 744         return 0;
 745 }
 746
 747 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
 748 {
 749         u8 size_free_fifo;
 750
 751         /*
 752          * Fill the FIFO, while the FIFO is not full and there are more bytes
 753          * to write
 754          */
 755         size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
 756         while (max_bytes-- && size_free_fifo) {
 757                 if (bus->wr_ind < bus->wr_size)
 758                         npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
 759                 else
 760                         npcm_i2c_wr_byte(bus, 0xFF);
 761                 size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
 762         }
 763 }
 764
 765 /*
 766  * npcm_i2c_set_fifo:
 767  * configure the FIFO before using it. If nread is -1 RX FIFO will not be
 768  * configured. same for nwrite
 769  */
 770 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
 771 {
 772         u8 rxf_ctl = 0;
 773
 774         if (!bus->fifo_use)
 775                 return;
 776         npcm_i2c_select_bank(bus, I2C_BANK_1);
 777         npcm_i2c_clear_tx_fifo(bus);
 778         npcm_i2c_clear_rx_fifo(bus);
 779
 780         /* configure RX FIFO */
 781         if (nread > 0) {
 782                 rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE);
 783
 784                 /* set LAST bit. if LAST is set next FIFO packet is nacked */
 785                 if (nread <= I2C_HW_FIFO_SIZE)
 786                         rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC;
 787
 788                 /*
 789                  * if we are about to read the first byte in blk rd mode,
 790                  * don't NACK it. If slave returns zero size HW can't NACK
 791                  * it immidiattly, it will read extra byte and then NACK.
 792                  */
 793                 if (bus->rd_ind == 0 && bus->read_block_use) {
 794                         /* set fifo to read one byte, no last: */
 795                         rxf_ctl = 1;
 796                 }
 797
 798                 /* set fifo size: */
 799                 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
 800         }
 801
 802         /* configure TX FIFO */
 803         if (nwrite > 0) {
 804                 if (nwrite > I2C_HW_FIFO_SIZE)
 805                         /* data to send is more then FIFO size. */
 806                         iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL);
 807                 else
 808                         iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
 809
 810                 npcm_i2c_clear_tx_fifo(bus);
 811         }
 812 }
 813
 814 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
 815 {
 816         u8 data;
 817
 818         while (bytes_in_fifo--) {
 819                 data = npcm_i2c_rd_byte(bus);
 820                 if (bus->rd_ind < bus->rd_size)
 821                         bus->rd_buf[bus->rd_ind++] = data;
 822         }
 823 }
 824
 825 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
 826 {
 827         /* Only current master is allowed to issue a stop condition */
 828         if (!npcm_i2c_is_master(bus))
 829                 return;
 830
 831         npcm_i2c_eob_int(bus, true);
 832         npcm_i2c_master_stop(bus);
 833         npcm_i2c_clear_master_status(bus);
 834 }
 835
 836 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 837 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
 838 {
 839         u8 slave_add;
 840
 841         if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
 842                 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
 843
 844         slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
 845
 846         return slave_add;
 847 }
 848
 849 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
 850 {
 851         int i;
 852
 853         /* Set the enable bit */
 854         slave_add |= 0x80;
 855
 856         for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
 857                 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
 858                         iowrite8(0, bus->reg + npcm_i2caddr[i]);
 859         }
 860
 861         return 0;
 862 }
 863
 864 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
 865 {
 866         /*
 867          * Fill the FIFO, while the FIFO is not full and there are more bytes
 868          * to write
 869          */
 870         npcm_i2c_clear_fifo_int(bus);
 871         npcm_i2c_clear_tx_fifo(bus);
 872         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 873         while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) {
 874                 if (bus->slv_wr_size <= 0)
 875                         break;
 876                 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
 877                 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
 878                 bus->slv_wr_ind++;
 879                 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
 880                 bus->slv_wr_size--;
 881         }
 882 }
 883
 884 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
 885 {
 886         u8 data;
 887
 888         if (!bus->slave)
 889                 return;
 890
 891         while (bytes_in_fifo--) {
 892                 data = npcm_i2c_rd_byte(bus);
 893
 894                 bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE;
 895                 bus->slv_rd_buf[bus->slv_rd_ind] = data;
 896                 bus->slv_rd_ind++;
 897
 898                 /* 1st byte is length in block protocol: */
 899                 if (bus->slv_rd_ind == 1 && bus->read_block_use)
 900                         bus->slv_rd_size = data + bus->PEC_use + 1;
 901         }
 902 }
 903
 904 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
 905 {
 906         int i;
 907         u8 value;
 908         int ind;
 909         int ret = bus->slv_wr_ind;
 910
 911         /* fill a cyclic buffer */
 912         for (i = 0; i < I2C_HW_FIFO_SIZE; i++) {
 913                 if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
 914                         break;
 915                 if (bus->state == I2C_SLAVE_MATCH) {
 916                         i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
 917                         bus->state = I2C_OPER_STARTED;
 918                 } else {
 919                         i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
 920                 }
 921                 ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE;
 922                 bus->slv_wr_buf[ind] = value;
 923                 bus->slv_wr_size++;
 924         }
 925         return I2C_HW_FIFO_SIZE - ret;
 926 }
 927
 928 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
 929 {
 930         int i;
 931
 932         for (i = 0; i < bus->slv_rd_ind; i++)
 933                 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
 934                                 &bus->slv_rd_buf[i]);
 935         /*
 936          * once we send bytes up, need to reset the counter of the wr buf
 937          * got data from master (new offset in device), ignore wr fifo:
 938          */
 939         if (bus->slv_rd_ind) {
 940                 bus->slv_wr_size = 0;
 941                 bus->slv_wr_ind = 0;
 942         }
 943
 944         bus->slv_rd_ind = 0;
 945         bus->slv_rd_size = bus->adap.quirks->max_read_len;
 946
 947         npcm_i2c_clear_fifo_int(bus);
 948         npcm_i2c_clear_rx_fifo(bus);
 949 }
 950
 951 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
 952                                    u8 *read_data)
 953 {
 954         bus->state = I2C_OPER_STARTED;
 955         bus->operation = I2C_READ_OPER;
 956         bus->slv_rd_size = nread;
 957         bus->slv_rd_ind = 0;
 958
 959         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 960         iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
 961         npcm_i2c_clear_tx_fifo(bus);
 962         npcm_i2c_clear_rx_fifo(bus);
 963 }
 964
 965 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
 966                                 u8 *write_data)
 967 {
 968         if (nwrite == 0)
 969                 return;
 970
 971         bus->operation = I2C_WRITE_OPER;
 972
 973         /* get the next buffer */
 974         npcm_i2c_slave_get_wr_buf(bus);
 975         npcm_i2c_write_fifo_slave(bus, nwrite);
 976 }
 977
 978 /*
 979  * npcm_i2c_slave_wr_buf_sync:
 980  * currently slave IF only supports single byte operations.
 981  * in order to utilyze the npcm HW FIFO, the driver will ask for 16 bytes
 982  * at a time, pack them in buffer, and then transmit them all together
 983  * to the FIFO and onward to the bus.
 984  * NACK on read will be once reached to bus->adap->quirks->max_read_len.
 985  * sending a NACK wherever the backend requests for it is not supported.
 986  * the next two functions allow reading to local buffer before writing it all
 987  * to the HW FIFO.
 988  */
 989 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
 990 {
 991         int left_in_fifo;
 992
 993         left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
 994                                  ioread8(bus->reg + NPCM_I2CTXF_STS));
 995
 996         /* fifo already full: */
 997         if (left_in_fifo >= I2C_HW_FIFO_SIZE ||
 998             bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
 999                 return;
1000
1001         /* update the wr fifo index back to the untransmitted bytes: */
1002         bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1003         bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1004
1005         if (bus->slv_wr_ind < 0)
1006                 bus->slv_wr_ind += I2C_HW_FIFO_SIZE;
1007 }
1008
1009 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1010 {
1011         if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1012                 /*
1013                  * Slave got an address match with direction bit 1 so it should
1014                  * transmit data. Write till the master will NACK
1015                  */
1016                 bus->operation = I2C_WRITE_OPER;
1017                 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1018                                     bus->slv_wr_buf);
1019         } else {
1020                 /*
1021                  * Slave got an address match with direction bit 0 so it should
1022                  * receive data.
1023                  * this module does not support saying no to bytes.
1024                  * it will always ACK.
1025                  */
1026                 bus->operation = I2C_READ_OPER;
1027                 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1028                 bus->stop_ind = I2C_SLAVE_RCV_IND;
1029                 npcm_i2c_slave_send_rd_buf(bus);
1030                 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1031                                        bus->slv_rd_buf);
1032         }
1033 }
1034
1035 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1036 {
1037         u8 val;
1038         irqreturn_t ret = IRQ_NONE;
1039         u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1040
1041         /* Slave: A NACK has occurred */
1042         if (NPCM_I2CST_NEGACK & i2cst) {
1043                 bus->stop_ind = I2C_NACK_IND;
1044                 npcm_i2c_slave_wr_buf_sync(bus);
1045                 if (bus->fifo_use)
1046                         /* clear the FIFO */
1047                         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1048                                  bus->reg + NPCM_I2CFIF_CTS);
1049
1050                 /* In slave write, NACK is OK, otherwise it is a problem */
1051                 bus->stop_ind = I2C_NO_STATUS_IND;
1052                 bus->operation = I2C_NO_OPER;
1053                 bus->own_slave_addr = 0xFF;
1054
1055                 /*
1056                  * Slave has to wait for STOP to decide this is the end
1057                  * of the transaction. tx is not yet considered as done
1058                  */
1059                 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1060
1061                 ret = IRQ_HANDLED;
1062         }
1063
1064         /* Slave mode: a Bus Error (BER) has been identified */
1065         if (NPCM_I2CST_BER & i2cst) {
1066                 /*
1067                  * Check whether bus arbitration or Start or Stop during data
1068                  * xfer bus arbitration problem should not result in recovery
1069                  */
1070                 bus->stop_ind = I2C_BUS_ERR_IND;
1071
1072                 /* wait for bus busy before clear fifo */
1073                 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1074
1075                 bus->state = I2C_IDLE;
1076
1077                 /*
1078                  * in BER case we might get 2 interrupts: one for slave one for
1079                  * master ( for a channel which is master\slave switching)
1080                  */
1081                 if (completion_done(&bus->cmd_complete) == false) {
1082                         bus->cmd_err = -EIO;
1083                         complete(&bus->cmd_complete);
1084                 }
1085                 bus->own_slave_addr = 0xFF;
1086                 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1087                 ret = IRQ_HANDLED;
1088         }
1089
1090         /* A Slave Stop Condition has been identified */
1091         if (NPCM_I2CST_SLVSTP & i2cst) {
1092                 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1093
1094                 bus->stop_ind = I2C_SLAVE_DONE_IND;
1095
1096                 if (bus->operation == I2C_READ_OPER)
1097                         npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1098
1099                 /* if the buffer is empty nothing will be sent */
1100                 npcm_i2c_slave_send_rd_buf(bus);
1101
1102                 /* Slave done transmitting or receiving */
1103                 bus->stop_ind = I2C_NO_STATUS_IND;
1104
1105                 /*
1106                  * Note, just because we got here, it doesn't mean we through
1107                  * away the wr buffer.
1108                  * we keep it until the next received offset.
1109                  */
1110                 bus->operation = I2C_NO_OPER;
1111                 bus->own_slave_addr = 0xFF;
1112                 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1113                 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1114                 if (bus->fifo_use) {
1115                         npcm_i2c_clear_fifo_int(bus);
1116                         npcm_i2c_clear_rx_fifo(bus);
1117                         npcm_i2c_clear_tx_fifo(bus);
1118
1119                         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1120                                  bus->reg + NPCM_I2CFIF_CTS);
1121                 }
1122                 bus->state = I2C_IDLE;
1123                 ret = IRQ_HANDLED;
1124         }
1125
1126         /* restart condition occurred and Rx-FIFO was not empty */
1127         if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1128                                        ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1129                 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1130                 bus->master_or_slave = I2C_SLAVE;
1131                 if (bus->operation == I2C_READ_OPER)
1132                         npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1133                 bus->operation = I2C_WRITE_OPER;
1134                 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1135                 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1136                       NPCM_I2CFIF_CTS_RXF_TXE;
1137                 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1138                 npcm_i2c_slave_rd_wr(bus);
1139                 ret = IRQ_HANDLED;
1140         }
1141
1142         /* A Slave Address Match has been identified */
1143         if (NPCM_I2CST_NMATCH & i2cst) {
1144                 u8 info = 0;
1145
1146                 /* Address match automatically implies slave mode */
1147                 bus->master_or_slave = I2C_SLAVE;
1148                 npcm_i2c_clear_fifo_int(bus);
1149                 npcm_i2c_clear_rx_fifo(bus);
1150                 npcm_i2c_clear_tx_fifo(bus);
1151                 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1152                 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
1153                 if (NPCM_I2CST_XMIT & i2cst) {
1154                         bus->operation = I2C_WRITE_OPER;
1155                 } else {
1156                         i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1157                                         &info);
1158                         bus->operation = I2C_READ_OPER;
1159                 }
1160                 if (bus->own_slave_addr == 0xFF) {
1161                         /* Check which type of address match */
1162                         val = ioread8(bus->reg + NPCM_I2CCST);
1163                         if (NPCM_I2CCST_MATCH & val) {
1164                                 u16 addr;
1165                                 enum i2c_addr eaddr;
1166                                 u8 i2ccst2;
1167                                 u8 i2ccst3;
1168
1169                                 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1170                                 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1171
1172                                 /*
1173                                  * the i2c module can response to 10 own SA.
1174                                  * check which one was addressed by the master.
1175                                  * repond to the first one.
1176                                  */
1177                                 addr = ((i2ccst3 & 0x07) << 7) |
1178                                         (i2ccst2 & 0x7F);
1179                                 info = ffs(addr);
1180                                 eaddr = (enum i2c_addr)info;
1181                                 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1182                                 addr &= 0x7F;
1183                                 bus->own_slave_addr = addr;
1184                                 if (bus->PEC_mask & BIT(info))
1185                                         bus->PEC_use = true;
1186                                 else
1187                                         bus->PEC_use = false;
1188                         } else {
1189                                 if (NPCM_I2CCST_GCMATCH & val)
1190                                         bus->own_slave_addr = 0;
1191                                 if (NPCM_I2CCST_ARPMATCH & val)
1192                                         bus->own_slave_addr = 0x61;
1193                         }
1194                 } else {
1195                         /*
1196                          *  Slave match can happen in two options:
1197                          *  1. Start, SA, read (slave read without further ado)
1198                          *  2. Start, SA, read, data, restart, SA, read,  ...
1199                          *     (slave read in fragmented mode)
1200                          *  3. Start, SA, write, data, restart, SA, read, ..
1201                          *     (regular write-read mode)
1202                          */
1203                         if ((bus->state == I2C_OPER_STARTED &&
1204                              bus->operation == I2C_READ_OPER &&
1205                              bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1206                              bus->stop_ind == I2C_SLAVE_RCV_IND) {
1207                                 /* slave tx after slave rx w/o STOP */
1208                                 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1209                         }
1210                 }
1211
1212                 if (NPCM_I2CST_XMIT & i2cst)
1213                         bus->stop_ind = I2C_SLAVE_XMIT_IND;
1214                 else
1215                         bus->stop_ind = I2C_SLAVE_RCV_IND;
1216                 bus->state = I2C_SLAVE_MATCH;
1217                 npcm_i2c_slave_rd_wr(bus);
1218                 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1219                 ret = IRQ_HANDLED;
1220         }
1221
1222         /* Slave SDA status is set - tx or rx */
1223         if ((NPCM_I2CST_SDAST & i2cst) ||
1224             (bus->fifo_use &&
1225             (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1226                 npcm_i2c_slave_rd_wr(bus);
1227                 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1228                 ret = IRQ_HANDLED;
1229         } /* SDAST */
1230
1231         /*
1232          * if irq is not one of the above, make sure EOB is disabled and all
1233          * status bits are cleared.
1234          */
1235         if (ret == IRQ_NONE) {
1236                 npcm_i2c_eob_int(bus, false);
1237                 npcm_i2c_clear_master_status(bus);
1238         }
1239
1240         return IRQ_HANDLED;
1241 }
1242
1243 static int npcm_i2c_reg_slave(struct i2c_client *client)
1244 {
1245         unsigned long lock_flags;
1246         struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1247
1248         bus->slave = client;
1249
1250         if (!bus->slave)
1251                 return -EINVAL;
1252
1253         if (client->flags & I2C_CLIENT_TEN)
1254                 return -EAFNOSUPPORT;
1255
1256         spin_lock_irqsave(&bus->lock, lock_flags);
1257
1258         npcm_i2c_init_params(bus);
1259         bus->slv_rd_size = 0;
1260         bus->slv_wr_size = 0;
1261         bus->slv_rd_ind = 0;
1262         bus->slv_wr_ind = 0;
1263         if (client->flags & I2C_CLIENT_PEC)
1264                 bus->PEC_use = true;
1265
1266         dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1267                  client->addr, bus->PEC_use);
1268
1269         npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1270         npcm_i2c_clear_fifo_int(bus);
1271         npcm_i2c_clear_rx_fifo(bus);
1272         npcm_i2c_clear_tx_fifo(bus);
1273         npcm_i2c_slave_int_enable(bus, true);
1274
1275         spin_unlock_irqrestore(&bus->lock, lock_flags);
1276         return 0;
1277 }
1278
1279 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1280 {
1281         struct npcm_i2c *bus = client->adapter->algo_data;
1282         unsigned long lock_flags;
1283
1284         spin_lock_irqsave(&bus->lock, lock_flags);
1285         if (!bus->slave) {
1286                 spin_unlock_irqrestore(&bus->lock, lock_flags);
1287                 return -EINVAL;
1288         }
1289         npcm_i2c_slave_int_enable(bus, false);
1290         npcm_i2c_remove_slave_addr(bus, client->addr);
1291         bus->slave = NULL;
1292         spin_unlock_irqrestore(&bus->lock, lock_flags);
1293         return 0;
1294 }
1295 #endif /* CONFIG_I2C_SLAVE */
1296
1297 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1298 {
1299         int rcount;
1300         int fifo_bytes;
1301         enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1302
1303         fifo_bytes = npcm_i2c_fifo_usage(bus);
1304         rcount = bus->rd_size - bus->rd_ind;
1305
1306         /*
1307          * In order not to change the RX_TRH during transaction (we found that
1308          * this might be problematic if it takes too much time to read the FIFO)
1309          * we read the data in the following way. If the number of bytes to
1310          * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1311          * and in the next int we read rest of the data.
1312          */
1313         if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE)
1314                 fifo_bytes = rcount - I2C_HW_FIFO_SIZE;
1315
1316         if (rcount <= fifo_bytes) {
1317                 /* last bytes are about to be read - end of tx */
1318                 bus->state = I2C_STOP_PENDING;
1319                 bus->stop_ind = ind;
1320                 npcm_i2c_eob_int(bus, true);
1321                 /* Stop should be set before reading last byte. */
1322                 npcm_i2c_master_stop(bus);
1323                 npcm_i2c_read_fifo(bus, fifo_bytes);
1324         } else {
1325                 npcm_i2c_read_fifo(bus, fifo_bytes);
1326                 rcount = bus->rd_size - bus->rd_ind;
1327                 npcm_i2c_set_fifo(bus, rcount, -1);
1328         }
1329 }
1330
1331 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1332 {
1333         u16 wcount;
1334
1335         if (bus->fifo_use)
1336                 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1337
1338         /* Master write operation - last byte handling */
1339         if (bus->wr_ind == bus->wr_size) {
1340                 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1341                         /*
1342                          * No more bytes to send (to add to the FIFO),
1343                          * however the FIFO is not empty yet. It is
1344                          * still in the middle of tx. Currently there's nothing
1345                          * to do except for waiting to the end of the tx
1346                          * We will get an int when the FIFO will get empty.
1347                          */
1348                         return;
1349
1350                 if (bus->rd_size == 0) {
1351                         /* all bytes have been written, in wr only operation */
1352                         npcm_i2c_eob_int(bus, true);
1353                         bus->state = I2C_STOP_PENDING;
1354                         bus->stop_ind = I2C_MASTER_DONE_IND;
1355                         npcm_i2c_master_stop(bus);
1356                         /* Clear SDA Status bit (by writing dummy byte) */
1357                         npcm_i2c_wr_byte(bus, 0xFF);
1358
1359                 } else {
1360                         /* last write-byte written on previous int - restart */
1361                         npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1362                         /* Generate repeated start upon next write to SDA */
1363                         npcm_i2c_master_start(bus);
1364
1365                         /*
1366                          * Receiving one byte only - stall after successful
1367                          * completion of send address byte. If we NACK here, and
1368                          * slave doesn't ACK the address, we might
1369                          * unintentionally NACK the next multi-byte read.
1370                          */
1371                         if (bus->rd_size == 1)
1372                                 npcm_i2c_stall_after_start(bus, true);
1373
1374                         /* Next int will occur on read */
1375                         bus->operation = I2C_READ_OPER;
1376                         /* send the slave address in read direction */
1377                         npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1378                 }
1379         } else {
1380                 /* write next byte not last byte and not slave address */
1381                 if (!bus->fifo_use || bus->wr_size == 1) {
1382                         npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1383                 } else {
1384                         wcount = bus->wr_size - bus->wr_ind;
1385                         npcm_i2c_set_fifo(bus, -1, wcount);
1386                         if (wcount)
1387                                 npcm_i2c_write_to_fifo_master(bus, wcount);
1388                 }
1389         }
1390 }
1391
1392 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1393 {
1394         u16 block_extra_bytes_size;
1395         u8 data;
1396
1397         /* added bytes to the packet: */
1398         block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1399
1400         /*
1401          * Perform master read, distinguishing between last byte and the rest of
1402          * the bytes. The last byte should be read when the clock is stopped
1403          */
1404         if (bus->rd_ind == 0) { /* first byte handling: */
1405                 if (bus->read_block_use) {
1406                         /* first byte in block protocol is the size: */
1407                         data = npcm_i2c_rd_byte(bus);
1408                         data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1409                         bus->rd_size = data + block_extra_bytes_size;
1410                         bus->rd_buf[bus->rd_ind++] = data;
1411
1412                         /* clear RX FIFO interrupt status: */
1413                         if (bus->fifo_use) {
1414                                 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1415                                 data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1416                                 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1417                         }
1418
1419                         npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1420                         npcm_i2c_stall_after_start(bus, false);
1421                 } else {
1422                         npcm_i2c_clear_tx_fifo(bus);
1423                         npcm_i2c_master_fifo_read(bus);
1424                 }
1425         } else {
1426                 if (bus->rd_size == block_extra_bytes_size &&
1427                     bus->read_block_use) {
1428                         bus->state = I2C_STOP_PENDING;
1429                         bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1430                         bus->cmd_err = -EIO;
1431                         npcm_i2c_eob_int(bus, true);
1432                         npcm_i2c_master_stop(bus);
1433                         npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1434                 } else {
1435                         npcm_i2c_master_fifo_read(bus);
1436                 }
1437         }
1438 }
1439
1440 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1441 {
1442         iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1443         npcm_i2c_nack(bus);
1444         bus->stop_ind = I2C_BUS_ERR_IND;
1445         npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1446 }
1447
1448 /* A NACK has occurred */
1449 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1450 {
1451         u8 val;
1452
1453         if (bus->nack_cnt < ULLONG_MAX)
1454                 bus->nack_cnt++;
1455
1456         if (bus->fifo_use) {
1457                 /*
1458                  * if there are still untransmitted bytes in TX FIFO
1459                  * reduce them from wr_ind
1460                  */
1461                 if (bus->operation == I2C_WRITE_OPER)
1462                         bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1463
1464                 /* clear the FIFO */
1465                 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1466         }
1467
1468         /* In master write operation, got unexpected NACK */
1469         bus->stop_ind = I2C_NACK_IND;
1470         /* Only current master is allowed to issue Stop Condition */
1471         if (npcm_i2c_is_master(bus)) {
1472                 /* stopping in the middle */
1473                 npcm_i2c_eob_int(bus, false);
1474                 npcm_i2c_master_stop(bus);
1475
1476                 /* Clear SDA Status bit (by reading dummy byte) */
1477                 npcm_i2c_rd_byte(bus);
1478
1479                 /*
1480                  * The bus is released from stall only after the SW clears
1481                  * NEGACK bit. Then a Stop condition is sent.
1482                  */
1483                 npcm_i2c_clear_master_status(bus);
1484                 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1485                                           !(val & NPCM_I2CCST_BUSY), 10, 200);
1486                 /* verify no status bits are still set after bus is released */
1487                 npcm_i2c_clear_master_status(bus);
1488         }
1489         bus->state = I2C_IDLE;
1490
1491         /*
1492          * In Master mode, NACK should be cleared only after STOP.
1493          * In such case, the bus is released from stall only after the
1494          * software clears NACK bit. Then a Stop condition is sent.
1495          */
1496         npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1497 }
1498
1499         /* Master mode: a Bus Error has been identified */
1500 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1501 {
1502         if (bus->ber_cnt < ULLONG_MAX)
1503                 bus->ber_cnt++;
1504         bus->stop_ind = I2C_BUS_ERR_IND;
1505         if (npcm_i2c_is_master(bus)) {
1506                 npcm_i2c_master_abort(bus);
1507         } else {
1508                 npcm_i2c_clear_master_status(bus);
1509
1510                 /* Clear BB (BUS BUSY) bit */
1511                 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1512
1513                 bus->cmd_err = -EAGAIN;
1514                 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1515         }
1516         bus->state = I2C_IDLE;
1517 }
1518
1519         /* EOB: a master End Of Busy (meaning STOP completed) */
1520 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1521 {
1522         npcm_i2c_eob_int(bus, false);
1523         bus->state = I2C_IDLE;
1524         npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1525 }
1526
1527 /* Address sent and requested stall occurred (Master mode) */
1528 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1529 {
1530         if (npcm_i2c_is_quick(bus)) {
1531                 bus->state = I2C_STOP_PENDING;
1532                 bus->stop_ind = I2C_MASTER_DONE_IND;
1533                 npcm_i2c_eob_int(bus, true);
1534                 npcm_i2c_master_stop(bus);
1535         } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1536                 /*
1537                  * Receiving one byte only - set NACK after ensuring
1538                  * slave ACKed the address byte.
1539                  */
1540                 npcm_i2c_nack(bus);
1541         }
1542
1543         /* Reset stall-after-address-byte */
1544         npcm_i2c_stall_after_start(bus, false);
1545
1546         /* Clear stall only after setting STOP */
1547         iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1548 }
1549
1550 /* SDA status is set - TX or RX, master */
1551 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1552 {
1553         u8 fif_cts;
1554
1555         if (!npcm_i2c_is_master(bus))
1556                 return;
1557
1558         if (bus->state == I2C_IDLE) {
1559                 bus->stop_ind = I2C_WAKE_UP_IND;
1560
1561                 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1562                         /*
1563                          * Need to stall after successful
1564                          * completion of sending address byte
1565                          */
1566                         npcm_i2c_stall_after_start(bus, true);
1567                 else
1568                         npcm_i2c_stall_after_start(bus, false);
1569
1570                 /*
1571                  * Receiving one byte only - stall after successful completion
1572                  * of sending address byte If we NACK here, and slave doesn't
1573                  * ACK the address, we might unintentionally NACK the next
1574                  * multi-byte read
1575                  */
1576                 if (bus->wr_size == 0 && bus->rd_size == 1)
1577                         npcm_i2c_stall_after_start(bus, true);
1578
1579                 /* Initiate I2C master tx */
1580
1581                 /* select bank 1 for FIFO regs */
1582                 npcm_i2c_select_bank(bus, I2C_BANK_1);
1583
1584                 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1585                 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1586
1587                 /* clear FIFO and relevant status bits. */
1588                 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1589                 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1590
1591                 /* re-enable */
1592                 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1593                 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1594
1595                 /*
1596                  * Configure the FIFO threshold:
1597                  * according to the needed # of bytes to read.
1598                  * Note: due to HW limitation can't config the rx fifo before it
1599                  * got and ACK on the restart. LAST bit will not be reset unless
1600                  * RX completed. It will stay set on the next tx.
1601                  */
1602                 if (bus->wr_size)
1603                         npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1604                 else
1605                         npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1606
1607                 bus->state = I2C_OPER_STARTED;
1608
1609                 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1610                         npcm_i2c_wr_byte(bus, bus->dest_addr);
1611                 else
1612                         npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1613         /* SDA interrupt, after start\restart */
1614         } else {
1615                 if (NPCM_I2CST_XMIT & i2cst) {
1616                         bus->operation = I2C_WRITE_OPER;
1617                         npcm_i2c_irq_master_handler_write(bus);
1618                 } else {
1619                         bus->operation = I2C_READ_OPER;
1620                         npcm_i2c_irq_master_handler_read(bus);
1621                 }
1622         }
1623 }
1624
1625 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1626 {
1627         u8 i2cst;
1628         int ret = -EIO;
1629
1630         i2cst = ioread8(bus->reg + NPCM_I2CST);
1631
1632         if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1633                 npcm_i2c_irq_handle_nmatch(bus);
1634                 return 0;
1635         }
1636         /* A NACK has occurred */
1637         if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1638                 npcm_i2c_irq_handle_nack(bus);
1639                 return 0;
1640         }
1641
1642         /* Master mode: a Bus Error has been identified */
1643         if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1644                 npcm_i2c_irq_handle_ber(bus);
1645                 return 0;
1646         }
1647
1648         /* EOB: a master End Of Busy (meaning STOP completed) */
1649         if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1650                        ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1651             (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1652                        ioread8(bus->reg + NPCM_I2CCST3)))) {
1653                 npcm_i2c_irq_handle_eob(bus);
1654                 return 0;
1655         }
1656
1657         /* Address sent and requested stall occurred (Master mode) */
1658         if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1659                 npcm_i2c_irq_handle_stall_after_start(bus);
1660                 ret = 0;
1661         }
1662
1663         /* SDA status is set - TX or RX, master */
1664         if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1665             (bus->fifo_use &&
1666             (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1667                 npcm_i2c_irq_handle_sda(bus, i2cst);
1668                 ret = 0;
1669         }
1670
1671         return ret;
1672 }
1673
1674 /* recovery using TGCLK functionality of the module */
1675 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1676 {
1677         u8               val;
1678         u8               fif_cts;
1679         bool             done = false;
1680         int              status = -ENOTRECOVERABLE;
1681         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1682         /* Allow 3 bytes (27 toggles) to be read from the slave: */
1683         int              iter = 27;
1684
1685         if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1686                 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1687                         bus->num, bus->dest_addr);
1688                 npcm_i2c_reset(bus);
1689                 return 0;
1690         }
1691
1692         npcm_i2c_int_enable(bus, false);
1693         npcm_i2c_disable(bus);
1694         npcm_i2c_enable(bus);
1695         iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1696         npcm_i2c_clear_tx_fifo(bus);
1697         npcm_i2c_clear_rx_fifo(bus);
1698         iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1699         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1700         npcm_i2c_stall_after_start(bus, false);
1701
1702         /* select bank 1 for FIFO regs */
1703         npcm_i2c_select_bank(bus, I2C_BANK_1);
1704
1705         /* clear FIFO and relevant status bits. */
1706         fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1707         fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1708         fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1709         iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1710         npcm_i2c_set_fifo(bus, -1, 0);
1711
1712         /* Repeat the following sequence until SDA is released */
1713         do {
1714                 /* Issue a single SCL toggle */
1715                 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1716                 usleep_range(20, 30);
1717                 /* If SDA line is inactive (high), stop */
1718                 if (npcm_i2c_get_SDA(_adap)) {
1719                         done = true;
1720                         status = 0;
1721                 }
1722         } while (!done && iter--);
1723
1724         /* If SDA line is released: send start-addr-stop, to re-sync. */
1725         if (npcm_i2c_get_SDA(_adap)) {
1726                 /* Send an address byte in write direction: */
1727                 npcm_i2c_wr_byte(bus, bus->dest_addr);
1728                 npcm_i2c_master_start(bus);
1729                 /* Wait until START condition is sent */
1730                 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1731                                             20, 200);
1732                 /* If START condition was sent */
1733                 if (npcm_i2c_is_master(bus) > 0) {
1734                         usleep_range(20, 30);
1735                         npcm_i2c_master_stop(bus);
1736                         usleep_range(200, 500);
1737                 }
1738         }
1739         npcm_i2c_reset(bus);
1740         npcm_i2c_int_enable(bus, true);
1741
1742         if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1743                 status = 0;
1744         else
1745                 status = -ENOTRECOVERABLE;
1746         if (status) {
1747                 if (bus->rec_fail_cnt < ULLONG_MAX)
1748                         bus->rec_fail_cnt++;
1749         } else {
1750                 if (bus->rec_succ_cnt < ULLONG_MAX)
1751                         bus->rec_succ_cnt++;
1752         }
1753         return status;
1754 }
1755
1756 /* recovery using bit banging functionality of the module */
1757 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1758 {
1759         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1760         struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1761
1762         rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1763
1764         /*
1765          * npcm i2c HW allows direct reading of SCL and SDA.
1766          * However, it does not support setting SCL and SDA directly.
1767          * The recovery function can togle SCL when SDA is low (but not set)
1768          * Getter functions used internally, and can be used externaly.
1769          */
1770         rinfo->get_scl = npcm_i2c_get_SCL;
1771         rinfo->get_sda = npcm_i2c_get_SDA;
1772         _adap->bus_recovery_info = rinfo;
1773 }
1774
1775 /* SCLFRQ min/max field values */
1776 #define SCLFRQ_MIN  10
1777 #define SCLFRQ_MAX  511
1778 #define clk_coef(freq, mul)     DIV_ROUND_UP((freq) * (mul), 1000000)
1779
1780 /*
1781  * npcm_i2c_init_clk: init HW timing parameters.
1782  * NPCM7XX i2c module timing parameters are depenent on module core clk (APB)
1783  * and bus frequency.
1784  * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are simetric.
1785  * 400kHz bus requires assymetric HT and LT. A different equation is recomended
1786  * by the HW designer, given core clock range (equations in comments below).
1787  *
1788  */
1789 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1790 {
1791         u32  k1 = 0;
1792         u32  k2 = 0;
1793         u8   dbnct = 0;
1794         u32  sclfrq = 0;
1795         u8   hldt = 7;
1796         u8   fast_mode = 0;
1797         u32  src_clk_khz;
1798         u32  bus_freq_khz;
1799
1800         src_clk_khz = bus->apb_clk / 1000;
1801         bus_freq_khz = bus_freq_hz / 1000;
1802         bus->bus_freq = bus_freq_hz;
1803
1804         /* 100KHz and below: */
1805         if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1806                 sclfrq = src_clk_khz / (bus_freq_khz * 4);
1807
1808                 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1809                         return -EDOM;
1810
1811                 if (src_clk_khz >= 40000)
1812                         hldt = 17;
1813                 else if (src_clk_khz >= 12500)
1814                         hldt = 15;
1815                 else
1816                         hldt = 7;
1817         }
1818
1819         /* 400KHz: */
1820         else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1821                 sclfrq = 0;
1822                 fast_mode = I2CCTL3_400K_MODE;
1823
1824                 if (src_clk_khz < 7500)
1825                         /* 400KHZ cannot be supported for core clock < 7.5MHz */
1826                         return -EDOM;
1827
1828                 else if (src_clk_khz >= 50000) {
1829                         k1 = 80;
1830                         k2 = 48;
1831                         hldt = 12;
1832                         dbnct = 7;
1833                 }
1834
1835                 /* Master or Slave with frequency > 25MHz */
1836                 else if (src_clk_khz > 25000) {
1837                         hldt = clk_coef(src_clk_khz, 300) + 7;
1838                         k1 = clk_coef(src_clk_khz, 1600);
1839                         k2 = clk_coef(src_clk_khz, 900);
1840                 }
1841         }
1842
1843         /* 1MHz: */
1844         else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1845                 sclfrq = 0;
1846                 fast_mode = I2CCTL3_400K_MODE;
1847
1848                 /* 1MHZ cannot be supported for core clock < 24 MHz */
1849                 if (src_clk_khz < 24000)
1850                         return -EDOM;
1851
1852                 k1 = clk_coef(src_clk_khz, 620);
1853                 k2 = clk_coef(src_clk_khz, 380);
1854
1855                 /* Core clk > 40 MHz */
1856                 if (src_clk_khz > 40000) {
1857                         /*
1858                          * Set HLDT:
1859                          * SDA hold time:  (HLDT-7) * T(CLK) >= 120
1860                          * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1861                          */
1862                         hldt = clk_coef(src_clk_khz, 120) + 7;
1863                 } else {
1864                         hldt = 7;
1865                         dbnct = 2;
1866                 }
1867         }
1868
1869         /* Frequency larger than 1 MHz is not supported */
1870         else
1871                 return -EINVAL;
1872
1873         if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1874                 k1 = round_up(k1, 2);
1875                 k2 = round_up(k2 + 1, 2);
1876                 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1877                     k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1878                         return -EDOM;
1879         }
1880
1881         /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1882         iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1883                  bus->reg + NPCM_I2CCTL2);
1884
1885         /* bits [8:7] are in I2CCTL3 reg */
1886         iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1887                  bus->reg + NPCM_I2CCTL3);
1888
1889         /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1890         npcm_i2c_select_bank(bus, I2C_BANK_0);
1891
1892         if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1893                 /*
1894                  * Set SCL Low/High Time:
1895                  * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2
1896                  * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1897                  */
1898                 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1899                 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1900
1901                 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1902         }
1903
1904         iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1905
1906         /* Return to Bank 1, and stay there by default: */
1907         npcm_i2c_select_bank(bus, I2C_BANK_1);
1908
1909         return 0;
1910 }
1911
1912 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1913                                 u32 bus_freq_hz)
1914 {
1915         u8 val;
1916         int ret;
1917
1918         /* Check whether module already enabled or frequency is out of bounds */
1919         if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1920             bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1921                 return -EINVAL;
1922
1923         npcm_i2c_int_enable(bus, false);
1924         npcm_i2c_disable(bus);
1925
1926         /* Configure FIFO mode : */
1927         if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1928                 bus->fifo_use = true;
1929                 npcm_i2c_select_bank(bus, I2C_BANK_0);
1930                 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1931                 val |= NPCM_I2CFIF_CTL_FIFO_EN;
1932                 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1933                 npcm_i2c_select_bank(bus, I2C_BANK_1);
1934         } else {
1935                 bus->fifo_use = false;
1936         }
1937
1938         /* Configure I2C module clock frequency */
1939         ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1940         if (ret) {
1941                 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1942                 return ret;
1943         }
1944
1945         /* Enable module (before configuring CTL1) */
1946         npcm_i2c_enable(bus);
1947         bus->state = I2C_IDLE;
1948         val = ioread8(bus->reg + NPCM_I2CCTL1);
1949         val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1950         iowrite8(val, bus->reg + NPCM_I2CCTL1);
1951
1952         npcm_i2c_reset(bus);
1953
1954         /* check HW is OK: SDA and SCL should be high at this point. */
1955         if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1956                 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1957                 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1958                         npcm_i2c_get_SCL(&bus->adap));
1959                 return -ENXIO;
1960         }
1961
1962         npcm_i2c_int_enable(bus, true);
1963         return 0;
1964 }
1965
1966 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1967 {
1968         u32 clk_freq_hz;
1969         int ret;
1970
1971         /* Initialize the internal data structures */
1972         bus->state = I2C_DISABLE;
1973         bus->master_or_slave = I2C_SLAVE;
1974         bus->int_time_stamp = 0;
1975 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1976         bus->slave = NULL;
1977 #endif
1978
1979         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1980                                        &clk_freq_hz);
1981         if (ret) {
1982                 dev_info(&pdev->dev, "Could not read clock-frequency property");
1983                 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
1984         }
1985
1986         ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
1987         if (ret) {
1988                 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
1989                 return ret;
1990         }
1991
1992         return 0;
1993 }
1994
1995 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
1996 {
1997         struct npcm_i2c *bus = dev_id;
1998
1999         if (npcm_i2c_is_master(bus))
2000                 bus->master_or_slave = I2C_MASTER;
2001
2002         if (bus->master_or_slave == I2C_MASTER) {
2003                 bus->int_time_stamp = jiffies;
2004                 if (!npcm_i2c_int_master_handler(bus))
2005                         return IRQ_HANDLED;
2006         }
2007 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2008         if (bus->slave) {
2009                 bus->master_or_slave = I2C_SLAVE;
2010                 if (npcm_i2c_int_slave_handler(bus))
2011                         return IRQ_HANDLED;
2012         }
2013 #endif
2014         /* clear status bits for spurious interrupts */
2015         npcm_i2c_clear_master_status(bus);
2016
2017         return IRQ_HANDLED;
2018 }
2019
2020 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2021                                        u8 slave_addr, u16 nwrite, u16 nread,
2022                                        u8 *write_data, u8 *read_data,
2023                                        bool use_PEC, bool use_read_block)
2024 {
2025         if (bus->state != I2C_IDLE) {
2026                 bus->cmd_err = -EBUSY;
2027                 return false;
2028         }
2029         bus->dest_addr = slave_addr << 1;
2030         bus->wr_buf = write_data;
2031         bus->wr_size = nwrite;
2032         bus->wr_ind = 0;
2033         bus->rd_buf = read_data;
2034         bus->rd_size = nread;
2035         bus->rd_ind = 0;
2036         bus->PEC_use = 0;
2037
2038         /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2039         if (nread)
2040                 bus->PEC_use = use_PEC;
2041
2042         bus->read_block_use = use_read_block;
2043         if (nread && !nwrite)
2044                 bus->operation = I2C_READ_OPER;
2045         else
2046                 bus->operation = I2C_WRITE_OPER;
2047         if (bus->fifo_use) {
2048                 u8 i2cfif_cts;
2049
2050                 npcm_i2c_select_bank(bus, I2C_BANK_1);
2051                 /* clear FIFO and relevant status bits. */
2052                 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2053                 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2054                 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2055                 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2056         }
2057
2058         bus->state = I2C_IDLE;
2059         npcm_i2c_stall_after_start(bus, true);
2060         npcm_i2c_master_start(bus);
2061         return true;
2062 }
2063
2064 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2065                                 int num)
2066 {
2067         struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2068         struct i2c_msg *msg0, *msg1;
2069         unsigned long time_left, flags;
2070         u16 nwrite, nread;
2071         u8 *write_data, *read_data;
2072         u8 slave_addr;
2073         unsigned long timeout;
2074         bool read_block = false;
2075         bool read_PEC = false;
2076         u8 bus_busy;
2077         unsigned long timeout_usec;
2078
2079         if (bus->state == I2C_DISABLE) {
2080                 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2081                 return -EINVAL;
2082         }
2083
2084         msg0 = &msgs[0];
2085         slave_addr = msg0->addr;
2086         if (msg0->flags & I2C_M_RD) { /* read */
2087                 nwrite = 0;
2088                 write_data = NULL;
2089                 read_data = msg0->buf;
2090                 if (msg0->flags & I2C_M_RECV_LEN) {
2091                         nread = 1;
2092                         read_block = true;
2093                         if (msg0->flags & I2C_CLIENT_PEC)
2094                                 read_PEC = true;
2095                 } else {
2096                         nread = msg0->len;
2097                 }
2098         } else { /* write */
2099                 nwrite = msg0->len;
2100                 write_data = msg0->buf;
2101                 nread = 0;
2102                 read_data = NULL;
2103                 if (num == 2) {
2104                         msg1 = &msgs[1];
2105                         read_data = msg1->buf;
2106                         if (msg1->flags & I2C_M_RECV_LEN) {
2107                                 nread = 1;
2108                                 read_block = true;
2109                                 if (msg1->flags & I2C_CLIENT_PEC)
2110                                         read_PEC = true;
2111                         } else {
2112                                 nread = msg1->len;
2113                                 read_block = false;
2114                         }
2115                 }
2116         }
2117
2118         /*
2119          * Adaptive TimeOut: estimated time in usec + 100% margin:
2120          * 2: double the timeout for clock stretching case
2121          * 9: bits per transaction (including the ack/nack)
2122          */
2123         timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2124         timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2125         if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2126                 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2127                 return -EINVAL;
2128         }
2129
2130         time_left = jiffies + timeout + 1;
2131         do {
2132                 /*
2133                  * we must clear slave address immediately when the bus is not
2134                  * busy, so we spinlock it, but we don't keep the lock for the
2135                  * entire while since it is too long.
2136                  */
2137                 spin_lock_irqsave(&bus->lock, flags);
2138                 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2139 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2140                 if (!bus_busy && bus->slave)
2141                         iowrite8((bus->slave->addr & 0x7F),
2142                                  bus->reg + NPCM_I2CADDR1);
2143 #endif
2144                 spin_unlock_irqrestore(&bus->lock, flags);
2145
2146         } while (time_is_after_jiffies(time_left) && bus_busy);
2147
2148         if (bus_busy) {
2149                 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2150                 npcm_i2c_reset(bus);
2151                 i2c_recover_bus(adap);
2152                 return -EAGAIN;
2153         }
2154
2155         npcm_i2c_init_params(bus);
2156         bus->dest_addr = slave_addr;
2157         bus->msgs = msgs;
2158         bus->msgs_num = num;
2159         bus->cmd_err = 0;
2160         bus->read_block_use = read_block;
2161
2162         reinit_completion(&bus->cmd_complete);
2163
2164         npcm_i2c_int_enable(bus, true);
2165
2166         if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2167                                        write_data, read_data, read_PEC,
2168                                        read_block)) {
2169                 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2170                                                         timeout);
2171
2172                 if (time_left == 0) {
2173                         if (bus->timeout_cnt < ULLONG_MAX)
2174                                 bus->timeout_cnt++;
2175                         if (bus->master_or_slave == I2C_MASTER) {
2176                                 i2c_recover_bus(adap);
2177                                 bus->cmd_err = -EIO;
2178                                 bus->state = I2C_IDLE;
2179                         }
2180                 }
2181         }
2182
2183         /* if there was BER, check if need to recover the bus: */
2184         if (bus->cmd_err == -EAGAIN)
2185                 bus->cmd_err = i2c_recover_bus(adap);
2186
2187         /*
2188          * After any type of error, check if LAST bit is still set,
2189          * due to a HW issue.
2190          * It cannot be cleared without resetting the module.
2191          */
2192         else if (bus->cmd_err &&
2193                  (NPCM_I2CRXF_CTL_LAST_PEC & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2194                 npcm_i2c_reset(bus);
2195
2196         /* after any xfer, successful or not, stall and EOB must be disabled */
2197         npcm_i2c_stall_after_start(bus, false);
2198         npcm_i2c_eob_int(bus, false);
2199
2200 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2201         /* reenable slave if it was enabled */
2202         if (bus->slave)
2203                 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2204                          bus->reg + NPCM_I2CADDR1);
2205 #else
2206         npcm_i2c_int_enable(bus, false);
2207 #endif
2208         return bus->cmd_err;
2209 }
2210
2211 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2212 {
2213         return I2C_FUNC_I2C |
2214                I2C_FUNC_SMBUS_EMUL |
2215                I2C_FUNC_SMBUS_BLOCK_DATA |
2216                I2C_FUNC_SMBUS_PEC |
2217                I2C_FUNC_SLAVE;
2218 }
2219
2220 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2221         .max_read_len = 32768,
2222         .max_write_len = 32768,
2223         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
2224 };
2225
2226 static const struct i2c_algorithm npcm_i2c_algo = {
2227         .master_xfer = npcm_i2c_master_xfer,
2228         .functionality = npcm_i2c_functionality,
2229 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2230         .reg_slave      = npcm_i2c_reg_slave,
2231         .unreg_slave    = npcm_i2c_unreg_slave,
2232 #endif
2233 };
2234
2235 /* i2c debugfs directory: used to keep health monitor of i2c devices */
2236 static struct dentry *npcm_i2c_debugfs_dir;
2237
2238 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2239                                   struct npcm_i2c *bus)
2240 {
2241         struct dentry *d;
2242
2243         if (!npcm_i2c_debugfs_dir)
2244                 return;
2245         d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
2246         if (IS_ERR_OR_NULL(d))
2247                 return;
2248         debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2249         debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2250         debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2251         debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2252         debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2253
2254         bus->debugfs = d;
2255 }
2256
2257 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2258 {
2259         struct npcm_i2c *bus;
2260         struct i2c_adapter *adap;
2261         struct clk *i2c_clk;
2262         static struct regmap *gcr_regmap;
2263         static struct regmap *clk_regmap;
2264         int irq;
2265         int ret;
2266
2267         bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2268         if (!bus)
2269                 return -ENOMEM;
2270
2271         bus->dev = &pdev->dev;
2272
2273         bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2274         /* core clk must be acquired to calculate module timing settings */
2275         i2c_clk = devm_clk_get(&pdev->dev, NULL);
2276         if (IS_ERR(i2c_clk))
2277                 return PTR_ERR(i2c_clk);
2278         bus->apb_clk = clk_get_rate(i2c_clk);
2279
2280         gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2281         if (IS_ERR(gcr_regmap))
2282                 return PTR_ERR(gcr_regmap);
2283         regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL);
2284
2285         clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk");
2286         if (IS_ERR(clk_regmap))
2287                 return PTR_ERR(clk_regmap);
2288
2289         bus->reg = devm_platform_ioremap_resource(pdev, 0);
2290         if (IS_ERR(bus->reg))
2291                 return PTR_ERR(bus->reg);
2292
2293         spin_lock_init(&bus->lock);
2294         init_completion(&bus->cmd_complete);
2295
2296         adap = &bus->adap;
2297         adap->owner = THIS_MODULE;
2298         adap->retries = 3;
2299         adap->timeout = msecs_to_jiffies(35);
2300         adap->algo = &npcm_i2c_algo;
2301         adap->quirks = &npcm_i2c_quirks;
2302         adap->algo_data = bus;
2303         adap->dev.parent = &pdev->dev;
2304         adap->dev.of_node = pdev->dev.of_node;
2305         adap->nr = pdev->id;
2306
2307         irq = platform_get_irq(pdev, 0);
2308         if (irq < 0)
2309                 return irq;
2310
2311         ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2312                                dev_name(bus->dev), bus);
2313         if (ret)
2314                 return ret;
2315
2316         ret = __npcm_i2c_init(bus, pdev);
2317         if (ret)
2318                 return ret;
2319
2320         npcm_i2c_recovery_init(adap);
2321
2322         i2c_set_adapdata(adap, bus);
2323
2324         snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2325                  bus->num);
2326         ret = i2c_add_numbered_adapter(&bus->adap);
2327         if (ret)
2328                 return ret;
2329
2330         platform_set_drvdata(pdev, bus);
2331         npcm_i2c_init_debugfs(pdev, bus);
2332         return 0;
2333 }
2334
2335 static int npcm_i2c_remove_bus(struct platform_device *pdev)
2336 {
2337         unsigned long lock_flags;
2338         struct npcm_i2c *bus = platform_get_drvdata(pdev);
2339
2340         debugfs_remove_recursive(bus->debugfs);
2341         spin_lock_irqsave(&bus->lock, lock_flags);
2342         npcm_i2c_disable(bus);
2343         spin_unlock_irqrestore(&bus->lock, lock_flags);
2344         i2c_del_adapter(&bus->adap);
2345         return 0;
2346 }
2347
2348 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2349         { .compatible = "nuvoton,npcm750-i2c", },
2350         {}
2351 };
2352 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2353
2354 static struct platform_driver npcm_i2c_bus_driver = {
2355         .probe = npcm_i2c_probe_bus,
2356         .remove = npcm_i2c_remove_bus,
2357         .driver = {
2358                 .name = "nuvoton-i2c",
2359                 .of_match_table = npcm_i2c_bus_of_table,
2360         }
2361 };
2362
2363 static int __init npcm_i2c_init(void)
2364 {
2365         npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
2366         return platform_driver_register(&npcm_i2c_bus_driver);
2367 }
2368 module_init(npcm_i2c_init);
2369
2370 static void __exit npcm_i2c_exit(void)
2371 {
2372         platform_driver_unregister(&npcm_i2c_bus_driver);
2373         debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2374 }
2375 module_exit(npcm_i2c_exit);
2376
2377 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2378 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2379 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2380 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2381 MODULE_LICENSE("GPL v2");