drivers/i2c/busses/i2c-mv64xxx.c

   1 /*
   2  * Driver for the i2c controller on the Marvell line of host bridges
   3  * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
   4  *
   5  * Author: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mv643xx_i2c.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/reset.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/delay.h>
  28
  29 #define MV64XXX_I2C_ADDR_ADDR(val)                      ((val & 0x7f) << 1)
  30 #define MV64XXX_I2C_BAUD_DIV_N(val)                     (val & 0x7)
  31 #define MV64XXX_I2C_BAUD_DIV_M(val)                     ((val & 0xf) << 3)
  32
  33 #define MV64XXX_I2C_REG_CONTROL_ACK                     BIT(2)
  34 #define MV64XXX_I2C_REG_CONTROL_IFLG                    BIT(3)
  35 #define MV64XXX_I2C_REG_CONTROL_STOP                    BIT(4)
  36 #define MV64XXX_I2C_REG_CONTROL_START                   BIT(5)
  37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN                  BIT(6)
  38 #define MV64XXX_I2C_REG_CONTROL_INTEN                   BIT(7)
  39
  40 /* Ctlr status values */
  41 #define MV64XXX_I2C_STATUS_BUS_ERR                      0x00
  42 #define MV64XXX_I2C_STATUS_MAST_START                   0x08
  43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START            0x10
  44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK             0x18
  45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK          0x20
  46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK                  0x28
  47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK               0x30
  48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB                0x38
  49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK             0x40
  50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK          0x48
  51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK             0x50
  52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK          0x58
  53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK           0xd0
  54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK        0xd8
  55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK           0xe0
  56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK        0xe8
  57 #define MV64XXX_I2C_STATUS_NO_STATUS                    0xf8
  58
  59 /* Register defines (I2C bridge) */
  60 #define MV64XXX_I2C_REG_TX_DATA_LO                      0xc0
  61 #define MV64XXX_I2C_REG_TX_DATA_HI                      0xc4
  62 #define MV64XXX_I2C_REG_RX_DATA_LO                      0xc8
  63 #define MV64XXX_I2C_REG_RX_DATA_HI                      0xcc
  64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL                  0xd0
  65 #define MV64XXX_I2C_REG_BRIDGE_STATUS                   0xd4
  66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE               0xd8
  67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK                0xdC
  68 #define MV64XXX_I2C_REG_BRIDGE_TIMING                   0xe0
  69
  70 /* Bridge Control values */
  71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR                   BIT(0)
  72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD                   BIT(1)
  73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT           2
  74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT             BIT(12)
  75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT        13
  76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT        16
  77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE               BIT(19)
  78 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START       BIT(20)
  79
  80 /* Bridge Status values */
  81 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR                 BIT(0)
  82
  83 /* Driver states */
  84 enum {
  85         MV64XXX_I2C_STATE_INVALID,
  86         MV64XXX_I2C_STATE_IDLE,
  87         MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
  88         MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
  89         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
  90         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
  91         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
  92         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
  93 };
  94
  95 /* Driver actions */
  96 enum {
  97         MV64XXX_I2C_ACTION_INVALID,
  98         MV64XXX_I2C_ACTION_CONTINUE,
  99         MV64XXX_I2C_ACTION_SEND_RESTART,
 100         MV64XXX_I2C_ACTION_SEND_ADDR_1,
 101         MV64XXX_I2C_ACTION_SEND_ADDR_2,
 102         MV64XXX_I2C_ACTION_SEND_DATA,
 103         MV64XXX_I2C_ACTION_RCV_DATA,
 104         MV64XXX_I2C_ACTION_RCV_DATA_STOP,
 105         MV64XXX_I2C_ACTION_SEND_STOP,
 106 };
 107
 108 struct mv64xxx_i2c_regs {
 109         u8      addr;
 110         u8      ext_addr;
 111         u8      data;
 112         u8      control;
 113         u8      status;
 114         u8      clock;
 115         u8      soft_reset;
 116 };
 117
 118 struct mv64xxx_i2c_data {
 119         struct i2c_msg          *msgs;
 120         int                     num_msgs;
 121         int                     irq;
 122         u32                     state;
 123         u32                     action;
 124         u32                     aborting;
 125         u32                     cntl_bits;
 126         void __iomem            *reg_base;
 127         struct mv64xxx_i2c_regs reg_offsets;
 128         u32                     addr1;
 129         u32                     addr2;
 130         u32                     bytes_left;
 131         u32                     byte_posn;
 132         u32                     send_stop;
 133         u32                     block;
 134         int                     rc;
 135         u32                     freq_m;
 136         u32                     freq_n;
 137         struct clk              *clk;
 138         struct clk              *reg_clk;
 139         wait_queue_head_t       waitq;
 140         spinlock_t              lock;
 141         struct i2c_msg          *msg;
 142         struct i2c_adapter      adapter;
 143         bool                    offload_enabled;
 144 /* 5us delay in order to avoid repeated start timing violation */
 145         bool                    errata_delay;
 146         struct reset_control    *rstc;
 147         bool                    irq_clear_inverted;
 148         /* Clk div is 2 to the power n, not 2 to the power n + 1 */
 149         bool                    clk_n_base_0;
 150 };
 151
 152 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
 153         .addr           = 0x00,
 154         .ext_addr       = 0x10,
 155         .data           = 0x04,
 156         .control        = 0x08,
 157         .status         = 0x0c,
 158         .clock          = 0x0c,
 159         .soft_reset     = 0x1c,
 160 };
 161
 162 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
 163         .addr           = 0x00,
 164         .ext_addr       = 0x04,
 165         .data           = 0x08,
 166         .control        = 0x0c,
 167         .status         = 0x10,
 168         .clock          = 0x14,
 169         .soft_reset     = 0x18,
 170 };
 171
 172 static void
 173 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
 174         struct i2c_msg *msg)
 175 {
 176         u32     dir = 0;
 177
 178         drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
 179                 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
 180
 181         if (msg->flags & I2C_M_RD)
 182                 dir = 1;
 183
 184         if (msg->flags & I2C_M_TEN) {
 185                 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
 186                 drv_data->addr2 = (u32)msg->addr & 0xff;
 187         } else {
 188                 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
 189                 drv_data->addr2 = 0;
 190         }
 191 }
 192
 193 /*
 194  *****************************************************************************
 195  *
 196  *      Finite State Machine & Interrupt Routines
 197  *
 198  *****************************************************************************
 199  */
 200
 201 /* Reset hardware and initialize FSM */
 202 static void
 203 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
 204 {
 205         if (drv_data->offload_enabled) {
 206                 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
 207                 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
 208                 writel(0, drv_data->reg_base +
 209                         MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 210                 writel(0, drv_data->reg_base +
 211                         MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
 212         }
 213
 214         writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
 215         writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
 216                 drv_data->reg_base + drv_data->reg_offsets.clock);
 217         writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
 218         writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
 219         writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
 220                 drv_data->reg_base + drv_data->reg_offsets.control);
 221         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 222 }
 223
 224 static void
 225 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
 226 {
 227         /*
 228          * If state is idle, then this is likely the remnants of an old
 229          * operation that driver has given up on or the user has killed.
 230          * If so, issue the stop condition and go to idle.
 231          */
 232         if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
 233                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 234                 return;
 235         }
 236
 237         /* The status from the ctlr [mostly] tells us what to do next */
 238         switch (status) {
 239         /* Start condition interrupt */
 240         case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
 241         case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
 242                 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
 243                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
 244                 break;
 245
 246         /* Performing a write */
 247         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
 248                 if (drv_data->msg->flags & I2C_M_TEN) {
 249                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
 250                         drv_data->state =
 251                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
 252                         break;
 253                 }
 254                 fallthrough;
 255         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
 256         case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
 257                 if ((drv_data->bytes_left == 0)
 258                                 || (drv_data->aborting
 259                                         && (drv_data->byte_posn != 0))) {
 260                         if (drv_data->send_stop || drv_data->aborting) {
 261                                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 262                                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 263                         } else {
 264                                 drv_data->action =
 265                                         MV64XXX_I2C_ACTION_SEND_RESTART;
 266                                 drv_data->state =
 267                                         MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
 268                         }
 269                 } else {
 270                         drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
 271                         drv_data->state =
 272                                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
 273                         drv_data->bytes_left--;
 274                 }
 275                 break;
 276
 277         /* Performing a read */
 278         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
 279                 if (drv_data->msg->flags & I2C_M_TEN) {
 280                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
 281                         drv_data->state =
 282                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
 283                         break;
 284                 }
 285                 fallthrough;
 286         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
 287                 if (drv_data->bytes_left == 0) {
 288                         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 289                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 290                         break;
 291                 }
 292                 fallthrough;
 293         case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
 294                 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
 295                         drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
 296                 else {
 297                         drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
 298                         drv_data->bytes_left--;
 299                 }
 300                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
 301
 302                 if ((drv_data->bytes_left == 1) || drv_data->aborting)
 303                         drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
 304                 break;
 305
 306         case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
 307                 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
 308                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 309                 break;
 310
 311         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
 312         case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
 313         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
 314                 /* Doesn't seem to be a device at other end */
 315                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 316                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 317                 drv_data->rc = -ENXIO;
 318                 break;
 319
 320         default:
 321                 dev_err(&drv_data->adapter.dev,
 322                         "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
 323                         "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
 324                          drv_data->state, status, drv_data->msg->addr,
 325                          drv_data->msg->flags);
 326                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 327                 mv64xxx_i2c_hw_init(drv_data);
 328                 drv_data->rc = -EIO;
 329         }
 330 }
 331
 332 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
 333 {
 334         drv_data->msg = drv_data->msgs;
 335         drv_data->byte_posn = 0;
 336         drv_data->bytes_left = drv_data->msg->len;
 337         drv_data->aborting = 0;
 338         drv_data->rc = 0;
 339
 340         mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
 341         writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
 342                drv_data->reg_base + drv_data->reg_offsets.control);
 343 }
 344
 345 static void
 346 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 347 {
 348         switch(drv_data->action) {
 349         case MV64XXX_I2C_ACTION_SEND_RESTART:
 350                 /* We should only get here if we have further messages */
 351                 BUG_ON(drv_data->num_msgs == 0);
 352
 353                 drv_data->msgs++;
 354                 drv_data->num_msgs--;
 355                 mv64xxx_i2c_send_start(drv_data);
 356
 357                 if (drv_data->errata_delay)
 358                         udelay(5);
 359
 360                 /*
 361                  * We're never at the start of the message here, and by this
 362                  * time it's already too late to do any protocol mangling.
 363                  * Thankfully, do not advertise support for that feature.
 364                  */
 365                 drv_data->send_stop = drv_data->num_msgs == 1;
 366                 break;
 367
 368         case MV64XXX_I2C_ACTION_CONTINUE:
 369                 writel(drv_data->cntl_bits,
 370                         drv_data->reg_base + drv_data->reg_offsets.control);
 371                 break;
 372
 373         case MV64XXX_I2C_ACTION_SEND_ADDR_1:
 374                 writel(drv_data->addr1,
 375                         drv_data->reg_base + drv_data->reg_offsets.data);
 376                 writel(drv_data->cntl_bits,
 377                         drv_data->reg_base + drv_data->reg_offsets.control);
 378                 break;
 379
 380         case MV64XXX_I2C_ACTION_SEND_ADDR_2:
 381                 writel(drv_data->addr2,
 382                         drv_data->reg_base + drv_data->reg_offsets.data);
 383                 writel(drv_data->cntl_bits,
 384                         drv_data->reg_base + drv_data->reg_offsets.control);
 385                 break;
 386
 387         case MV64XXX_I2C_ACTION_SEND_DATA:
 388                 writel(drv_data->msg->buf[drv_data->byte_posn++],
 389                         drv_data->reg_base + drv_data->reg_offsets.data);
 390                 writel(drv_data->cntl_bits,
 391                         drv_data->reg_base + drv_data->reg_offsets.control);
 392                 break;
 393
 394         case MV64XXX_I2C_ACTION_RCV_DATA:
 395                 drv_data->msg->buf[drv_data->byte_posn++] =
 396                         readl(drv_data->reg_base + drv_data->reg_offsets.data);
 397                 writel(drv_data->cntl_bits,
 398                         drv_data->reg_base + drv_data->reg_offsets.control);
 399                 break;
 400
 401         case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
 402                 drv_data->msg->buf[drv_data->byte_posn++] =
 403                         readl(drv_data->reg_base + drv_data->reg_offsets.data);
 404                 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 405                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 406                         drv_data->reg_base + drv_data->reg_offsets.control);
 407                 drv_data->block = 0;
 408                 if (drv_data->errata_delay)
 409                         udelay(5);
 410
 411                 wake_up(&drv_data->waitq);
 412                 break;
 413
 414         case MV64XXX_I2C_ACTION_INVALID:
 415         default:
 416                 dev_err(&drv_data->adapter.dev,
 417                         "mv64xxx_i2c_do_action: Invalid action: %d\n",
 418                         drv_data->action);
 419                 drv_data->rc = -EIO;
 420                 fallthrough;
 421         case MV64XXX_I2C_ACTION_SEND_STOP:
 422                 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 423                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 424                         drv_data->reg_base + drv_data->reg_offsets.control);
 425                 drv_data->block = 0;
 426                 wake_up(&drv_data->waitq);
 427                 break;
 428         }
 429 }
 430
 431 static void
 432 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
 433                                  struct i2c_msg *msg)
 434 {
 435         u32 buf[2];
 436
 437         buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
 438         buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
 439
 440         memcpy(msg->buf, buf, msg->len);
 441 }
 442
 443 static int
 444 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
 445 {
 446         u32 cause, status;
 447
 448         cause = readl(drv_data->reg_base +
 449                       MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 450         if (!cause)
 451                 return IRQ_NONE;
 452
 453         status = readl(drv_data->reg_base +
 454                        MV64XXX_I2C_REG_BRIDGE_STATUS);
 455
 456         if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
 457                 drv_data->rc = -EIO;
 458                 goto out;
 459         }
 460
 461         drv_data->rc = 0;
 462
 463         /*
 464          * Transaction is a one message read transaction, read data
 465          * for this message.
 466          */
 467         if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
 468                 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
 469                 drv_data->msgs++;
 470                 drv_data->num_msgs--;
 471         }
 472         /*
 473          * Transaction is a two messages write/read transaction, read
 474          * data for the second (read) message.
 475          */
 476         else if (drv_data->num_msgs == 2 &&
 477                  !(drv_data->msgs[0].flags & I2C_M_RD) &&
 478                  drv_data->msgs[1].flags & I2C_M_RD) {
 479                 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
 480                 drv_data->msgs += 2;
 481                 drv_data->num_msgs -= 2;
 482         }
 483
 484 out:
 485         writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
 486         writel(0, drv_data->reg_base +
 487                MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 488         drv_data->block = 0;
 489
 490         wake_up(&drv_data->waitq);
 491
 492         return IRQ_HANDLED;
 493 }
 494
 495 static irqreturn_t
 496 mv64xxx_i2c_intr(int irq, void *dev_id)
 497 {
 498         struct mv64xxx_i2c_data *drv_data = dev_id;
 499         u32             status;
 500         irqreturn_t     rc = IRQ_NONE;
 501
 502         spin_lock(&drv_data->lock);
 503
 504         if (drv_data->offload_enabled)
 505                 rc = mv64xxx_i2c_intr_offload(drv_data);
 506
 507         while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
 508                                                 MV64XXX_I2C_REG_CONTROL_IFLG) {
 509                 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
 510                 mv64xxx_i2c_fsm(drv_data, status);
 511                 mv64xxx_i2c_do_action(drv_data);
 512
 513                 if (drv_data->irq_clear_inverted)
 514                         writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
 515                                drv_data->reg_base + drv_data->reg_offsets.control);
 516
 517                 rc = IRQ_HANDLED;
 518         }
 519         spin_unlock(&drv_data->lock);
 520
 521         return rc;
 522 }
 523
 524 /*
 525  *****************************************************************************
 526  *
 527  *      I2C Msg Execution Routines
 528  *
 529  *****************************************************************************
 530  */
 531 static void
 532 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
 533 {
 534         long            time_left;
 535         unsigned long   flags;
 536         char            abort = 0;
 537
 538         time_left = wait_event_timeout(drv_data->waitq,
 539                 !drv_data->block, drv_data->adapter.timeout);
 540
 541         spin_lock_irqsave(&drv_data->lock, flags);
 542         if (!time_left) { /* Timed out */
 543                 drv_data->rc = -ETIMEDOUT;
 544                 abort = 1;
 545         } else if (time_left < 0) { /* Interrupted/Error */
 546                 drv_data->rc = time_left; /* errno value */
 547                 abort = 1;
 548         }
 549
 550         if (abort && drv_data->block) {
 551                 drv_data->aborting = 1;
 552                 spin_unlock_irqrestore(&drv_data->lock, flags);
 553
 554                 time_left = wait_event_timeout(drv_data->waitq,
 555                         !drv_data->block, drv_data->adapter.timeout);
 556
 557                 if ((time_left <= 0) && drv_data->block) {
 558                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 559                         dev_err(&drv_data->adapter.dev,
 560                                 "mv64xxx: I2C bus locked, block: %d, "
 561                                 "time_left: %d\n", drv_data->block,
 562                                 (int)time_left);
 563                         mv64xxx_i2c_hw_init(drv_data);
 564                 }
 565         } else
 566                 spin_unlock_irqrestore(&drv_data->lock, flags);
 567 }
 568
 569 static int
 570 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
 571                                 int is_last)
 572 {
 573         unsigned long   flags;
 574
 575         spin_lock_irqsave(&drv_data->lock, flags);
 576
 577         drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
 578
 579         drv_data->send_stop = is_last;
 580         drv_data->block = 1;
 581         mv64xxx_i2c_send_start(drv_data);
 582         spin_unlock_irqrestore(&drv_data->lock, flags);
 583
 584         mv64xxx_i2c_wait_for_completion(drv_data);
 585         return drv_data->rc;
 586 }
 587
 588 static void
 589 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
 590 {
 591         struct i2c_msg *msg = drv_data->msgs;
 592         u32 buf[2];
 593
 594         memcpy(buf, msg->buf, msg->len);
 595
 596         writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
 597         writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
 598 }
 599
 600 static int
 601 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
 602 {
 603         struct i2c_msg *msgs = drv_data->msgs;
 604         int num = drv_data->num_msgs;
 605         unsigned long ctrl_reg;
 606         unsigned long flags;
 607
 608         spin_lock_irqsave(&drv_data->lock, flags);
 609
 610         /* Build transaction */
 611         ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
 612                 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
 613
 614         if (msgs[0].flags & I2C_M_TEN)
 615                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
 616
 617         /* Single write message transaction */
 618         if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
 619                 size_t len = msgs[0].len - 1;
 620
 621                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
 622                         (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
 623                 mv64xxx_i2c_prepare_tx(drv_data);
 624         }
 625         /* Single read message transaction */
 626         else if (num == 1 && msgs[0].flags & I2C_M_RD) {
 627                 size_t len = msgs[0].len - 1;
 628
 629                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
 630                         (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
 631         }
 632         /*
 633          * Transaction with one write and one read message. This is
 634          * guaranteed by the mv64xx_i2c_can_offload() checks.
 635          */
 636         else if (num == 2) {
 637                 size_t lentx = msgs[0].len - 1;
 638                 size_t lenrx = msgs[1].len - 1;
 639
 640                 ctrl_reg |=
 641                         MV64XXX_I2C_BRIDGE_CONTROL_RD |
 642                         MV64XXX_I2C_BRIDGE_CONTROL_WR |
 643                         (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
 644                         (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
 645                         MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
 646                 mv64xxx_i2c_prepare_tx(drv_data);
 647         }
 648
 649         /* Execute transaction */
 650         drv_data->block = 1;
 651         writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
 652         spin_unlock_irqrestore(&drv_data->lock, flags);
 653
 654         mv64xxx_i2c_wait_for_completion(drv_data);
 655
 656         return drv_data->rc;
 657 }
 658
 659 static bool
 660 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
 661 {
 662         return msg->len <= 8 && msg->len >= 1;
 663 }
 664
 665 static bool
 666 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
 667 {
 668         struct i2c_msg *msgs = drv_data->msgs;
 669         int num = drv_data->num_msgs;
 670
 671         if (!drv_data->offload_enabled)
 672                 return false;
 673
 674         /*
 675          * We can offload a transaction consisting of a single
 676          * message, as long as the message has a length between 1 and
 677          * 8 bytes.
 678          */
 679         if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
 680                 return true;
 681
 682         /*
 683          * We can offload a transaction consisting of two messages, if
 684          * the first is a write and a second is a read, and both have
 685          * a length between 1 and 8 bytes.
 686          */
 687         if (num == 2 &&
 688             mv64xxx_i2c_valid_offload_sz(msgs) &&
 689             mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
 690             !(msgs[0].flags & I2C_M_RD) &&
 691             msgs[1].flags & I2C_M_RD)
 692                 return true;
 693
 694         return false;
 695 }
 696
 697 /*
 698  *****************************************************************************
 699  *
 700  *      I2C Core Support Routines (Interface to higher level I2C code)
 701  *
 702  *****************************************************************************
 703  */
 704 static u32
 705 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
 706 {
 707         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
 708 }
 709
 710 static int
 711 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 712 {
 713         struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
 714         int rc, ret = num;
 715
 716         BUG_ON(drv_data->msgs != NULL);
 717         drv_data->msgs = msgs;
 718         drv_data->num_msgs = num;
 719
 720         if (mv64xxx_i2c_can_offload(drv_data))
 721                 rc = mv64xxx_i2c_offload_xfer(drv_data);
 722         else
 723                 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
 724
 725         if (rc < 0)
 726                 ret = rc;
 727
 728         drv_data->num_msgs = 0;
 729         drv_data->msgs = NULL;
 730
 731         return ret;
 732 }
 733
 734 static const struct i2c_algorithm mv64xxx_i2c_algo = {
 735         .master_xfer = mv64xxx_i2c_xfer,
 736         .functionality = mv64xxx_i2c_functionality,
 737 };
 738
 739 /*
 740  *****************************************************************************
 741  *
 742  *      Driver Interface & Early Init Routines
 743  *
 744  *****************************************************************************
 745  */
 746 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
 747         { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
 748         { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
 749         { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 750         { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 751         { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 752         {}
 753 };
 754 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
 755
 756 #ifdef CONFIG_OF
 757 static int
 758 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
 759                   const int tclk, const int n, const int m)
 760 {
 761         if (drv_data->clk_n_base_0)
 762                 return tclk / (10 * (m + 1) * (1 << n));
 763         else
 764                 return tclk / (10 * (m + 1) * (2 << n));
 765 }
 766
 767 static bool
 768 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
 769                           const u32 req_freq, const u32 tclk)
 770 {
 771         int freq, delta, best_delta = INT_MAX;
 772         int m, n;
 773
 774         for (n = 0; n <= 7; n++)
 775                 for (m = 0; m <= 15; m++) {
 776                         freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
 777                         delta = req_freq - freq;
 778                         if (delta >= 0 && delta < best_delta) {
 779                                 drv_data->freq_m = m;
 780                                 drv_data->freq_n = n;
 781                                 best_delta = delta;
 782                         }
 783                         if (best_delta == 0)
 784                                 return true;
 785                 }
 786         if (best_delta == INT_MAX)
 787                 return false;
 788         return true;
 789 }
 790
 791 static int
 792 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 793                   struct device *dev)
 794 {
 795         const struct of_device_id *device;
 796         struct device_node *np = dev->of_node;
 797         u32 bus_freq, tclk;
 798         int rc = 0;
 799
 800         /* CLK is mandatory when using DT to describe the i2c bus. We
 801          * need to know tclk in order to calculate bus clock
 802          * factors.
 803          */
 804         if (IS_ERR(drv_data->clk)) {
 805                 rc = -ENODEV;
 806                 goto out;
 807         }
 808         tclk = clk_get_rate(drv_data->clk);
 809
 810         if (of_property_read_u32(np, "clock-frequency", &bus_freq))
 811                 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
 812
 813         if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
 814             of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
 815                 drv_data->clk_n_base_0 = true;
 816
 817         if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
 818                 rc = -EINVAL;
 819                 goto out;
 820         }
 821
 822         drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
 823         if (IS_ERR(drv_data->rstc)) {
 824                 rc = PTR_ERR(drv_data->rstc);
 825                 goto out;
 826         }
 827         reset_control_deassert(drv_data->rstc);
 828
 829         /* Its not yet defined how timeouts will be specified in device tree.
 830          * So hard code the value to 1 second.
 831          */
 832         drv_data->adapter.timeout = HZ;
 833
 834         device = of_match_device(mv64xxx_i2c_of_match_table, dev);
 835         if (!device)
 836                 return -ENODEV;
 837
 838         memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
 839
 840         /*
 841          * For controllers embedded in new SoCs activate the
 842          * Transaction Generator support and the errata fix.
 843          */
 844         if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
 845                 drv_data->offload_enabled = true;
 846                 /* The delay is only needed in standard mode (100kHz) */
 847                 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 848                         drv_data->errata_delay = true;
 849         }
 850
 851         if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
 852                 drv_data->offload_enabled = false;
 853                 /* The delay is only needed in standard mode (100kHz) */
 854                 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 855                         drv_data->errata_delay = true;
 856         }
 857
 858         if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
 859                 drv_data->irq_clear_inverted = true;
 860
 861 out:
 862         return rc;
 863 }
 864 #else /* CONFIG_OF */
 865 static int
 866 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 867                   struct device *dev)
 868 {
 869         return -ENODEV;
 870 }
 871 #endif /* CONFIG_OF */
 872
 873 static int
 874 mv64xxx_i2c_probe(struct platform_device *pd)
 875 {
 876         struct mv64xxx_i2c_data         *drv_data;
 877         struct mv64xxx_i2c_pdata        *pdata = dev_get_platdata(&pd->dev);
 878         int     rc;
 879
 880         if ((!pdata && !pd->dev.of_node))
 881                 return -ENODEV;
 882
 883         drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
 884                                 GFP_KERNEL);
 885         if (!drv_data)
 886                 return -ENOMEM;
 887
 888         drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
 889         if (IS_ERR(drv_data->reg_base))
 890                 return PTR_ERR(drv_data->reg_base);
 891
 892         strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
 893                 sizeof(drv_data->adapter.name));
 894
 895         init_waitqueue_head(&drv_data->waitq);
 896         spin_lock_init(&drv_data->lock);
 897
 898         /* Not all platforms have clocks */
 899         drv_data->clk = devm_clk_get(&pd->dev, NULL);
 900         if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
 901                 return -EPROBE_DEFER;
 902         if (!IS_ERR(drv_data->clk))
 903                 clk_prepare_enable(drv_data->clk);
 904
 905         drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
 906         if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
 907                 return -EPROBE_DEFER;
 908         if (!IS_ERR(drv_data->reg_clk))
 909                 clk_prepare_enable(drv_data->reg_clk);
 910
 911         drv_data->irq = platform_get_irq(pd, 0);
 912
 913         if (pdata) {
 914                 drv_data->freq_m = pdata->freq_m;
 915                 drv_data->freq_n = pdata->freq_n;
 916                 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
 917                 drv_data->offload_enabled = false;
 918                 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
 919         } else if (pd->dev.of_node) {
 920                 rc = mv64xxx_of_config(drv_data, &pd->dev);
 921                 if (rc)
 922                         goto exit_clk;
 923         }
 924         if (drv_data->irq < 0) {
 925                 rc = drv_data->irq;
 926                 goto exit_reset;
 927         }
 928
 929         drv_data->adapter.dev.parent = &pd->dev;
 930         drv_data->adapter.algo = &mv64xxx_i2c_algo;
 931         drv_data->adapter.owner = THIS_MODULE;
 932         drv_data->adapter.class = I2C_CLASS_DEPRECATED;
 933         drv_data->adapter.nr = pd->id;
 934         drv_data->adapter.dev.of_node = pd->dev.of_node;
 935         platform_set_drvdata(pd, drv_data);
 936         i2c_set_adapdata(&drv_data->adapter, drv_data);
 937
 938         mv64xxx_i2c_hw_init(drv_data);
 939
 940         rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
 941                          MV64XXX_I2C_CTLR_NAME, drv_data);
 942         if (rc) {
 943                 dev_err(&drv_data->adapter.dev,
 944                         "mv64xxx: Can't register intr handler irq%d: %d\n",
 945                         drv_data->irq, rc);
 946                 goto exit_reset;
 947         } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
 948                 dev_err(&drv_data->adapter.dev,
 949                         "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
 950                 goto exit_free_irq;
 951         }
 952
 953         return 0;
 954
 955 exit_free_irq:
 956         free_irq(drv_data->irq, drv_data);
 957 exit_reset:
 958         reset_control_assert(drv_data->rstc);
 959 exit_clk:
 960         clk_disable_unprepare(drv_data->reg_clk);
 961         clk_disable_unprepare(drv_data->clk);
 962
 963         return rc;
 964 }
 965
 966 static int
 967 mv64xxx_i2c_remove(struct platform_device *dev)
 968 {
 969         struct mv64xxx_i2c_data         *drv_data = platform_get_drvdata(dev);
 970
 971         i2c_del_adapter(&drv_data->adapter);
 972         free_irq(drv_data->irq, drv_data);
 973         reset_control_assert(drv_data->rstc);
 974         clk_disable_unprepare(drv_data->reg_clk);
 975         clk_disable_unprepare(drv_data->clk);
 976
 977         return 0;
 978 }
 979
 980 #ifdef CONFIG_PM
 981 static int mv64xxx_i2c_resume(struct device *dev)
 982 {
 983         struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
 984
 985         mv64xxx_i2c_hw_init(drv_data);
 986
 987         return 0;
 988 }
 989
 990 static const struct dev_pm_ops mv64xxx_i2c_pm = {
 991         .resume = mv64xxx_i2c_resume,
 992 };
 993
 994 #define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
 995 #else
 996 #define mv64xxx_i2c_pm_ops NULL
 997 #endif
 998
 999 static struct platform_driver mv64xxx_i2c_driver = {
1000         .probe  = mv64xxx_i2c_probe,
1001         .remove = mv64xxx_i2c_remove,
1002         .driver = {
1003                 .name   = MV64XXX_I2C_CTLR_NAME,
1004                 .pm     = mv64xxx_i2c_pm_ops,
1005                 .of_match_table = mv64xxx_i2c_of_match_table,
1006         },
1007 };
1008
1009 module_platform_driver(mv64xxx_i2c_driver);
1010
1011 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1012 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1013 MODULE_LICENSE("GPL");