2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/slab.h>
24 #include <linux/clk.h>
26 #include <linux/iopoll.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/i2c.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
32 #include <asm/mpc52xx.h>
33 #include <asm/mpc85xx.h>
34 #include <sysdev/fsl_soc.h>
36 #define DRV_NAME "mpc-i2c"
38 #define MPC_I2C_CLOCK_LEGACY 0
39 #define MPC_I2C_CLOCK_PRESERVE (~0U)
41 #define MPC_I2C_FDR 0x04
42 #define MPC_I2C_CR 0x08
43 #define MPC_I2C_SR 0x0c
44 #define MPC_I2C_DR 0x10
45 #define MPC_I2C_DFSRR 0x14
67 wait_queue_head_t queue;
68 struct i2c_adapter adap;
71 #ifdef CONFIG_PM_SLEEP
75 bool has_errata_A004447;
78 struct mpc_i2c_divider {
80 u16 fdr; /* including dfsrr */
84 void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
85 u32 clock, u32 prescaler);
89 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
91 writeb(x, i2c->base + MPC_I2C_CR);
94 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
96 struct mpc_i2c *i2c = dev_id;
97 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
98 /* Read again to allow register to stabilise */
99 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
100 writeb(0, i2c->base + MPC_I2C_SR);
101 wake_up(&i2c->queue);
107 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
108 * the bus, because it wants to send ACK.
109 * Following sequence of enabling/disabling and sending start/stop generates
110 * the 9 pulses, each with a START then ending with STOP, so it's all OK.
112 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
117 for (k = 9; k; k--) {
119 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
120 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
121 readb(i2c->base + MPC_I2C_DR); /* init xfer */
122 udelay(15); /* let it hit the bus */
123 local_irq_save(flags); /* should not be delayed further */
124 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
125 readb(i2c->base + MPC_I2C_DR);
128 local_irq_restore(flags);
130 writeccr(i2c, CCR_MEN); /* Initiate STOP */
131 readb(i2c->base + MPC_I2C_DR);
132 udelay(15); /* Let STOP propagate */
136 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
138 unsigned long orig_jiffies = jiffies;
143 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
145 if (time_after(jiffies, orig_jiffies + timeout)) {
146 dev_dbg(i2c->dev, "timeout\n");
152 cmd_err = readb(i2c->base + MPC_I2C_SR);
153 writeb(0, i2c->base + MPC_I2C_SR);
156 result = wait_event_timeout(i2c->queue,
157 (i2c->interrupt & CSR_MIF), timeout);
159 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
160 dev_dbg(i2c->dev, "wait timeout\n");
165 cmd_err = i2c->interrupt;
172 if (!(cmd_err & CSR_MCF)) {
173 dev_dbg(i2c->dev, "unfinished\n");
177 if (cmd_err & CSR_MAL) {
178 dev_dbg(i2c->dev, "MAL\n");
182 if (writing && (cmd_err & CSR_RXAK)) {
183 dev_dbg(i2c->dev, "No RXAK\n");
185 writeccr(i2c, CCR_MEN);
191 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
193 void __iomem *addr = i2c->base + MPC_I2C_SR;
196 return readb_poll_timeout(addr, val, val & mask, 0, 100);
200 * Workaround for Erratum A004447. From the P2040CE Rev Q
202 * 1. Set up the frequency divider and sampling rate.
204 * 3. Poll for I2CSR[MBB] to get set.
205 * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
206 * step 5. If MAL is not set, then go to step 13.
210 * 8. Poll for I2CSR[MBB] to get set.
211 * 9. Issue read to I2CDR.
212 * 10. Poll for I2CSR[MIF] to be set.
214 * 12. Workaround complete. Skip the next steps.
215 * 13. Issue read to I2CDR.
216 * 14. Poll for I2CSR[MIF] to be set.
219 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
224 writeccr(i2c, CCR_MEN | CCR_MSTA);
225 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
227 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
231 val = readb(i2c->base + MPC_I2C_SR);
235 writeccr(i2c, CCR_MSTA | CCR_RSVD);
236 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
237 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
239 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
242 val = readb(i2c->base + MPC_I2C_DR);
243 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
245 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
248 writeccr(i2c, CCR_MEN | CCR_RSVD);
250 val = readb(i2c->base + MPC_I2C_DR);
251 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
253 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
256 writeccr(i2c, CCR_MEN);
260 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
261 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
262 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
263 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
264 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
265 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
266 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
267 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
268 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
269 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
270 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
271 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
272 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
273 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
274 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
275 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
276 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
277 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
278 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
279 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
282 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
283 int prescaler, u32 *real_clk)
285 const struct mpc_i2c_divider *div = NULL;
286 unsigned int pvr = mfspr(SPRN_PVR);
290 if (clock == MPC_I2C_CLOCK_LEGACY) {
291 /* see below - default fdr = 0x3f -> div = 2048 */
292 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
296 /* Determine divider value */
297 divider = mpc5xxx_get_bus_frequency(node) / clock;
300 * We want to choose an FDR/DFSR that generates an I2C bus speed that
301 * is equal to or lower than the requested speed.
303 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
304 div = &mpc_i2c_dividers_52xx[i];
305 /* Old MPC5200 rev A CPUs do not support the high bits */
306 if (div->fdr & 0xc0 && pvr == 0x80822011)
308 if (div->divider >= divider)
312 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
313 return (int)div->fdr;
316 static void mpc_i2c_setup_52xx(struct device_node *node,
318 u32 clock, u32 prescaler)
322 if (clock == MPC_I2C_CLOCK_PRESERVE) {
323 dev_dbg(i2c->dev, "using fdr %d\n",
324 readb(i2c->base + MPC_I2C_FDR));
328 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
329 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
331 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
334 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
337 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
338 static void mpc_i2c_setup_52xx(struct device_node *node,
340 u32 clock, u32 prescaler)
343 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
345 #ifdef CONFIG_PPC_MPC512x
346 static void mpc_i2c_setup_512x(struct device_node *node,
348 u32 clock, u32 prescaler)
350 struct device_node *node_ctrl;
355 /* Enable I2C interrupts for mpc5121 */
356 node_ctrl = of_find_compatible_node(NULL, NULL,
357 "fsl,mpc5121-i2c-ctrl");
359 ctrl = of_iomap(node_ctrl, 0);
361 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
362 pval = of_get_property(node, "reg", NULL);
363 idx = (*pval & 0xff) / 0x20;
364 setbits32(ctrl, 1 << (24 + idx * 2));
367 of_node_put(node_ctrl);
370 /* The clock setup for the 52xx works also fine for the 512x */
371 mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
373 #else /* CONFIG_PPC_MPC512x */
374 static void mpc_i2c_setup_512x(struct device_node *node,
376 u32 clock, u32 prescaler)
379 #endif /* CONFIG_PPC_MPC512x */
381 #ifdef CONFIG_FSL_SOC
382 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
383 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
384 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
385 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
386 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
387 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
388 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
389 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
390 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
391 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
392 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
393 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
394 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
395 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
396 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
397 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
398 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
399 {49152, 0x011e}, {61440, 0x011f}
402 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
404 struct device_node *node = NULL;
408 node = of_find_node_by_name(NULL, "global-utilities");
410 const u32 *prop = of_get_property(node, "reg", NULL);
413 * Map and check POR Device Status Register 2
414 * (PORDEVSR2) at 0xE0014
416 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
419 "Error: couldn't map PORDEVSR2\n");
421 val = in_be32(reg) & 0x00000080; /* sec-cfg */
430 static u32 mpc_i2c_get_prescaler_8xxx(void)
432 /* mpc83xx and mpc82xx all have prescaler 1 */
436 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
437 || pvr_version_is(PVR_VER_E500MC)
438 || pvr_version_is(PVR_VER_E5500)
439 || pvr_version_is(PVR_VER_E6500)) {
440 unsigned int svr = mfspr(SPRN_SVR);
442 if ((SVR_SOC_VER(svr) == SVR_8540)
443 || (SVR_SOC_VER(svr) == SVR_8541)
444 || (SVR_SOC_VER(svr) == SVR_8560)
445 || (SVR_SOC_VER(svr) == SVR_8555)
446 || (SVR_SOC_VER(svr) == SVR_8610))
447 /* the above 85xx SoCs have prescaler 1 */
450 /* all the other 85xx have prescaler 2 */
457 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
458 u32 prescaler, u32 *real_clk)
460 const struct mpc_i2c_divider *div = NULL;
464 if (clock == MPC_I2C_CLOCK_LEGACY) {
465 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
466 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
470 /* Determine proper divider value */
471 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
472 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
474 prescaler = mpc_i2c_get_prescaler_8xxx();
476 divider = fsl_get_sys_freq() / clock / prescaler;
478 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
479 fsl_get_sys_freq(), clock, divider);
482 * We want to choose an FDR/DFSR that generates an I2C bus speed that
483 * is equal to or lower than the requested speed.
485 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
486 div = &mpc_i2c_dividers_8xxx[i];
487 if (div->divider >= divider)
491 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
492 return div ? (int)div->fdr : -EINVAL;
495 static void mpc_i2c_setup_8xxx(struct device_node *node,
497 u32 clock, u32 prescaler)
501 if (clock == MPC_I2C_CLOCK_PRESERVE) {
502 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
503 readb(i2c->base + MPC_I2C_DFSRR),
504 readb(i2c->base + MPC_I2C_FDR));
508 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
509 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
511 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
512 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
515 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
516 i2c->real_clk, fdr >> 8, fdr & 0xff);
519 #else /* !CONFIG_FSL_SOC */
520 static void mpc_i2c_setup_8xxx(struct device_node *node,
522 u32 clock, u32 prescaler)
525 #endif /* CONFIG_FSL_SOC */
527 static void mpc_i2c_start(struct mpc_i2c *i2c)
529 /* Clear arbitration */
530 writeb(0, i2c->base + MPC_I2C_SR);
532 writeccr(i2c, CCR_MEN);
535 static void mpc_i2c_stop(struct mpc_i2c *i2c)
537 writeccr(i2c, CCR_MEN);
540 static int mpc_write(struct mpc_i2c *i2c, int target,
541 const u8 *data, int length, int restart)
544 unsigned timeout = i2c->adap.timeout;
545 u32 flags = restart ? CCR_RSTA : 0;
547 /* Start as master */
548 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
549 /* Write target byte */
550 writeb((target << 1), i2c->base + MPC_I2C_DR);
552 result = i2c_wait(i2c, timeout, 1);
556 for (i = 0; i < length; i++) {
557 /* Write data byte */
558 writeb(data[i], i2c->base + MPC_I2C_DR);
560 result = i2c_wait(i2c, timeout, 1);
568 static int mpc_read(struct mpc_i2c *i2c, int target,
569 u8 *data, int length, int restart, bool recv_len)
571 unsigned timeout = i2c->adap.timeout;
573 u32 flags = restart ? CCR_RSTA : 0;
575 /* Switch to read - restart */
576 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
577 /* Write target address byte - this time with the read flag set */
578 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
580 result = i2c_wait(i2c, timeout, 1);
585 if (length == 1 && !recv_len)
586 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
588 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
590 readb(i2c->base + MPC_I2C_DR);
593 for (i = 0; i < length; i++) {
596 result = i2c_wait(i2c, timeout, 0);
601 * For block reads, we have to know the total length (1st byte)
602 * before we can determine if we are done.
604 if (i || !recv_len) {
605 /* Generate txack on next to last byte */
607 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
609 /* Do not generate stop on last byte */
611 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
615 byte = readb(i2c->base + MPC_I2C_DR);
618 * Adjust length if first received byte is length.
619 * The length is 1 length byte plus actually data length
621 if (i == 0 && recv_len) {
622 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
626 * For block reads, generate txack here if data length
627 * is 1 byte (total length is 2 bytes).
630 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
639 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
641 struct i2c_msg *pmsg;
644 unsigned long orig_jiffies = jiffies;
645 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
649 /* Allow bus up to 1s to become not busy */
650 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
651 if (signal_pending(current)) {
652 dev_dbg(i2c->dev, "Interrupted\n");
656 if (time_after(jiffies, orig_jiffies + HZ)) {
657 u8 status = readb(i2c->base + MPC_I2C_SR);
659 dev_dbg(i2c->dev, "timeout\n");
660 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
661 writeb(status & ~CSR_MAL,
662 i2c->base + MPC_I2C_SR);
663 i2c_recover_bus(&i2c->adap);
670 for (i = 0; ret >= 0 && i < num; i++) {
673 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
674 pmsg->flags & I2C_M_RD ? "read" : "write",
675 pmsg->len, pmsg->addr, i + 1, num);
676 if (pmsg->flags & I2C_M_RD) {
677 bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
679 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
681 if (recv_len && ret > 0)
685 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
688 mpc_i2c_stop(i2c); /* Initiate STOP */
689 orig_jiffies = jiffies;
690 /* Wait until STOP is seen, allow up to 1 s */
691 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
692 if (time_after(jiffies, orig_jiffies + HZ)) {
693 u8 status = readb(i2c->base + MPC_I2C_SR);
695 dev_dbg(i2c->dev, "timeout\n");
696 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
697 writeb(status & ~CSR_MAL,
698 i2c->base + MPC_I2C_SR);
699 i2c_recover_bus(&i2c->adap);
705 return (ret < 0) ? ret : num;
708 static u32 mpc_functionality(struct i2c_adapter *adap)
710 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
711 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
714 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
716 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
718 if (i2c->has_errata_A004447)
719 mpc_i2c_fixup_A004447(i2c);
726 static const struct i2c_algorithm mpc_algo = {
727 .master_xfer = mpc_xfer,
728 .functionality = mpc_functionality,
731 static struct i2c_adapter mpc_ops = {
732 .owner = THIS_MODULE,
737 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
738 .recover_bus = fsl_i2c_bus_recovery,
741 static const struct of_device_id mpc_i2c_of_match[];
742 static int fsl_i2c_probe(struct platform_device *op)
744 const struct of_device_id *match;
747 u32 clock = MPC_I2C_CLOCK_LEGACY;
754 match = of_match_device(mpc_i2c_of_match, &op->dev);
758 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
762 i2c->dev = &op->dev; /* for debug and error output */
764 init_waitqueue_head(&i2c->queue);
766 i2c->base = of_iomap(op->dev.of_node, 0);
768 dev_err(i2c->dev, "failed to map controller\n");
773 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
774 if (i2c->irq) { /* no i2c->irq implies polling */
775 result = request_irq(i2c->irq, mpc_i2c_isr,
776 IRQF_SHARED, "i2c-mpc", i2c);
778 dev_err(i2c->dev, "failed to attach interrupt\n");
784 * enable clock for the I2C peripheral (non fatal),
785 * keep a reference upon successful allocation
787 clk = devm_clk_get(&op->dev, NULL);
789 err = clk_prepare_enable(clk);
791 dev_err(&op->dev, "failed to enable clock\n");
798 if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
799 clock = MPC_I2C_CLOCK_PRESERVE;
801 prop = of_get_property(op->dev.of_node, "clock-frequency",
803 if (prop && plen == sizeof(u32))
808 const struct mpc_i2c_data *data = match->data;
809 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
811 /* Backwards compatibility */
812 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
813 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
816 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
817 if (prop && plen == sizeof(u32)) {
818 mpc_ops.timeout = *prop * HZ / 1000000;
819 if (mpc_ops.timeout < 5)
822 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
824 platform_set_drvdata(op, i2c);
825 if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
826 i2c->has_errata_A004447 = true;
829 of_address_to_resource(op->dev.of_node, 0, &res);
830 scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
831 "MPC adapter at 0x%llx", (unsigned long long)res.start);
832 i2c_set_adapdata(&i2c->adap, i2c);
833 i2c->adap.dev.parent = &op->dev;
834 i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
835 i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
837 result = i2c_add_adapter(&i2c->adap);
845 clk_disable_unprepare(i2c->clk_per);
846 free_irq(i2c->irq, i2c);
848 irq_dispose_mapping(i2c->irq);
855 static int fsl_i2c_remove(struct platform_device *op)
857 struct mpc_i2c *i2c = platform_get_drvdata(op);
859 i2c_del_adapter(&i2c->adap);
862 clk_disable_unprepare(i2c->clk_per);
865 free_irq(i2c->irq, i2c);
867 irq_dispose_mapping(i2c->irq);
873 #ifdef CONFIG_PM_SLEEP
874 static int mpc_i2c_suspend(struct device *dev)
876 struct mpc_i2c *i2c = dev_get_drvdata(dev);
878 i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
879 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
884 static int mpc_i2c_resume(struct device *dev)
886 struct mpc_i2c *i2c = dev_get_drvdata(dev);
888 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
889 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
894 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
895 #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
897 #define MPC_I2C_PM_OPS NULL
900 static const struct mpc_i2c_data mpc_i2c_data_512x = {
901 .setup = mpc_i2c_setup_512x,
904 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
905 .setup = mpc_i2c_setup_52xx,
908 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
909 .setup = mpc_i2c_setup_8xxx,
912 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
913 .setup = mpc_i2c_setup_8xxx,
917 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
918 .setup = mpc_i2c_setup_8xxx,
922 static const struct of_device_id mpc_i2c_of_match[] = {
923 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
924 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
925 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
926 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
927 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
928 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
929 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
930 /* Backward compatibility */
931 {.compatible = "fsl-i2c", },
934 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
936 /* Structure for a device driver */
937 static struct platform_driver mpc_i2c_driver = {
938 .probe = fsl_i2c_probe,
939 .remove = fsl_i2c_remove,
942 .of_match_table = mpc_i2c_of_match,
943 .pm = MPC_I2C_PM_OPS,
947 module_platform_driver(mpc_i2c_driver);
949 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
950 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
951 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
952 MODULE_LICENSE("GPL");