drivers/i2c/busses/i2c-mpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This is a combined i2c adapter and algorithm driver for the
   4  * MPC107/Tsi107 PowerPC northbridge and processors that include
   5  * the same I2C unit (8240, 8245, 85xx).
   6  *
   7  * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
   8  * Copyright (C) 2021 Allied Telesis Labs
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/sched/signal.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/property.h>
  19 #include <linux/slab.h>
  20
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/fsl_devices.h>
  25 #include <linux/i2c.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/delay.h>
  28
  29 #include <asm/mpc52xx.h>
  30 #include <asm/mpc85xx.h>
  31 #include <sysdev/fsl_soc.h>
  32
  33 #define MPC_I2C_CLOCK_LEGACY   0
  34 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  35
  36 #define MPC_I2C_FDR   0x04
  37 #define MPC_I2C_CR    0x08
  38 #define MPC_I2C_SR    0x0c
  39 #define MPC_I2C_DR    0x10
  40 #define MPC_I2C_DFSRR 0x14
  41
  42 #define CCR_MEN  0x80
  43 #define CCR_MIEN 0x40
  44 #define CCR_MSTA 0x20
  45 #define CCR_MTX  0x10
  46 #define CCR_TXAK 0x08
  47 #define CCR_RSTA 0x04
  48 #define CCR_RSVD 0x02
  49
  50 #define CSR_MCF  0x80
  51 #define CSR_MAAS 0x40
  52 #define CSR_MBB  0x20
  53 #define CSR_MAL  0x10
  54 #define CSR_SRW  0x04
  55 #define CSR_MIF  0x02
  56 #define CSR_RXAK 0x01
  57
  58 enum mpc_i2c_action {
  59         MPC_I2C_ACTION_START = 1,
  60         MPC_I2C_ACTION_RESTART,
  61         MPC_I2C_ACTION_READ_BEGIN,
  62         MPC_I2C_ACTION_READ_BYTE,
  63         MPC_I2C_ACTION_WRITE,
  64         MPC_I2C_ACTION_STOP,
  65
  66         __MPC_I2C_ACTION_CNT
  67 };
  68
  69 static const char * const action_str[] = {
  70         "invalid",
  71         "start",
  72         "restart",
  73         "read begin",
  74         "read",
  75         "write",
  76         "stop",
  77 };
  78
  79 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
  80
  81 struct mpc_i2c {
  82         struct device *dev;
  83         void __iomem *base;
  84         u32 interrupt;
  85         wait_queue_head_t waitq;
  86         spinlock_t lock;
  87         struct i2c_adapter adap;
  88         int irq;
  89         u32 real_clk;
  90         u8 fdr, dfsrr;
  91         struct clk *clk_per;
  92         u32 cntl_bits;
  93         enum mpc_i2c_action action;
  94         struct i2c_msg *msgs;
  95         int num_msgs;
  96         int curr_msg;
  97         u32 byte_posn;
  98         u32 block;
  99         int rc;
 100         int expect_rxack;
 101         bool has_errata_A004447;
 102 };
 103
 104 struct mpc_i2c_divider {
 105         u16 divider;
 106         u16 fdr;        /* including dfsrr */
 107 };
 108
 109 struct mpc_i2c_data {
 110         void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
 111 };
 112
 113 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
 114 {
 115         writeb(x, i2c->base + MPC_I2C_CR);
 116 }
 117
 118 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
 119  * the bus, because it wants to send ACK.
 120  * Following sequence of enabling/disabling and sending start/stop generates
 121  * the 9 pulses, each with a START then ending with STOP, so it's all OK.
 122  */
 123 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 124 {
 125         int k;
 126         unsigned long flags;
 127
 128         for (k = 9; k; k--) {
 129                 writeccr(i2c, 0);
 130                 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
 131                 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
 132                 readb(i2c->base + MPC_I2C_DR); /* init xfer */
 133                 udelay(15); /* let it hit the bus */
 134                 local_irq_save(flags); /* should not be delayed further */
 135                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
 136                 readb(i2c->base + MPC_I2C_DR);
 137                 if (k != 1)
 138                         udelay(5);
 139                 local_irq_restore(flags);
 140         }
 141         writeccr(i2c, CCR_MEN); /* Initiate STOP */
 142         readb(i2c->base + MPC_I2C_DR);
 143         udelay(15); /* Let STOP propagate */
 144         writeccr(i2c, 0);
 145 }
 146
 147 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
 148 {
 149         void __iomem *addr = i2c->base + MPC_I2C_SR;
 150         u8 val;
 151
 152         return readb_poll_timeout(addr, val, val & mask, 0, 100);
 153 }
 154
 155 /*
 156  * Workaround for Erratum A004447. From the P2040CE Rev Q
 157  *
 158  * 1.  Set up the frequency divider and sampling rate.
 159  * 2.  I2CCR - a0h
 160  * 3.  Poll for I2CSR[MBB] to get set.
 161  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
 162  *     step 5. If MAL is not set, then go to step 13.
 163  * 5.  I2CCR - 00h
 164  * 6.  I2CCR - 22h
 165  * 7.  I2CCR - a2h
 166  * 8.  Poll for I2CSR[MBB] to get set.
 167  * 9.  Issue read to I2CDR.
 168  * 10. Poll for I2CSR[MIF] to be set.
 169  * 11. I2CCR - 82h
 170  * 12. Workaround complete. Skip the next steps.
 171  * 13. Issue read to I2CDR.
 172  * 14. Poll for I2CSR[MIF] to be set.
 173  * 15. I2CCR - 80h
 174  */
 175 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
 176 {
 177         int ret;
 178         u32 val;
 179
 180         writeccr(i2c, CCR_MEN | CCR_MSTA);
 181         ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 182         if (ret) {
 183                 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 184                 return;
 185         }
 186
 187         val = readb(i2c->base + MPC_I2C_SR);
 188
 189         if (val & CSR_MAL) {
 190                 writeccr(i2c, 0x00);
 191                 writeccr(i2c, CCR_MSTA | CCR_RSVD);
 192                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
 193                 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 194                 if (ret) {
 195                         dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 196                         return;
 197                 }
 198                 val = readb(i2c->base + MPC_I2C_DR);
 199                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 200                 if (ret) {
 201                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 202                         return;
 203                 }
 204                 writeccr(i2c, CCR_MEN | CCR_RSVD);
 205         } else {
 206                 val = readb(i2c->base + MPC_I2C_DR);
 207                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 208                 if (ret) {
 209                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 210                         return;
 211                 }
 212                 writeccr(i2c, CCR_MEN);
 213         }
 214 }
 215
 216 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 217 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
 218         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 219         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 220         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 221         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 222         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 223         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 224         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 225         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 226         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 227         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 228         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 229         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 230         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 231         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 232         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 233         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 234         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 235         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 236 };
 237
 238 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 239                                           u32 *real_clk)
 240 {
 241         struct fwnode_handle *fwnode = of_fwnode_handle(node);
 242         const struct mpc_i2c_divider *div = NULL;
 243         unsigned int pvr = mfspr(SPRN_PVR);
 244         u32 divider;
 245         int i;
 246
 247         if (clock == MPC_I2C_CLOCK_LEGACY) {
 248                 /* see below - default fdr = 0x3f -> div = 2048 */
 249                 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / 2048;
 250                 return -EINVAL;
 251         }
 252
 253         /* Determine divider value */
 254         divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
 255
 256         /*
 257          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 258          * is equal to or lower than the requested speed.
 259          */
 260         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 261                 div = &mpc_i2c_dividers_52xx[i];
 262                 /* Old MPC5200 rev A CPUs do not support the high bits */
 263                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 264                         continue;
 265                 if (div->divider >= divider)
 266                         break;
 267         }
 268
 269         *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
 270         return (int)div->fdr;
 271 }
 272
 273 static void mpc_i2c_setup_52xx(struct device_node *node,
 274                                          struct mpc_i2c *i2c,
 275                                          u32 clock)
 276 {
 277         int ret, fdr;
 278
 279         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 280                 dev_dbg(i2c->dev, "using fdr %d\n",
 281                         readb(i2c->base + MPC_I2C_FDR));
 282                 return;
 283         }
 284
 285         ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
 286         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 287
 288         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 289
 290         if (ret >= 0)
 291                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
 292                          fdr);
 293 }
 294 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 295 static void mpc_i2c_setup_52xx(struct device_node *node,
 296                                          struct mpc_i2c *i2c,
 297                                          u32 clock)
 298 {
 299 }
 300 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 301
 302 #ifdef CONFIG_PPC_MPC512x
 303 static void mpc_i2c_setup_512x(struct device_node *node,
 304                                          struct mpc_i2c *i2c,
 305                                          u32 clock)
 306 {
 307         struct device_node *node_ctrl;
 308         void __iomem *ctrl;
 309         u32 idx;
 310
 311         /* Enable I2C interrupts for mpc5121 */
 312         node_ctrl = of_find_compatible_node(NULL, NULL,
 313                                             "fsl,mpc5121-i2c-ctrl");
 314         if (node_ctrl) {
 315                 ctrl = of_iomap(node_ctrl, 0);
 316                 if (ctrl) {
 317                         u64 addr;
 318                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 319                         of_property_read_reg(node, 0, &addr, NULL);
 320                         idx = (addr & 0xff) / 0x20;
 321                         setbits32(ctrl, 1 << (24 + idx * 2));
 322                         iounmap(ctrl);
 323                 }
 324                 of_node_put(node_ctrl);
 325         }
 326
 327         /* The clock setup for the 52xx works also fine for the 512x */
 328         mpc_i2c_setup_52xx(node, i2c, clock);
 329 }
 330 #else /* CONFIG_PPC_MPC512x */
 331 static void mpc_i2c_setup_512x(struct device_node *node,
 332                                          struct mpc_i2c *i2c,
 333                                          u32 clock)
 334 {
 335 }
 336 #endif /* CONFIG_PPC_MPC512x */
 337
 338 #ifdef CONFIG_FSL_SOC
 339 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
 340         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 341         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 342         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 343         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 344         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 345         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 346         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 347         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 348         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 349         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 350         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 351         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 352         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 353         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 354         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 355         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 356         {49152, 0x011e}, {61440, 0x011f}
 357 };
 358
 359 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
 360 {
 361         struct device_node *node;
 362         u32 __iomem *reg;
 363         u32 val = 0;
 364
 365         node = of_find_node_by_name(NULL, "global-utilities");
 366         if (node) {
 367                 const u32 *prop = of_get_property(node, "reg", NULL);
 368                 if (prop) {
 369                         /*
 370                          * Map and check POR Device Status Register 2
 371                          * (PORDEVSR2) at 0xE0014. Note than while MPC8533
 372                          * and MPC8544 indicate SEC frequency ratio
 373                          * configuration as bit 26 in PORDEVSR2, other MPC8xxx
 374                          * parts may store it differently or may not have it
 375                          * at all.
 376                          */
 377                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 378                         if (!reg)
 379                                 printk(KERN_ERR
 380                                        "Error: couldn't map PORDEVSR2\n");
 381                         else
 382                                 val = in_be32(reg) & 0x00000020; /* sec-cfg */
 383                         iounmap(reg);
 384                 }
 385         }
 386         of_node_put(node);
 387
 388         return val;
 389 }
 390
 391 static u32 mpc_i2c_get_prescaler_8xxx(void)
 392 {
 393         /*
 394          * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
 395          * may have prescaler 1, 2, or 3, depending on the power-on
 396          * configuration.
 397          */
 398         u32 prescaler = 1;
 399
 400         /* mpc85xx */
 401         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
 402                 || pvr_version_is(PVR_VER_E500MC)
 403                 || pvr_version_is(PVR_VER_E5500)
 404                 || pvr_version_is(PVR_VER_E6500)) {
 405                 unsigned int svr = mfspr(SPRN_SVR);
 406
 407                 if ((SVR_SOC_VER(svr) == SVR_8540)
 408                         || (SVR_SOC_VER(svr) == SVR_8541)
 409                         || (SVR_SOC_VER(svr) == SVR_8560)
 410                         || (SVR_SOC_VER(svr) == SVR_8555)
 411                         || (SVR_SOC_VER(svr) == SVR_8610))
 412                         /* the above 85xx SoCs have prescaler 1 */
 413                         prescaler = 1;
 414                 else if ((SVR_SOC_VER(svr) == SVR_8533)
 415                         || (SVR_SOC_VER(svr) == SVR_8544))
 416                         /* the above 85xx SoCs have prescaler 3 or 2 */
 417                         prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 418                 else
 419                         /* all the other 85xx have prescaler 2 */
 420                         prescaler = 2;
 421         }
 422
 423         return prescaler;
 424 }
 425
 426 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 427                                           u32 *real_clk)
 428 {
 429         const struct mpc_i2c_divider *div = NULL;
 430         u32 prescaler = mpc_i2c_get_prescaler_8xxx();
 431         u32 divider;
 432         int i;
 433
 434         if (clock == MPC_I2C_CLOCK_LEGACY) {
 435                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
 436                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
 437                 return -EINVAL;
 438         }
 439
 440         divider = fsl_get_sys_freq() / clock / prescaler;
 441
 442         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 443                  fsl_get_sys_freq(), clock, divider);
 444
 445         /*
 446          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 447          * is equal to or lower than the requested speed.
 448          */
 449         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 450                 div = &mpc_i2c_dividers_8xxx[i];
 451                 if (div->divider >= divider)
 452                         break;
 453         }
 454
 455         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
 456         return (int)div->fdr;
 457 }
 458
 459 static void mpc_i2c_setup_8xxx(struct device_node *node,
 460                                          struct mpc_i2c *i2c,
 461                                          u32 clock)
 462 {
 463         int ret, fdr;
 464
 465         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 466                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 467                         readb(i2c->base + MPC_I2C_DFSRR),
 468                         readb(i2c->base + MPC_I2C_FDR));
 469                 return;
 470         }
 471
 472         ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
 473         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 474
 475         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 476         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 477
 478         if (ret >= 0)
 479                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 480                          i2c->real_clk, fdr >> 8, fdr & 0xff);
 481 }
 482
 483 #else /* !CONFIG_FSL_SOC */
 484 static void mpc_i2c_setup_8xxx(struct device_node *node,
 485                                          struct mpc_i2c *i2c,
 486                                          u32 clock)
 487 {
 488 }
 489 #endif /* CONFIG_FSL_SOC */
 490
 491 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
 492 {
 493         i2c->rc = rc;
 494         i2c->block = 0;
 495         i2c->cntl_bits = CCR_MEN;
 496         writeccr(i2c, i2c->cntl_bits);
 497         wake_up(&i2c->waitq);
 498 }
 499
 500 static void mpc_i2c_do_action(struct mpc_i2c *i2c)
 501 {
 502         struct i2c_msg *msg = NULL;
 503         int dir = 0;
 504         int recv_len = 0;
 505         u8 byte;
 506
 507         dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
 508
 509         i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
 510
 511         if (i2c->action != MPC_I2C_ACTION_STOP) {
 512                 msg = &i2c->msgs[i2c->curr_msg];
 513                 if (msg->flags & I2C_M_RD)
 514                         dir = 1;
 515                 if (msg->flags & I2C_M_RECV_LEN)
 516                         recv_len = 1;
 517         }
 518
 519         switch (i2c->action) {
 520         case MPC_I2C_ACTION_RESTART:
 521                 i2c->cntl_bits |= CCR_RSTA;
 522                 fallthrough;
 523
 524         case MPC_I2C_ACTION_START:
 525                 i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
 526                 writeccr(i2c, i2c->cntl_bits);
 527                 writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
 528                 i2c->expect_rxack = 1;
 529                 i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
 530                 break;
 531
 532         case MPC_I2C_ACTION_READ_BEGIN:
 533                 if (msg->len) {
 534                         if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
 535                                 i2c->cntl_bits |= CCR_TXAK;
 536
 537                         writeccr(i2c, i2c->cntl_bits);
 538                         /* Dummy read */
 539                         readb(i2c->base + MPC_I2C_DR);
 540                 }
 541                 i2c->action = MPC_I2C_ACTION_READ_BYTE;
 542                 break;
 543
 544         case MPC_I2C_ACTION_READ_BYTE:
 545                 if (i2c->byte_posn || !recv_len) {
 546                         /* Generate Tx ACK on next to last byte */
 547                         if (i2c->byte_posn == msg->len - 2)
 548                                 i2c->cntl_bits |= CCR_TXAK;
 549                         /* Do not generate stop on last byte */
 550                         if (i2c->byte_posn == msg->len - 1)
 551                                 i2c->cntl_bits |= CCR_MTX;
 552
 553                         writeccr(i2c, i2c->cntl_bits);
 554                 }
 555
 556                 byte = readb(i2c->base + MPC_I2C_DR);
 557
 558                 if (i2c->byte_posn == 0 && recv_len) {
 559                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
 560                                 mpc_i2c_finish(i2c, -EPROTO);
 561                                 return;
 562                         }
 563                         msg->len += byte;
 564                         /*
 565                          * For block reads, generate Tx ACK here if data length
 566                          * is 1 byte (total length is 2 bytes).
 567                          */
 568                         if (msg->len == 2) {
 569                                 i2c->cntl_bits |= CCR_TXAK;
 570                                 writeccr(i2c, i2c->cntl_bits);
 571                         }
 572                 }
 573
 574                 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
 575                 msg->buf[i2c->byte_posn++] = byte;
 576                 break;
 577
 578         case MPC_I2C_ACTION_WRITE:
 579                 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
 580                         msg->buf[i2c->byte_posn]);
 581                 writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
 582                 i2c->expect_rxack = 1;
 583                 break;
 584
 585         case MPC_I2C_ACTION_STOP:
 586                 mpc_i2c_finish(i2c, 0);
 587                 break;
 588
 589         default:
 590                 WARN(1, "Unexpected action %d\n", i2c->action);
 591                 break;
 592         }
 593
 594         if (msg && msg->len == i2c->byte_posn) {
 595                 i2c->curr_msg++;
 596                 i2c->byte_posn = 0;
 597
 598                 if (i2c->curr_msg == i2c->num_msgs) {
 599                         i2c->action = MPC_I2C_ACTION_STOP;
 600                         /*
 601                          * We don't get another interrupt on read so
 602                          * finish the transfer now
 603                          */
 604                         if (dir)
 605                                 mpc_i2c_finish(i2c, 0);
 606                 } else {
 607                         i2c->action = MPC_I2C_ACTION_RESTART;
 608                 }
 609         }
 610 }
 611
 612 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
 613 {
 614         spin_lock(&i2c->lock);
 615
 616         if (!(status & CSR_MCF)) {
 617                 dev_dbg(i2c->dev, "unfinished\n");
 618                 mpc_i2c_finish(i2c, -EIO);
 619                 goto out;
 620         }
 621
 622         if (status & CSR_MAL) {
 623                 dev_dbg(i2c->dev, "arbitration lost\n");
 624                 mpc_i2c_finish(i2c, -EAGAIN);
 625                 goto out;
 626         }
 627
 628         if (i2c->expect_rxack && (status & CSR_RXAK)) {
 629                 dev_dbg(i2c->dev, "no Rx ACK\n");
 630                 mpc_i2c_finish(i2c, -ENXIO);
 631                 goto out;
 632         }
 633         i2c->expect_rxack = 0;
 634
 635         mpc_i2c_do_action(i2c);
 636
 637 out:
 638         spin_unlock(&i2c->lock);
 639 }
 640
 641 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
 642 {
 643         struct mpc_i2c *i2c = dev_id;
 644         u8 status;
 645
 646         status = readb(i2c->base + MPC_I2C_SR);
 647         if (status & CSR_MIF) {
 648                 /* Wait up to 100us for transfer to properly complete */
 649                 readb_poll_timeout_atomic(i2c->base + MPC_I2C_SR, status, status & CSR_MCF, 0, 100);
 650                 writeb(0, i2c->base + MPC_I2C_SR);
 651                 mpc_i2c_do_intr(i2c, status);
 652                 return IRQ_HANDLED;
 653         }
 654         return IRQ_NONE;
 655 }
 656
 657 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
 658 {
 659         long time_left;
 660
 661         time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
 662         if (!time_left)
 663                 return -ETIMEDOUT;
 664         if (time_left < 0)
 665                 return time_left;
 666
 667         return 0;
 668 }
 669
 670 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
 671 {
 672         unsigned long orig_jiffies;
 673         unsigned long flags;
 674         int ret;
 675
 676         spin_lock_irqsave(&i2c->lock, flags);
 677
 678         i2c->curr_msg = 0;
 679         i2c->rc = 0;
 680         i2c->byte_posn = 0;
 681         i2c->block = 1;
 682         i2c->action = MPC_I2C_ACTION_START;
 683
 684         i2c->cntl_bits = CCR_MEN | CCR_MIEN;
 685         writeb(0, i2c->base + MPC_I2C_SR);
 686         writeccr(i2c, i2c->cntl_bits);
 687
 688         mpc_i2c_do_action(i2c);
 689
 690         spin_unlock_irqrestore(&i2c->lock, flags);
 691
 692         ret = mpc_i2c_wait_for_completion(i2c);
 693         if (ret)
 694                 i2c->rc = ret;
 695
 696         if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
 697                 i2c_recover_bus(&i2c->adap);
 698
 699         orig_jiffies = jiffies;
 700         /* Wait until STOP is seen, allow up to 1 s */
 701         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 702                 if (time_after(jiffies, orig_jiffies + HZ)) {
 703                         u8 status = readb(i2c->base + MPC_I2C_SR);
 704
 705                         dev_dbg(i2c->dev, "timeout\n");
 706                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 707                                 writeb(status & ~CSR_MAL,
 708                                        i2c->base + MPC_I2C_SR);
 709                                 i2c_recover_bus(&i2c->adap);
 710                         }
 711                         return -EIO;
 712                 }
 713                 cond_resched();
 714         }
 715
 716         return i2c->rc;
 717 }
 718
 719 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 720 {
 721         int rc, ret = num;
 722         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 723         int i;
 724
 725         dev_dbg(i2c->dev, "num = %d\n", num);
 726         for (i = 0; i < num; i++)
 727                 dev_dbg(i2c->dev, "  addr = %02x, flags = %02x, len = %d, %*ph\n",
 728                         msgs[i].addr, msgs[i].flags, msgs[i].len,
 729                         msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
 730                         msgs[i].buf);
 731
 732         WARN_ON(i2c->msgs != NULL);
 733         i2c->msgs = msgs;
 734         i2c->num_msgs = num;
 735
 736         rc = mpc_i2c_execute_msg(i2c);
 737         if (rc < 0)
 738                 ret = rc;
 739
 740         i2c->num_msgs = 0;
 741         i2c->msgs = NULL;
 742
 743         return ret;
 744 }
 745
 746 static u32 mpc_functionality(struct i2c_adapter *adap)
 747 {
 748         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 749           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
 750 }
 751
 752 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
 753 {
 754         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 755
 756         if (i2c->has_errata_A004447)
 757                 mpc_i2c_fixup_A004447(i2c);
 758         else
 759                 mpc_i2c_fixup(i2c);
 760
 761         return 0;
 762 }
 763
 764 static const struct i2c_algorithm mpc_algo = {
 765         .master_xfer = mpc_xfer,
 766         .functionality = mpc_functionality,
 767 };
 768
 769 static struct i2c_adapter mpc_ops = {
 770         .owner = THIS_MODULE,
 771         .algo = &mpc_algo,
 772 };
 773
 774 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
 775         .recover_bus = fsl_i2c_bus_recovery,
 776 };
 777
 778 static int fsl_i2c_probe(struct platform_device *op)
 779 {
 780         const struct mpc_i2c_data *data;
 781         struct mpc_i2c *i2c;
 782         struct clk *clk;
 783         int result;
 784         u32 clock;
 785         int err;
 786
 787         i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL);
 788         if (!i2c)
 789                 return -ENOMEM;
 790
 791         i2c->dev = &op->dev; /* for debug and error output */
 792
 793         init_waitqueue_head(&i2c->waitq);
 794         spin_lock_init(&i2c->lock);
 795
 796         i2c->base = devm_platform_ioremap_resource(op, 0);
 797         if (IS_ERR(i2c->base))
 798                 return PTR_ERR(i2c->base);
 799
 800         i2c->irq = platform_get_irq(op, 0);
 801         if (i2c->irq < 0)
 802                 return i2c->irq;
 803
 804         result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr,
 805                         IRQF_SHARED, "i2c-mpc", i2c);
 806         if (result < 0) {
 807                 dev_err(i2c->dev, "failed to attach interrupt\n");
 808                 return result;
 809         }
 810
 811         /*
 812          * enable clock for the I2C peripheral (non fatal),
 813          * keep a reference upon successful allocation
 814          */
 815         clk = devm_clk_get_optional(&op->dev, NULL);
 816         if (IS_ERR(clk))
 817                 return PTR_ERR(clk);
 818
 819         err = clk_prepare_enable(clk);
 820         if (err) {
 821                 dev_err(&op->dev, "failed to enable clock\n");
 822                 return err;
 823         }
 824
 825         i2c->clk_per = clk;
 826
 827         if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
 828                 clock = MPC_I2C_CLOCK_PRESERVE;
 829         } else {
 830                 result = of_property_read_u32(op->dev.of_node,
 831                                               "clock-frequency", &clock);
 832                 if (result)
 833                         clock = MPC_I2C_CLOCK_LEGACY;
 834         }
 835
 836         data = device_get_match_data(&op->dev);
 837         if (data) {
 838                 data->setup(op->dev.of_node, i2c, clock);
 839         } else {
 840                 /* Backwards compatibility */
 841                 if (of_property_read_bool(op->dev.of_node, "dfsrr"))
 842                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
 843         }
 844
 845         /* Sadly, we have to support two deprecated bindings here */
 846         result = of_property_read_u32(op->dev.of_node,
 847                                       "i2c-transfer-timeout-us",
 848                                       &mpc_ops.timeout);
 849         if (result == -EINVAL)
 850                 result = of_property_read_u32(op->dev.of_node,
 851                                               "i2c-scl-clk-low-timeout-us",
 852                                               &mpc_ops.timeout);
 853         if (result == -EINVAL)
 854                 result = of_property_read_u32(op->dev.of_node,
 855                                               "fsl,timeout", &mpc_ops.timeout);
 856
 857         if (!result) {
 858                 mpc_ops.timeout *= HZ / 1000000;
 859                 if (mpc_ops.timeout < 5)
 860                         mpc_ops.timeout = 5;
 861         } else {
 862                 mpc_ops.timeout = HZ;
 863         }
 864
 865         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
 866
 867         if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
 868                 i2c->has_errata_A004447 = true;
 869
 870         i2c->adap = mpc_ops;
 871         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
 872                   "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
 873         i2c->adap.dev.parent = &op->dev;
 874         i2c->adap.nr = op->id;
 875         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
 876         i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
 877         platform_set_drvdata(op, i2c);
 878         i2c_set_adapdata(&i2c->adap, i2c);
 879
 880         result = i2c_add_numbered_adapter(&i2c->adap);
 881         if (result)
 882                 goto fail_add;
 883
 884         return 0;
 885
 886  fail_add:
 887         clk_disable_unprepare(i2c->clk_per);
 888
 889         return result;
 890 };
 891
 892 static void fsl_i2c_remove(struct platform_device *op)
 893 {
 894         struct mpc_i2c *i2c = platform_get_drvdata(op);
 895
 896         i2c_del_adapter(&i2c->adap);
 897
 898         clk_disable_unprepare(i2c->clk_per);
 899 };
 900
 901 static int __maybe_unused mpc_i2c_suspend(struct device *dev)
 902 {
 903         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 904
 905         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
 906         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
 907
 908         return 0;
 909 }
 910
 911 static int __maybe_unused mpc_i2c_resume(struct device *dev)
 912 {
 913         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 914
 915         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
 916         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
 917
 918         return 0;
 919 }
 920 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
 921
 922 static const struct mpc_i2c_data mpc_i2c_data_512x = {
 923         .setup = mpc_i2c_setup_512x,
 924 };
 925
 926 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
 927         .setup = mpc_i2c_setup_52xx,
 928 };
 929
 930 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
 931         .setup = mpc_i2c_setup_8xxx,
 932 };
 933
 934 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
 935         .setup = mpc_i2c_setup_8xxx,
 936 };
 937
 938 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
 939         .setup = mpc_i2c_setup_8xxx,
 940 };
 941
 942 static const struct of_device_id mpc_i2c_of_match[] = {
 943         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 944         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 945         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 946         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 947         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 948         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 949         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 950         /* Backward compatibility */
 951         {.compatible = "fsl-i2c", },
 952         {},
 953 };
 954 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 955
 956 /* Structure for a device driver */
 957 static struct platform_driver mpc_i2c_driver = {
 958         .probe          = fsl_i2c_probe,
 959         .remove_new     = fsl_i2c_remove,
 960         .driver = {
 961                 .name = "mpc-i2c",
 962                 .of_match_table = mpc_i2c_of_match,
 963                 .pm = &mpc_i2c_pm_ops,
 964         },
 965 };
 966
 967 module_platform_driver(mpc_i2c_driver);
 968
 969 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 970 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 971                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 972 MODULE_LICENSE("GPL");