drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.8
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/iopoll.h>
  27 #include <linux/fsl_devices.h>
  28 #include <linux/i2c.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/mpc52xx.h>
  33 #include <asm/mpc85xx.h>
  34 #include <sysdev/fsl_soc.h>
  35
  36 #define DRV_NAME "mpc-i2c"
  37
  38 #define MPC_I2C_CLOCK_LEGACY   0
  39 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  40
  41 #define MPC_I2C_FDR   0x04
  42 #define MPC_I2C_CR    0x08
  43 #define MPC_I2C_SR    0x0c
  44 #define MPC_I2C_DR    0x10
  45 #define MPC_I2C_DFSRR 0x14
  46
  47 #define CCR_MEN  0x80
  48 #define CCR_MIEN 0x40
  49 #define CCR_MSTA 0x20
  50 #define CCR_MTX  0x10
  51 #define CCR_TXAK 0x08
  52 #define CCR_RSTA 0x04
  53 #define CCR_RSVD 0x02
  54
  55 #define CSR_MCF  0x80
  56 #define CSR_MAAS 0x40
  57 #define CSR_MBB  0x20
  58 #define CSR_MAL  0x10
  59 #define CSR_SRW  0x04
  60 #define CSR_MIF  0x02
  61 #define CSR_RXAK 0x01
  62
  63 struct mpc_i2c {
  64         struct device *dev;
  65         void __iomem *base;
  66         u32 interrupt;
  67         wait_queue_head_t queue;
  68         struct i2c_adapter adap;
  69         int irq;
  70         u32 real_clk;
  71 #ifdef CONFIG_PM_SLEEP
  72         u8 fdr, dfsrr;
  73 #endif
  74         struct clk *clk_per;
  75         bool has_errata_A004447;
  76 };
  77
  78 struct mpc_i2c_divider {
  79         u16 divider;
  80         u16 fdr;        /* including dfsrr */
  81 };
  82
  83 struct mpc_i2c_data {
  84         void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
  85                       u32 clock, u32 prescaler);
  86         u32 prescaler;
  87 };
  88
  89 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
  90 {
  91         writeb(x, i2c->base + MPC_I2C_CR);
  92 }
  93
  94 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  95 {
  96         struct mpc_i2c *i2c = dev_id;
  97         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  98                 /* Read again to allow register to stabilise */
  99                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
 100                 writeb(0, i2c->base + MPC_I2C_SR);
 101                 wake_up(&i2c->queue);
 102                 return IRQ_HANDLED;
 103         }
 104         return IRQ_NONE;
 105 }
 106
 107 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
 108  * the bus, because it wants to send ACK.
 109  * Following sequence of enabling/disabling and sending start/stop generates
 110  * the 9 pulses, so it's all OK.
 111  */
 112 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 113 {
 114         int k;
 115         u32 delay_val = 1000000 / i2c->real_clk + 1;
 116
 117         if (delay_val < 2)
 118                 delay_val = 2;
 119
 120         for (k = 9; k; k--) {
 121                 writeccr(i2c, 0);
 122                 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
 123                 readb(i2c->base + MPC_I2C_DR);
 124                 writeccr(i2c, CCR_MEN);
 125                 udelay(delay_val << 1);
 126         }
 127 }
 128
 129 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
 130 {
 131         unsigned long orig_jiffies = jiffies;
 132         u32 cmd_err;
 133         int result = 0;
 134
 135         if (!i2c->irq) {
 136                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
 137                         schedule();
 138                         if (time_after(jiffies, orig_jiffies + timeout)) {
 139                                 dev_dbg(i2c->dev, "timeout\n");
 140                                 writeccr(i2c, 0);
 141                                 result = -ETIMEDOUT;
 142                                 break;
 143                         }
 144                 }
 145                 cmd_err = readb(i2c->base + MPC_I2C_SR);
 146                 writeb(0, i2c->base + MPC_I2C_SR);
 147         } else {
 148                 /* Interrupt mode */
 149                 result = wait_event_timeout(i2c->queue,
 150                         (i2c->interrupt & CSR_MIF), timeout);
 151
 152                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
 153                         dev_dbg(i2c->dev, "wait timeout\n");
 154                         writeccr(i2c, 0);
 155                         result = -ETIMEDOUT;
 156                 }
 157
 158                 cmd_err = i2c->interrupt;
 159                 i2c->interrupt = 0;
 160         }
 161
 162         if (result < 0)
 163                 return result;
 164
 165         if (!(cmd_err & CSR_MCF)) {
 166                 dev_dbg(i2c->dev, "unfinished\n");
 167                 return -EIO;
 168         }
 169
 170         if (cmd_err & CSR_MAL) {
 171                 dev_dbg(i2c->dev, "MAL\n");
 172                 return -EAGAIN;
 173         }
 174
 175         if (writing && (cmd_err & CSR_RXAK)) {
 176                 dev_dbg(i2c->dev, "No RXAK\n");
 177                 /* generate stop */
 178                 writeccr(i2c, CCR_MEN);
 179                 return -ENXIO;
 180         }
 181         return 0;
 182 }
 183
 184 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
 185 {
 186         void __iomem *addr = i2c->base + MPC_I2C_SR;
 187         u8 val;
 188
 189         return readb_poll_timeout(addr, val, val & mask, 0, 100);
 190 }
 191
 192 /*
 193  * Workaround for Erratum A004447. From the P2040CE Rev Q
 194  *
 195  * 1.  Set up the frequency divider and sampling rate.
 196  * 2.  I2CCR - a0h
 197  * 3.  Poll for I2CSR[MBB] to get set.
 198  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
 199  *     step 5. If MAL is not set, then go to step 13.
 200  * 5.  I2CCR - 00h
 201  * 6.  I2CCR - 22h
 202  * 7.  I2CCR - a2h
 203  * 8.  Poll for I2CSR[MBB] to get set.
 204  * 9.  Issue read to I2CDR.
 205  * 10. Poll for I2CSR[MIF] to be set.
 206  * 11. I2CCR - 82h
 207  * 12. Workaround complete. Skip the next steps.
 208  * 13. Issue read to I2CDR.
 209  * 14. Poll for I2CSR[MIF] to be set.
 210  * 15. I2CCR - 80h
 211  */
 212 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
 213 {
 214         int ret;
 215         u32 val;
 216
 217         writeccr(i2c, CCR_MEN | CCR_MSTA);
 218         ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 219         if (ret) {
 220                 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 221                 return;
 222         }
 223
 224         val = readb(i2c->base + MPC_I2C_SR);
 225
 226         if (val & CSR_MAL) {
 227                 writeccr(i2c, 0x00);
 228                 writeccr(i2c, CCR_MSTA | CCR_RSVD);
 229                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
 230                 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 231                 if (ret) {
 232                         dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 233                         return;
 234                 }
 235                 val = readb(i2c->base + MPC_I2C_DR);
 236                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 237                 if (ret) {
 238                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 239                         return;
 240                 }
 241                 writeccr(i2c, CCR_MEN | CCR_RSVD);
 242         } else {
 243                 val = readb(i2c->base + MPC_I2C_DR);
 244                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 245                 if (ret) {
 246                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 247                         return;
 248                 }
 249                 writeccr(i2c, CCR_MEN);
 250         }
 251 }
 252
 253 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 254 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
 255         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 256         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 257         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 258         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 259         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 260         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 261         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 262         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 263         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 264         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 265         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 266         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 267         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 268         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 269         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 270         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 271         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 272         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 273 };
 274
 275 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 276                                           int prescaler, u32 *real_clk)
 277 {
 278         const struct mpc_i2c_divider *div = NULL;
 279         unsigned int pvr = mfspr(SPRN_PVR);
 280         u32 divider;
 281         int i;
 282
 283         if (clock == MPC_I2C_CLOCK_LEGACY) {
 284                 /* see below - default fdr = 0x3f -> div = 2048 */
 285                 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
 286                 return -EINVAL;
 287         }
 288
 289         /* Determine divider value */
 290         divider = mpc5xxx_get_bus_frequency(node) / clock;
 291
 292         /*
 293          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 294          * is equal to or lower than the requested speed.
 295          */
 296         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 297                 div = &mpc_i2c_dividers_52xx[i];
 298                 /* Old MPC5200 rev A CPUs do not support the high bits */
 299                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 300                         continue;
 301                 if (div->divider >= divider)
 302                         break;
 303         }
 304
 305         *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
 306         return (int)div->fdr;
 307 }
 308
 309 static void mpc_i2c_setup_52xx(struct device_node *node,
 310                                          struct mpc_i2c *i2c,
 311                                          u32 clock, u32 prescaler)
 312 {
 313         int ret, fdr;
 314
 315         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 316                 dev_dbg(i2c->dev, "using fdr %d\n",
 317                         readb(i2c->base + MPC_I2C_FDR));
 318                 return;
 319         }
 320
 321         ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
 322         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 323
 324         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 325
 326         if (ret >= 0)
 327                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
 328                          fdr);
 329 }
 330 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 331 static void mpc_i2c_setup_52xx(struct device_node *node,
 332                                          struct mpc_i2c *i2c,
 333                                          u32 clock, u32 prescaler)
 334 {
 335 }
 336 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 337
 338 #ifdef CONFIG_PPC_MPC512x
 339 static void mpc_i2c_setup_512x(struct device_node *node,
 340                                          struct mpc_i2c *i2c,
 341                                          u32 clock, u32 prescaler)
 342 {
 343         struct device_node *node_ctrl;
 344         void __iomem *ctrl;
 345         const u32 *pval;
 346         u32 idx;
 347
 348         /* Enable I2C interrupts for mpc5121 */
 349         node_ctrl = of_find_compatible_node(NULL, NULL,
 350                                             "fsl,mpc5121-i2c-ctrl");
 351         if (node_ctrl) {
 352                 ctrl = of_iomap(node_ctrl, 0);
 353                 if (ctrl) {
 354                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 355                         pval = of_get_property(node, "reg", NULL);
 356                         idx = (*pval & 0xff) / 0x20;
 357                         setbits32(ctrl, 1 << (24 + idx * 2));
 358                         iounmap(ctrl);
 359                 }
 360                 of_node_put(node_ctrl);
 361         }
 362
 363         /* The clock setup for the 52xx works also fine for the 512x */
 364         mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
 365 }
 366 #else /* CONFIG_PPC_MPC512x */
 367 static void mpc_i2c_setup_512x(struct device_node *node,
 368                                          struct mpc_i2c *i2c,
 369                                          u32 clock, u32 prescaler)
 370 {
 371 }
 372 #endif /* CONFIG_PPC_MPC512x */
 373
 374 #ifdef CONFIG_FSL_SOC
 375 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
 376         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 377         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 378         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 379         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 380         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 381         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 382         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 383         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 384         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 385         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 386         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 387         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 388         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 389         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 390         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 391         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 392         {49152, 0x011e}, {61440, 0x011f}
 393 };
 394
 395 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
 396 {
 397         struct device_node *node = NULL;
 398         u32 __iomem *reg;
 399         u32 val = 0;
 400
 401         node = of_find_node_by_name(NULL, "global-utilities");
 402         if (node) {
 403                 const u32 *prop = of_get_property(node, "reg", NULL);
 404                 if (prop) {
 405                         /*
 406                          * Map and check POR Device Status Register 2
 407                          * (PORDEVSR2) at 0xE0014
 408                          */
 409                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 410                         if (!reg)
 411                                 printk(KERN_ERR
 412                                        "Error: couldn't map PORDEVSR2\n");
 413                         else
 414                                 val = in_be32(reg) & 0x00000080; /* sec-cfg */
 415                         iounmap(reg);
 416                 }
 417         }
 418         of_node_put(node);
 419
 420         return val;
 421 }
 422
 423 static u32 mpc_i2c_get_prescaler_8xxx(void)
 424 {
 425         /* mpc83xx and mpc82xx all have prescaler 1 */
 426         u32 prescaler = 1;
 427
 428         /* mpc85xx */
 429         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
 430                 || pvr_version_is(PVR_VER_E500MC)
 431                 || pvr_version_is(PVR_VER_E5500)
 432                 || pvr_version_is(PVR_VER_E6500)) {
 433                 unsigned int svr = mfspr(SPRN_SVR);
 434
 435                 if ((SVR_SOC_VER(svr) == SVR_8540)
 436                         || (SVR_SOC_VER(svr) == SVR_8541)
 437                         || (SVR_SOC_VER(svr) == SVR_8560)
 438                         || (SVR_SOC_VER(svr) == SVR_8555)
 439                         || (SVR_SOC_VER(svr) == SVR_8610))
 440                         /* the above 85xx SoCs have prescaler 1 */
 441                         prescaler = 1;
 442                 else
 443                         /* all the other 85xx have prescaler 2 */
 444                         prescaler = 2;
 445         }
 446
 447         return prescaler;
 448 }
 449
 450 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 451                                           u32 prescaler, u32 *real_clk)
 452 {
 453         const struct mpc_i2c_divider *div = NULL;
 454         u32 divider;
 455         int i;
 456
 457         if (clock == MPC_I2C_CLOCK_LEGACY) {
 458                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
 459                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
 460                 return -EINVAL;
 461         }
 462
 463         /* Determine proper divider value */
 464         if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
 465                 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 466         if (!prescaler)
 467                 prescaler = mpc_i2c_get_prescaler_8xxx();
 468
 469         divider = fsl_get_sys_freq() / clock / prescaler;
 470
 471         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 472                  fsl_get_sys_freq(), clock, divider);
 473
 474         /*
 475          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 476          * is equal to or lower than the requested speed.
 477          */
 478         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 479                 div = &mpc_i2c_dividers_8xxx[i];
 480                 if (div->divider >= divider)
 481                         break;
 482         }
 483
 484         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
 485         return div ? (int)div->fdr : -EINVAL;
 486 }
 487
 488 static void mpc_i2c_setup_8xxx(struct device_node *node,
 489                                          struct mpc_i2c *i2c,
 490                                          u32 clock, u32 prescaler)
 491 {
 492         int ret, fdr;
 493
 494         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 495                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 496                         readb(i2c->base + MPC_I2C_DFSRR),
 497                         readb(i2c->base + MPC_I2C_FDR));
 498                 return;
 499         }
 500
 501         ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
 502         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 503
 504         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 505         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 506
 507         if (ret >= 0)
 508                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 509                          i2c->real_clk, fdr >> 8, fdr & 0xff);
 510 }
 511
 512 #else /* !CONFIG_FSL_SOC */
 513 static void mpc_i2c_setup_8xxx(struct device_node *node,
 514                                          struct mpc_i2c *i2c,
 515                                          u32 clock, u32 prescaler)
 516 {
 517 }
 518 #endif /* CONFIG_FSL_SOC */
 519
 520 static void mpc_i2c_start(struct mpc_i2c *i2c)
 521 {
 522         /* Clear arbitration */
 523         writeb(0, i2c->base + MPC_I2C_SR);
 524         /* Start with MEN */
 525         writeccr(i2c, CCR_MEN);
 526 }
 527
 528 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 529 {
 530         writeccr(i2c, CCR_MEN);
 531 }
 532
 533 static int mpc_write(struct mpc_i2c *i2c, int target,
 534                      const u8 *data, int length, int restart)
 535 {
 536         int i, result;
 537         unsigned timeout = i2c->adap.timeout;
 538         u32 flags = restart ? CCR_RSTA : 0;
 539
 540         /* Start as master */
 541         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 542         /* Write target byte */
 543         writeb((target << 1), i2c->base + MPC_I2C_DR);
 544
 545         result = i2c_wait(i2c, timeout, 1);
 546         if (result < 0)
 547                 return result;
 548
 549         for (i = 0; i < length; i++) {
 550                 /* Write data byte */
 551                 writeb(data[i], i2c->base + MPC_I2C_DR);
 552
 553                 result = i2c_wait(i2c, timeout, 1);
 554                 if (result < 0)
 555                         return result;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int mpc_read(struct mpc_i2c *i2c, int target,
 562                     u8 *data, int length, int restart, bool recv_len)
 563 {
 564         unsigned timeout = i2c->adap.timeout;
 565         int i, result;
 566         u32 flags = restart ? CCR_RSTA : 0;
 567
 568         /* Switch to read - restart */
 569         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 570         /* Write target address byte - this time with the read flag set */
 571         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 572
 573         result = i2c_wait(i2c, timeout, 1);
 574         if (result < 0)
 575                 return result;
 576
 577         if (length) {
 578                 if (length == 1 && !recv_len)
 579                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 580                 else
 581                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 582                 /* Dummy read */
 583                 readb(i2c->base + MPC_I2C_DR);
 584         }
 585
 586         for (i = 0; i < length; i++) {
 587                 u8 byte;
 588
 589                 result = i2c_wait(i2c, timeout, 0);
 590                 if (result < 0)
 591                         return result;
 592
 593                 /*
 594                  * For block reads, we have to know the total length (1st byte)
 595                  * before we can determine if we are done.
 596                  */
 597                 if (i || !recv_len) {
 598                         /* Generate txack on next to last byte */
 599                         if (i == length - 2)
 600                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
 601                                          | CCR_TXAK);
 602                         /* Do not generate stop on last byte */
 603                         if (i == length - 1)
 604                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
 605                                          | CCR_MTX);
 606                 }
 607
 608                 byte = readb(i2c->base + MPC_I2C_DR);
 609
 610                 /*
 611                  * Adjust length if first received byte is length.
 612                  * The length is 1 length byte plus actually data length
 613                  */
 614                 if (i == 0 && recv_len) {
 615                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
 616                                 return -EPROTO;
 617                         length += byte;
 618                         /*
 619                          * For block reads, generate txack here if data length
 620                          * is 1 byte (total length is 2 bytes).
 621                          */
 622                         if (length == 2)
 623                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
 624                                          | CCR_TXAK);
 625                 }
 626                 data[i] = byte;
 627         }
 628
 629         return length;
 630 }
 631
 632 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 633 {
 634         struct i2c_msg *pmsg;
 635         int i;
 636         int ret = 0;
 637         unsigned long orig_jiffies = jiffies;
 638         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 639
 640         mpc_i2c_start(i2c);
 641
 642         /* Allow bus up to 1s to become not busy */
 643         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 644                 if (signal_pending(current)) {
 645                         dev_dbg(i2c->dev, "Interrupted\n");
 646                         writeccr(i2c, 0);
 647                         return -EINTR;
 648                 }
 649                 if (time_after(jiffies, orig_jiffies + HZ)) {
 650                         u8 status = readb(i2c->base + MPC_I2C_SR);
 651
 652                         dev_dbg(i2c->dev, "timeout\n");
 653                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 654                                 writeb(status & ~CSR_MAL,
 655                                        i2c->base + MPC_I2C_SR);
 656                                 i2c_recover_bus(&i2c->adap);
 657                         }
 658                         return -EIO;
 659                 }
 660                 schedule();
 661         }
 662
 663         for (i = 0; ret >= 0 && i < num; i++) {
 664                 pmsg = &msgs[i];
 665                 dev_dbg(i2c->dev,
 666                         "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 667                         pmsg->flags & I2C_M_RD ? "read" : "write",
 668                         pmsg->len, pmsg->addr, i + 1, num);
 669                 if (pmsg->flags & I2C_M_RD) {
 670                         bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
 671
 672                         ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
 673                                        recv_len);
 674                         if (recv_len && ret > 0)
 675                                 pmsg->len = ret;
 676                 } else {
 677                         ret =
 678                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 679                 }
 680         }
 681         mpc_i2c_stop(i2c); /* Initiate STOP */
 682         orig_jiffies = jiffies;
 683         /* Wait until STOP is seen, allow up to 1 s */
 684         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 685                 if (time_after(jiffies, orig_jiffies + HZ)) {
 686                         u8 status = readb(i2c->base + MPC_I2C_SR);
 687
 688                         dev_dbg(i2c->dev, "timeout\n");
 689                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 690                                 writeb(status & ~CSR_MAL,
 691                                        i2c->base + MPC_I2C_SR);
 692                                 i2c_recover_bus(&i2c->adap);
 693                         }
 694                         return -EIO;
 695                 }
 696                 cond_resched();
 697         }
 698         return (ret < 0) ? ret : num;
 699 }
 700
 701 static u32 mpc_functionality(struct i2c_adapter *adap)
 702 {
 703         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 704           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
 705 }
 706
 707 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
 708 {
 709         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 710
 711         if (i2c->has_errata_A004447)
 712                 mpc_i2c_fixup_A004447(i2c);
 713         else
 714                 mpc_i2c_fixup(i2c);
 715
 716         return 0;
 717 }
 718
 719 static const struct i2c_algorithm mpc_algo = {
 720         .master_xfer = mpc_xfer,
 721         .functionality = mpc_functionality,
 722 };
 723
 724 static struct i2c_adapter mpc_ops = {
 725         .owner = THIS_MODULE,
 726         .algo = &mpc_algo,
 727         .timeout = HZ,
 728 };
 729
 730 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
 731         .recover_bus = fsl_i2c_bus_recovery,
 732 };
 733
 734 static const struct of_device_id mpc_i2c_of_match[];
 735 static int fsl_i2c_probe(struct platform_device *op)
 736 {
 737         const struct of_device_id *match;
 738         struct mpc_i2c *i2c;
 739         const u32 *prop;
 740         u32 clock = MPC_I2C_CLOCK_LEGACY;
 741         int result = 0;
 742         int plen;
 743         struct resource res;
 744         struct clk *clk;
 745         int err;
 746
 747         match = of_match_device(mpc_i2c_of_match, &op->dev);
 748         if (!match)
 749                 return -EINVAL;
 750
 751         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 752         if (!i2c)
 753                 return -ENOMEM;
 754
 755         i2c->dev = &op->dev; /* for debug and error output */
 756
 757         init_waitqueue_head(&i2c->queue);
 758
 759         i2c->base = of_iomap(op->dev.of_node, 0);
 760         if (!i2c->base) {
 761                 dev_err(i2c->dev, "failed to map controller\n");
 762                 result = -ENOMEM;
 763                 goto fail_map;
 764         }
 765
 766         i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 767         if (i2c->irq) { /* no i2c->irq implies polling */
 768                 result = request_irq(i2c->irq, mpc_i2c_isr,
 769                                      IRQF_SHARED, "i2c-mpc", i2c);
 770                 if (result < 0) {
 771                         dev_err(i2c->dev, "failed to attach interrupt\n");
 772                         goto fail_request;
 773                 }
 774         }
 775
 776         /*
 777          * enable clock for the I2C peripheral (non fatal),
 778          * keep a reference upon successful allocation
 779          */
 780         clk = devm_clk_get(&op->dev, NULL);
 781         if (!IS_ERR(clk)) {
 782                 err = clk_prepare_enable(clk);
 783                 if (err) {
 784                         dev_err(&op->dev, "failed to enable clock\n");
 785                         goto fail_request;
 786                 } else {
 787                         i2c->clk_per = clk;
 788                 }
 789         }
 790
 791         if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
 792                 clock = MPC_I2C_CLOCK_PRESERVE;
 793         } else {
 794                 prop = of_get_property(op->dev.of_node, "clock-frequency",
 795                                         &plen);
 796                 if (prop && plen == sizeof(u32))
 797                         clock = *prop;
 798         }
 799
 800         if (match->data) {
 801                 const struct mpc_i2c_data *data = match->data;
 802                 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
 803         } else {
 804                 /* Backwards compatibility */
 805                 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
 806                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
 807         }
 808
 809         prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
 810         if (prop && plen == sizeof(u32)) {
 811                 mpc_ops.timeout = *prop * HZ / 1000000;
 812                 if (mpc_ops.timeout < 5)
 813                         mpc_ops.timeout = 5;
 814         }
 815         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
 816
 817         platform_set_drvdata(op, i2c);
 818         if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
 819                 i2c->has_errata_A004447 = true;
 820
 821         i2c->adap = mpc_ops;
 822         of_address_to_resource(op->dev.of_node, 0, &res);
 823         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
 824                   "MPC adapter at 0x%llx", (unsigned long long)res.start);
 825         i2c_set_adapdata(&i2c->adap, i2c);
 826         i2c->adap.dev.parent = &op->dev;
 827         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
 828         i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
 829
 830         result = i2c_add_adapter(&i2c->adap);
 831         if (result < 0) {
 832                 dev_err(i2c->dev, "failed to add adapter\n");
 833                 goto fail_add;
 834         }
 835
 836         return result;
 837
 838  fail_add:
 839         if (i2c->clk_per)
 840                 clk_disable_unprepare(i2c->clk_per);
 841         free_irq(i2c->irq, i2c);
 842  fail_request:
 843         irq_dispose_mapping(i2c->irq);
 844         iounmap(i2c->base);
 845  fail_map:
 846         kfree(i2c);
 847         return result;
 848 };
 849
 850 static int fsl_i2c_remove(struct platform_device *op)
 851 {
 852         struct mpc_i2c *i2c = platform_get_drvdata(op);
 853
 854         i2c_del_adapter(&i2c->adap);
 855
 856         if (i2c->clk_per)
 857                 clk_disable_unprepare(i2c->clk_per);
 858
 859         if (i2c->irq)
 860                 free_irq(i2c->irq, i2c);
 861
 862         irq_dispose_mapping(i2c->irq);
 863         iounmap(i2c->base);
 864         kfree(i2c);
 865         return 0;
 866 };
 867
 868 #ifdef CONFIG_PM_SLEEP
 869 static int mpc_i2c_suspend(struct device *dev)
 870 {
 871         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 872
 873         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
 874         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
 875
 876         return 0;
 877 }
 878
 879 static int mpc_i2c_resume(struct device *dev)
 880 {
 881         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 882
 883         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
 884         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
 885
 886         return 0;
 887 }
 888
 889 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
 890 #define MPC_I2C_PM_OPS  (&mpc_i2c_pm_ops)
 891 #else
 892 #define MPC_I2C_PM_OPS  NULL
 893 #endif
 894
 895 static const struct mpc_i2c_data mpc_i2c_data_512x = {
 896         .setup = mpc_i2c_setup_512x,
 897 };
 898
 899 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
 900         .setup = mpc_i2c_setup_52xx,
 901 };
 902
 903 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
 904         .setup = mpc_i2c_setup_8xxx,
 905 };
 906
 907 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
 908         .setup = mpc_i2c_setup_8xxx,
 909         .prescaler = 2,
 910 };
 911
 912 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
 913         .setup = mpc_i2c_setup_8xxx,
 914         .prescaler = 3,
 915 };
 916
 917 static const struct of_device_id mpc_i2c_of_match[] = {
 918         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 919         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 920         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 921         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 922         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 923         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 924         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 925         /* Backward compatibility */
 926         {.compatible = "fsl-i2c", },
 927         {},
 928 };
 929 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 930
 931 /* Structure for a device driver */
 932 static struct platform_driver mpc_i2c_driver = {
 933         .probe          = fsl_i2c_probe,
 934         .remove         = fsl_i2c_remove,
 935         .driver = {
 936                 .name = DRV_NAME,
 937                 .of_match_table = mpc_i2c_of_match,
 938                 .pm = MPC_I2C_PM_OPS,
 939         },
 940 };
 941
 942 module_platform_driver(mpc_i2c_driver);
 943
 944 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 945 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 946                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 947 MODULE_LICENSE("GPL");