2 * I2C bus driver for Amlogic Meson SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/completion.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/types.h>
23 /* Meson I2C register map */
25 #define REG_SLAVE_ADDR 0x04
26 #define REG_TOK_LIST0 0x08
27 #define REG_TOK_LIST1 0x0c
28 #define REG_TOK_WDATA0 0x10
29 #define REG_TOK_WDATA1 0x14
30 #define REG_TOK_RDATA0 0x18
31 #define REG_TOK_RDATA1 0x1c
33 /* Control register fields */
34 #define REG_CTRL_START BIT(0)
35 #define REG_CTRL_ACK_IGNORE BIT(1)
36 #define REG_CTRL_STATUS BIT(2)
37 #define REG_CTRL_ERROR BIT(3)
38 #define REG_CTRL_CLKDIV_SHIFT 12
39 #define REG_CTRL_CLKDIV_MASK GENMASK(21, 12)
40 #define REG_CTRL_CLKDIVEXT_SHIFT 28
41 #define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28)
43 #define REG_SLV_ADDR GENMASK(7, 0)
44 #define REG_SLV_SDA_FILTER GENMASK(10, 8)
45 #define REG_SLV_SCL_FILTER GENMASK(13, 11)
46 #define REG_SLV_SCL_LOW GENMASK(27, 16)
47 #define REG_SLV_SCL_LOW_EN BIT(28)
49 #define I2C_TIMEOUT_MS 500
54 TOKEN_SLAVE_ADDR_WRITE,
55 TOKEN_SLAVE_ADDR_READ,
68 * struct meson_i2c - Meson I2C device private data
70 * @adap: I2C adapter instance
71 * @dev: Pointer to device structure
72 * @regs: Base address of the device memory mapped registers
73 * @clk: Pointer to clock structure
75 * @msg: Pointer to the current I2C message
76 * @state: Current state in the driver state machine
77 * @last: Flag set for the last message in the transfer
78 * @count: Number of bytes to be sent/received in current transfer
79 * @pos: Current position in the send/receive buffer
80 * @error: Flag set when an error is received
81 * @lock: To avoid race conditions between irq handler and xfer code
82 * @done: Completion used to wait for transfer termination
83 * @tokens: Sequence of tokens to be written to the device
84 * @num_tokens: Number of tokens
87 struct i2c_adapter adap;
100 struct completion done;
105 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
110 data = readl(i2c->regs + reg);
113 writel(data, i2c->regs + reg);
116 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
123 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
125 if (i2c->num_tokens < 8)
126 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
128 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
133 static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
135 unsigned long clk_rate = clk_get_rate(i2c->clk);
138 div = DIV_ROUND_UP(clk_rate, freq * 4);
140 /* clock divider has 12 bits */
141 if (div >= (1 << 12)) {
142 dev_err(i2c->dev, "requested bus frequency too low\n");
146 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
147 (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
149 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
150 (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
152 /* Disable HIGH/LOW mode */
153 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
155 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
156 clk_rate, freq, div);
159 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
164 rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
165 rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
167 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
168 rdata0, rdata1, len);
170 for (i = 0; i < min(4, len); i++)
171 *buf++ = (rdata0 >> i * 8) & 0xff;
173 for (i = 4; i < min(8, len); i++)
174 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
177 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
179 u32 wdata0 = 0, wdata1 = 0;
182 for (i = 0; i < min(4, len); i++)
183 wdata0 |= *buf++ << (i * 8);
185 for (i = 4; i < min(8, len); i++)
186 wdata1 |= *buf++ << ((i - 4) * 8);
188 writel(wdata0, i2c->regs + REG_TOK_WDATA0);
189 writel(wdata1, i2c->regs + REG_TOK_WDATA1);
191 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
192 wdata0, wdata1, len);
195 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
197 bool write = !(i2c->msg->flags & I2C_M_RD);
200 i2c->count = min(i2c->msg->len - i2c->pos, 8);
202 for (i = 0; i < i2c->count - 1; i++)
203 meson_i2c_add_token(i2c, TOKEN_DATA);
206 if (write || i2c->pos + i2c->count < i2c->msg->len)
207 meson_i2c_add_token(i2c, TOKEN_DATA);
209 meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
213 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
215 if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
216 meson_i2c_add_token(i2c, TOKEN_STOP);
218 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
219 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
222 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
224 struct meson_i2c *i2c = dev_id;
227 spin_lock(&i2c->lock);
229 meson_i2c_reset_tokens(i2c);
230 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
231 ctrl = readl(i2c->regs + REG_CTRL);
233 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
234 i2c->state, i2c->pos, i2c->count, ctrl);
236 if (i2c->state == STATE_IDLE) {
237 spin_unlock(&i2c->lock);
241 if (ctrl & REG_CTRL_ERROR) {
243 * The bit is set when the IGNORE_NAK bit is cleared
244 * and the device didn't respond. In this case, the
245 * I2C controller automatically generates a STOP
248 dev_dbg(i2c->dev, "error bit set\n");
250 i2c->state = STATE_IDLE;
251 complete(&i2c->done);
255 if (i2c->state == STATE_READ && i2c->count)
256 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
258 i2c->pos += i2c->count;
260 if (i2c->pos >= i2c->msg->len) {
261 i2c->state = STATE_IDLE;
262 complete(&i2c->done);
266 /* Restart the processing */
267 meson_i2c_prepare_xfer(i2c);
268 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
270 spin_unlock(&i2c->lock);
275 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
279 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
280 TOKEN_SLAVE_ADDR_WRITE;
283 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR,
284 FIELD_PREP(REG_SLV_ADDR, msg->addr << 1));
286 meson_i2c_add_token(i2c, TOKEN_START);
287 meson_i2c_add_token(i2c, token);
290 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
293 unsigned long time_left, flags;
302 meson_i2c_reset_tokens(i2c);
304 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
305 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
307 if (!(msg->flags & I2C_M_NOSTART))
308 meson_i2c_do_start(i2c, msg);
310 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
311 meson_i2c_prepare_xfer(i2c);
312 reinit_completion(&i2c->done);
314 /* Start the transfer */
315 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
317 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
318 time_left = wait_for_completion_timeout(&i2c->done, time_left);
321 * Protect access to i2c struct and registers from interrupt
322 * handlers triggered by a transfer terminated after the
325 spin_lock_irqsave(&i2c->lock, flags);
327 /* Abort any active operation */
328 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
331 i2c->state = STATE_IDLE;
338 spin_unlock_irqrestore(&i2c->lock, flags);
343 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
346 struct meson_i2c *i2c = adap->algo_data;
349 clk_enable(i2c->clk);
351 for (i = 0; i < num; i++) {
352 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
357 clk_disable(i2c->clk);
362 static u32 meson_i2c_func(struct i2c_adapter *adap)
364 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
367 static const struct i2c_algorithm meson_i2c_algorithm = {
368 .master_xfer = meson_i2c_xfer,
369 .functionality = meson_i2c_func,
372 static int meson_i2c_probe(struct platform_device *pdev)
374 struct device_node *np = pdev->dev.of_node;
375 struct meson_i2c *i2c;
376 struct resource *mem;
377 struct i2c_timings timings;
380 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
384 i2c_parse_fw_timings(&pdev->dev, &timings, true);
386 i2c->dev = &pdev->dev;
387 platform_set_drvdata(pdev, i2c);
389 spin_lock_init(&i2c->lock);
390 init_completion(&i2c->done);
392 i2c->clk = devm_clk_get(&pdev->dev, NULL);
393 if (IS_ERR(i2c->clk)) {
394 dev_err(&pdev->dev, "can't get device clock\n");
395 return PTR_ERR(i2c->clk);
398 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
399 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
400 if (IS_ERR(i2c->regs))
401 return PTR_ERR(i2c->regs);
403 irq = platform_get_irq(pdev, 0);
405 dev_err(&pdev->dev, "can't find IRQ\n");
409 ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
411 dev_err(&pdev->dev, "can't request IRQ\n");
415 ret = clk_prepare(i2c->clk);
417 dev_err(&pdev->dev, "can't prepare clock\n");
421 strlcpy(i2c->adap.name, "Meson I2C adapter",
422 sizeof(i2c->adap.name));
423 i2c->adap.owner = THIS_MODULE;
424 i2c->adap.algo = &meson_i2c_algorithm;
425 i2c->adap.dev.parent = &pdev->dev;
426 i2c->adap.dev.of_node = np;
427 i2c->adap.algo_data = i2c;
430 * A transfer is triggered when START bit changes from 0 to 1.
431 * Ensure that the bit is set to 0 after probe
433 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
435 ret = i2c_add_adapter(&i2c->adap);
437 clk_unprepare(i2c->clk);
441 /* Disable filtering */
442 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
443 REG_SLV_SDA_FILTER | REG_SLV_SCL_FILTER, 0);
445 meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
450 static int meson_i2c_remove(struct platform_device *pdev)
452 struct meson_i2c *i2c = platform_get_drvdata(pdev);
454 i2c_del_adapter(&i2c->adap);
455 clk_unprepare(i2c->clk);
460 static const struct of_device_id meson_i2c_match[] = {
461 { .compatible = "amlogic,meson6-i2c" },
462 { .compatible = "amlogic,meson-gxbb-i2c" },
465 MODULE_DEVICE_TABLE(of, meson_i2c_match);
467 static struct platform_driver meson_i2c_driver = {
468 .probe = meson_i2c_probe,
469 .remove = meson_i2c_remove,
472 .of_match_table = meson_i2c_match,
476 module_platform_driver(meson_i2c_driver);
478 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
479 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
480 MODULE_LICENSE("GPL v2");