drivers/i2c/busses/i2c-ismt.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * Copyright(c) 2012 Intel Corporation. All rights reserved.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  * The full GNU General Public License is included in this distribution
  18  * in the file called LICENSE.GPL.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  *   * Redistributions of source code must retain the above copyright
  27  *     notice, this list of conditions and the following disclaimer.
  28  *   * Redistributions in binary form must reproduce the above copyright
  29  *     notice, this list of conditions and the following disclaimer in
  30  *     the documentation and/or other materials provided with the
  31  *     distribution.
  32  *   * Neither the name of Intel Corporation nor the names of its
  33  *     contributors may be used to endorse or promote products derived
  34  *     from this software without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47  */
  48
  49 /*
  50  *  Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
  51  *  S12xx Product Family.
  52  *
  53  *  Features supported by this driver:
  54  *  Hardware PEC                     yes
  55  *  Block buffer                     yes
  56  *  Block process call transaction   no
  57  *  Slave mode                       no
  58  */
  59
  60 #include <linux/module.h>
  61 #include <linux/pci.h>
  62 #include <linux/kernel.h>
  63 #include <linux/stddef.h>
  64 #include <linux/completion.h>
  65 #include <linux/dma-mapping.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <linux/interrupt.h>
  69
  70 #include <linux/io-64-nonatomic-lo-hi.h>
  71
  72 /* PCI Address Constants */
  73 #define SMBBAR          0
  74
  75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
  76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0  0x0c59
  77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1  0x0c5a
  78 #define PCI_DEVICE_ID_INTEL_CDF_SMT     0x18ac
  79 #define PCI_DEVICE_ID_INTEL_DNV_SMT     0x19ac
  80 #define PCI_DEVICE_ID_INTEL_EBG_SMT     0x1bff
  81 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT  0x1f15
  82
  83 #define ISMT_DESC_ENTRIES       2       /* number of descriptor entries */
  84 #define ISMT_MAX_RETRIES        3       /* number of SMBus retries to attempt */
  85 #define ISMT_LOG_ENTRIES        3       /* number of interrupt cause log entries */
  86
  87 /* Hardware Descriptor Constants - Control Field */
  88 #define ISMT_DESC_CWRL  0x01    /* Command/Write Length */
  89 #define ISMT_DESC_BLK   0X04    /* Perform Block Transaction */
  90 #define ISMT_DESC_FAIR  0x08    /* Set fairness flag upon successful arbit. */
  91 #define ISMT_DESC_PEC   0x10    /* Packet Error Code */
  92 #define ISMT_DESC_I2C   0x20    /* I2C Enable */
  93 #define ISMT_DESC_INT   0x40    /* Interrupt */
  94 #define ISMT_DESC_SOE   0x80    /* Stop On Error */
  95
  96 /* Hardware Descriptor Constants - Status Field */
  97 #define ISMT_DESC_SCS   0x01    /* Success */
  98 #define ISMT_DESC_DLTO  0x04    /* Data Low Time Out */
  99 #define ISMT_DESC_NAK   0x08    /* NAK Received */
 100 #define ISMT_DESC_CRC   0x10    /* CRC Error */
 101 #define ISMT_DESC_CLTO  0x20    /* Clock Low Time Out */
 102 #define ISMT_DESC_COL   0x40    /* Collisions */
 103 #define ISMT_DESC_LPR   0x80    /* Large Packet Received */
 104
 105 /* Macros */
 106 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
 107
 108 /* iSMT General Register address offsets (SMBBAR + <addr>) */
 109 #define ISMT_GR_GCTRL           0x000   /* General Control */
 110 #define ISMT_GR_SMTICL          0x008   /* SMT Interrupt Cause Location */
 111 #define ISMT_GR_ERRINTMSK       0x010   /* Error Interrupt Mask */
 112 #define ISMT_GR_ERRAERMSK       0x014   /* Error AER Mask */
 113 #define ISMT_GR_ERRSTS          0x018   /* Error Status */
 114 #define ISMT_GR_ERRINFO         0x01c   /* Error Information */
 115
 116 /* iSMT Master Registers */
 117 #define ISMT_MSTR_MDBA          0x100   /* Master Descriptor Base Address */
 118 #define ISMT_MSTR_MCTRL         0x108   /* Master Control */
 119 #define ISMT_MSTR_MSTS          0x10c   /* Master Status */
 120 #define ISMT_MSTR_MDS           0x110   /* Master Descriptor Size */
 121 #define ISMT_MSTR_RPOLICY       0x114   /* Retry Policy */
 122
 123 /* iSMT Miscellaneous Registers */
 124 #define ISMT_SPGT       0x300   /* SMBus PHY Global Timing */
 125
 126 /* General Control Register (GCTRL) bit definitions */
 127 #define ISMT_GCTRL_TRST 0x04    /* Target Reset */
 128 #define ISMT_GCTRL_KILL 0x08    /* Kill */
 129 #define ISMT_GCTRL_SRST 0x40    /* Soft Reset */
 130
 131 /* Master Control Register (MCTRL) bit definitions */
 132 #define ISMT_MCTRL_SS   0x01            /* Start/Stop */
 133 #define ISMT_MCTRL_MEIE 0x10            /* Master Error Interrupt Enable */
 134 #define ISMT_MCTRL_FMHP 0x00ff0000      /* Firmware Master Head Ptr (FMHP) */
 135
 136 /* Master Status Register (MSTS) bit definitions */
 137 #define ISMT_MSTS_HMTP  0xff0000        /* HW Master Tail Pointer (HMTP) */
 138 #define ISMT_MSTS_MIS   0x20            /* Master Interrupt Status (MIS) */
 139 #define ISMT_MSTS_MEIS  0x10            /* Master Error Int Status (MEIS) */
 140 #define ISMT_MSTS_IP    0x01            /* In Progress */
 141
 142 /* Master Descriptor Size (MDS) bit definitions */
 143 #define ISMT_MDS_MASK   0xff    /* Master Descriptor Size mask (MDS) */
 144
 145 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
 146 #define ISMT_SPGT_SPD_MASK      0xc0000000      /* SMBus Speed mask */
 147 #define ISMT_SPGT_SPD_80K       0x00            /* 80 kHz */
 148 #define ISMT_SPGT_SPD_100K      (0x1 << 30)     /* 100 kHz */
 149 #define ISMT_SPGT_SPD_400K      (0x2 << 30)     /* 400 kHz */
 150 #define ISMT_SPGT_SPD_1M        (0x3 << 30)     /* 1 MHz */
 151
 152
 153 /* MSI Control Register (MSICTL) bit definitions */
 154 #define ISMT_MSICTL_MSIE        0x01    /* MSI Enable */
 155
 156 /* iSMT Hardware Descriptor */
 157 struct ismt_desc {
 158         u8 tgtaddr_rw;  /* target address & r/w bit */
 159         u8 wr_len_cmd;  /* write length in bytes or a command */
 160         u8 rd_len;      /* read length */
 161         u8 control;     /* control bits */
 162         u8 status;      /* status bits */
 163         u8 retry;       /* collision retry and retry count */
 164         u8 rxbytes;     /* received bytes */
 165         u8 txbytes;     /* transmitted bytes */
 166         u32 dptr_low;   /* lower 32 bit of the data pointer */
 167         u32 dptr_high;  /* upper 32 bit of the data pointer */
 168 } __packed;
 169
 170 struct ismt_priv {
 171         struct i2c_adapter adapter;
 172         void __iomem *smba;                     /* PCI BAR */
 173         struct pci_dev *pci_dev;
 174         struct ismt_desc *hw;                   /* descriptor virt base addr */
 175         dma_addr_t io_rng_dma;                  /* descriptor HW base addr */
 176         u8 head;                                /* ring buffer head pointer */
 177         struct completion cmp;                  /* interrupt completion */
 178         u8 buffer[I2C_SMBUS_BLOCK_MAX + 16];    /* temp R/W data buffer */
 179         dma_addr_t log_dma;
 180         u32 *log;
 181 };
 182
 183 static const struct pci_device_id ismt_ids[] = {
 184         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
 185         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
 186         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
 187         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
 188         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
 189         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
 190         { 0, }
 191 };
 192
 193 MODULE_DEVICE_TABLE(pci, ismt_ids);
 194
 195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
 196 static unsigned int bus_speed;
 197 module_param(bus_speed, uint, S_IRUGO);
 198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
 199
 200 /**
 201  * __ismt_desc_dump() - dump the contents of a specific descriptor
 202  * @dev: the iSMT device
 203  * @desc: the iSMT hardware descriptor
 204  */
 205 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
 206 {
 207
 208         dev_dbg(dev, "Descriptor struct:  %p\n", desc);
 209         dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
 210         dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
 211         dev_dbg(dev, "\trd_len=    0x%02X\n", desc->rd_len);
 212         dev_dbg(dev, "\tcontrol=   0x%02X\n", desc->control);
 213         dev_dbg(dev, "\tstatus=    0x%02X\n", desc->status);
 214         dev_dbg(dev, "\tretry=     0x%02X\n", desc->retry);
 215         dev_dbg(dev, "\trxbytes=   0x%02X\n", desc->rxbytes);
 216         dev_dbg(dev, "\ttxbytes=   0x%02X\n", desc->txbytes);
 217         dev_dbg(dev, "\tdptr_low=  0x%08X\n", desc->dptr_low);
 218         dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
 219 }
 220 /**
 221  * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
 222  * @priv: iSMT private data
 223  */
 224 static void ismt_desc_dump(struct ismt_priv *priv)
 225 {
 226         struct device *dev = &priv->pci_dev->dev;
 227         struct ismt_desc *desc = &priv->hw[priv->head];
 228
 229         dev_dbg(dev, "Dump of the descriptor struct:  0x%X\n", priv->head);
 230         __ismt_desc_dump(dev, desc);
 231 }
 232
 233 /**
 234  * ismt_gen_reg_dump() - dump the iSMT General Registers
 235  * @priv: iSMT private data
 236  */
 237 static void ismt_gen_reg_dump(struct ismt_priv *priv)
 238 {
 239         struct device *dev = &priv->pci_dev->dev;
 240
 241         dev_dbg(dev, "Dump of the iSMT General Registers\n");
 242         dev_dbg(dev, "  GCTRL.... : (0x%p)=0x%X\n",
 243                 priv->smba + ISMT_GR_GCTRL,
 244                 readl(priv->smba + ISMT_GR_GCTRL));
 245         dev_dbg(dev, "  SMTICL... : (0x%p)=0x%016llX\n",
 246                 priv->smba + ISMT_GR_SMTICL,
 247                 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
 248         dev_dbg(dev, "  ERRINTMSK : (0x%p)=0x%X\n",
 249                 priv->smba + ISMT_GR_ERRINTMSK,
 250                 readl(priv->smba + ISMT_GR_ERRINTMSK));
 251         dev_dbg(dev, "  ERRAERMSK : (0x%p)=0x%X\n",
 252                 priv->smba + ISMT_GR_ERRAERMSK,
 253                 readl(priv->smba + ISMT_GR_ERRAERMSK));
 254         dev_dbg(dev, "  ERRSTS... : (0x%p)=0x%X\n",
 255                 priv->smba + ISMT_GR_ERRSTS,
 256                 readl(priv->smba + ISMT_GR_ERRSTS));
 257         dev_dbg(dev, "  ERRINFO.. : (0x%p)=0x%X\n",
 258                 priv->smba + ISMT_GR_ERRINFO,
 259                 readl(priv->smba + ISMT_GR_ERRINFO));
 260 }
 261
 262 /**
 263  * ismt_mstr_reg_dump() - dump the iSMT Master Registers
 264  * @priv: iSMT private data
 265  */
 266 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
 267 {
 268         struct device *dev = &priv->pci_dev->dev;
 269
 270         dev_dbg(dev, "Dump of the iSMT Master Registers\n");
 271         dev_dbg(dev, "  MDBA..... : (0x%p)=0x%016llX\n",
 272                 priv->smba + ISMT_MSTR_MDBA,
 273                 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
 274         dev_dbg(dev, "  MCTRL.... : (0x%p)=0x%X\n",
 275                 priv->smba + ISMT_MSTR_MCTRL,
 276                 readl(priv->smba + ISMT_MSTR_MCTRL));
 277         dev_dbg(dev, "  MSTS..... : (0x%p)=0x%X\n",
 278                 priv->smba + ISMT_MSTR_MSTS,
 279                 readl(priv->smba + ISMT_MSTR_MSTS));
 280         dev_dbg(dev, "  MDS...... : (0x%p)=0x%X\n",
 281                 priv->smba + ISMT_MSTR_MDS,
 282                 readl(priv->smba + ISMT_MSTR_MDS));
 283         dev_dbg(dev, "  RPOLICY.. : (0x%p)=0x%X\n",
 284                 priv->smba + ISMT_MSTR_RPOLICY,
 285                 readl(priv->smba + ISMT_MSTR_RPOLICY));
 286         dev_dbg(dev, "  SPGT..... : (0x%p)=0x%X\n",
 287                 priv->smba + ISMT_SPGT,
 288                 readl(priv->smba + ISMT_SPGT));
 289 }
 290
 291 /**
 292  * ismt_submit_desc() - add a descriptor to the ring
 293  * @priv: iSMT private data
 294  */
 295 static void ismt_submit_desc(struct ismt_priv *priv)
 296 {
 297         uint fmhp;
 298         uint val;
 299
 300         ismt_desc_dump(priv);
 301         ismt_gen_reg_dump(priv);
 302         ismt_mstr_reg_dump(priv);
 303
 304         /* Set the FMHP (Firmware Master Head Pointer)*/
 305         fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
 306         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 307         writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
 308                priv->smba + ISMT_MSTR_MCTRL);
 309
 310         /* Set the start bit */
 311         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 312         writel(val | ISMT_MCTRL_SS,
 313                priv->smba + ISMT_MSTR_MCTRL);
 314 }
 315
 316 /**
 317  * ismt_process_desc() - handle the completion of the descriptor
 318  * @desc: the iSMT hardware descriptor
 319  * @data: data buffer from the upper layer
 320  * @priv: ismt_priv struct holding our dma buffer
 321  * @size: SMBus transaction type
 322  * @read_write: flag to indicate if this is a read or write
 323  */
 324 static int ismt_process_desc(const struct ismt_desc *desc,
 325                              union i2c_smbus_data *data,
 326                              struct ismt_priv *priv, int size,
 327                              char read_write)
 328 {
 329         u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
 330
 331         dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
 332         __ismt_desc_dump(&priv->pci_dev->dev, desc);
 333         ismt_gen_reg_dump(priv);
 334         ismt_mstr_reg_dump(priv);
 335
 336         if (desc->status & ISMT_DESC_SCS) {
 337                 if (read_write == I2C_SMBUS_WRITE &&
 338                     size != I2C_SMBUS_PROC_CALL)
 339                         return 0;
 340
 341                 switch (size) {
 342                 case I2C_SMBUS_BYTE:
 343                 case I2C_SMBUS_BYTE_DATA:
 344                         data->byte = dma_buffer[0];
 345                         break;
 346                 case I2C_SMBUS_WORD_DATA:
 347                 case I2C_SMBUS_PROC_CALL:
 348                         data->word = dma_buffer[0] | (dma_buffer[1] << 8);
 349                         break;
 350                 case I2C_SMBUS_BLOCK_DATA:
 351                         if (desc->rxbytes != dma_buffer[0] + 1)
 352                                 return -EMSGSIZE;
 353
 354                         memcpy(data->block, dma_buffer, desc->rxbytes);
 355                         break;
 356                 case I2C_SMBUS_I2C_BLOCK_DATA:
 357                         memcpy(&data->block[1], dma_buffer, desc->rxbytes);
 358                         data->block[0] = desc->rxbytes;
 359                         break;
 360                 }
 361                 return 0;
 362         }
 363
 364         if (likely(desc->status & ISMT_DESC_NAK))
 365                 return -ENXIO;
 366
 367         if (desc->status & ISMT_DESC_CRC)
 368                 return -EBADMSG;
 369
 370         if (desc->status & ISMT_DESC_COL)
 371                 return -EAGAIN;
 372
 373         if (desc->status & ISMT_DESC_LPR)
 374                 return -EPROTO;
 375
 376         if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
 377                 return -ETIMEDOUT;
 378
 379         return -EIO;
 380 }
 381
 382 /**
 383  * ismt_access() - process an SMBus command
 384  * @adap: the i2c host adapter
 385  * @addr: address of the i2c/SMBus target
 386  * @flags: command options
 387  * @read_write: read from or write to device
 388  * @command: the i2c/SMBus command to issue
 389  * @size: SMBus transaction type
 390  * @data: read/write data buffer
 391  */
 392 static int ismt_access(struct i2c_adapter *adap, u16 addr,
 393                        unsigned short flags, char read_write, u8 command,
 394                        int size, union i2c_smbus_data *data)
 395 {
 396         int ret;
 397         unsigned long time_left;
 398         dma_addr_t dma_addr = 0; /* address of the data buffer */
 399         u8 dma_size = 0;
 400         enum dma_data_direction dma_direction = 0;
 401         struct ismt_desc *desc;
 402         struct ismt_priv *priv = i2c_get_adapdata(adap);
 403         struct device *dev = &priv->pci_dev->dev;
 404         u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
 405
 406         desc = &priv->hw[priv->head];
 407
 408         /* Initialize the DMA buffer */
 409         memset(priv->buffer, 0, sizeof(priv->buffer));
 410
 411         /* Initialize the descriptor */
 412         memset(desc, 0, sizeof(struct ismt_desc));
 413         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
 414
 415         /* Always clear the log entries */
 416         memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32));
 417
 418         /* Initialize common control bits */
 419         if (likely(pci_dev_msi_enabled(priv->pci_dev)))
 420                 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
 421         else
 422                 desc->control = ISMT_DESC_FAIR;
 423
 424         if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
 425             && (size != I2C_SMBUS_I2C_BLOCK_DATA))
 426                 desc->control |= ISMT_DESC_PEC;
 427
 428         switch (size) {
 429         case I2C_SMBUS_QUICK:
 430                 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
 431                 break;
 432
 433         case I2C_SMBUS_BYTE:
 434                 if (read_write == I2C_SMBUS_WRITE) {
 435                         /*
 436                          * Send Byte
 437                          * The command field contains the write data
 438                          */
 439                         dev_dbg(dev, "I2C_SMBUS_BYTE:  WRITE\n");
 440                         desc->control |= ISMT_DESC_CWRL;
 441                         desc->wr_len_cmd = command;
 442                 } else {
 443                         /* Receive Byte */
 444                         dev_dbg(dev, "I2C_SMBUS_BYTE:  READ\n");
 445                         dma_size = 1;
 446                         dma_direction = DMA_FROM_DEVICE;
 447                         desc->rd_len = 1;
 448                 }
 449                 break;
 450
 451         case I2C_SMBUS_BYTE_DATA:
 452                 if (read_write == I2C_SMBUS_WRITE) {
 453                         /*
 454                          * Write Byte
 455                          * Command plus 1 data byte
 456                          */
 457                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  WRITE\n");
 458                         desc->wr_len_cmd = 2;
 459                         dma_size = 2;
 460                         dma_direction = DMA_TO_DEVICE;
 461                         dma_buffer[0] = command;
 462                         dma_buffer[1] = data->byte;
 463                 } else {
 464                         /* Read Byte */
 465                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  READ\n");
 466                         desc->control |= ISMT_DESC_CWRL;
 467                         desc->wr_len_cmd = command;
 468                         desc->rd_len = 1;
 469                         dma_size = 1;
 470                         dma_direction = DMA_FROM_DEVICE;
 471                 }
 472                 break;
 473
 474         case I2C_SMBUS_WORD_DATA:
 475                 if (read_write == I2C_SMBUS_WRITE) {
 476                         /* Write Word */
 477                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  WRITE\n");
 478                         desc->wr_len_cmd = 3;
 479                         dma_size = 3;
 480                         dma_direction = DMA_TO_DEVICE;
 481                         dma_buffer[0] = command;
 482                         dma_buffer[1] = data->word & 0xff;
 483                         dma_buffer[2] = data->word >> 8;
 484                 } else {
 485                         /* Read Word */
 486                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  READ\n");
 487                         desc->wr_len_cmd = command;
 488                         desc->control |= ISMT_DESC_CWRL;
 489                         desc->rd_len = 2;
 490                         dma_size = 2;
 491                         dma_direction = DMA_FROM_DEVICE;
 492                 }
 493                 break;
 494
 495         case I2C_SMBUS_PROC_CALL:
 496                 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
 497                 desc->wr_len_cmd = 3;
 498                 desc->rd_len = 2;
 499                 dma_size = 3;
 500                 dma_direction = DMA_BIDIRECTIONAL;
 501                 dma_buffer[0] = command;
 502                 dma_buffer[1] = data->word & 0xff;
 503                 dma_buffer[2] = data->word >> 8;
 504                 break;
 505
 506         case I2C_SMBUS_BLOCK_DATA:
 507                 if (read_write == I2C_SMBUS_WRITE) {
 508                         /* Block Write */
 509                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  WRITE\n");
 510                         dma_size = data->block[0] + 1;
 511                         dma_direction = DMA_TO_DEVICE;
 512                         desc->wr_len_cmd = dma_size;
 513                         desc->control |= ISMT_DESC_BLK;
 514                         dma_buffer[0] = command;
 515                         memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
 516                 } else {
 517                         /* Block Read */
 518                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  READ\n");
 519                         dma_size = I2C_SMBUS_BLOCK_MAX;
 520                         dma_direction = DMA_FROM_DEVICE;
 521                         desc->rd_len = dma_size;
 522                         desc->wr_len_cmd = command;
 523                         desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
 524                 }
 525                 break;
 526
 527         case I2C_SMBUS_I2C_BLOCK_DATA:
 528                 /* Make sure the length is valid */
 529                 if (data->block[0] < 1)
 530                         data->block[0] = 1;
 531
 532                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 533                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 534
 535                 if (read_write == I2C_SMBUS_WRITE) {
 536                         /* i2c Block Write */
 537                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  WRITE\n");
 538                         dma_size = data->block[0] + 1;
 539                         dma_direction = DMA_TO_DEVICE;
 540                         desc->wr_len_cmd = dma_size;
 541                         desc->control |= ISMT_DESC_I2C;
 542                         dma_buffer[0] = command;
 543                         memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
 544                 } else {
 545                         /* i2c Block Read */
 546                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  READ\n");
 547                         dma_size = data->block[0];
 548                         dma_direction = DMA_FROM_DEVICE;
 549                         desc->rd_len = dma_size;
 550                         desc->wr_len_cmd = command;
 551                         desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
 552                         /*
 553                          * Per the "Table 15-15. I2C Commands",
 554                          * in the External Design Specification (EDS),
 555                          * (Document Number: 508084, Revision: 2.0),
 556                          * the _rw bit must be 0
 557                          */
 558                         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
 559                 }
 560                 break;
 561
 562         default:
 563                 dev_err(dev, "Unsupported transaction %d\n",
 564                         size);
 565                 return -EOPNOTSUPP;
 566         }
 567
 568         /* map the data buffer */
 569         if (dma_size != 0) {
 570                 dev_dbg(dev, " dev=%p\n", dev);
 571                 dev_dbg(dev, " data=%p\n", data);
 572                 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
 573                 dev_dbg(dev, " dma_size=%d\n", dma_size);
 574                 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
 575
 576                 dma_addr = dma_map_single(dev,
 577                                       dma_buffer,
 578                                       dma_size,
 579                                       dma_direction);
 580
 581                 if (dma_mapping_error(dev, dma_addr)) {
 582                         dev_err(dev, "Error in mapping dma buffer %p\n",
 583                                 dma_buffer);
 584                         return -EIO;
 585                 }
 586
 587                 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
 588
 589                 desc->dptr_low = lower_32_bits(dma_addr);
 590                 desc->dptr_high = upper_32_bits(dma_addr);
 591         }
 592
 593         reinit_completion(&priv->cmp);
 594
 595         /* Add the descriptor */
 596         ismt_submit_desc(priv);
 597
 598         /* Now we wait for interrupt completion, 1s */
 599         time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
 600
 601         /* unmap the data buffer */
 602         if (dma_size != 0)
 603                 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
 604
 605         if (unlikely(!time_left)) {
 606                 dev_err(dev, "completion wait timed out\n");
 607                 ret = -ETIMEDOUT;
 608                 goto out;
 609         }
 610
 611         /* do any post processing of the descriptor here */
 612         ret = ismt_process_desc(desc, data, priv, size, read_write);
 613
 614 out:
 615         /* Update the ring pointer */
 616         priv->head++;
 617         priv->head %= ISMT_DESC_ENTRIES;
 618
 619         return ret;
 620 }
 621
 622 /**
 623  * ismt_func() - report which i2c commands are supported by this adapter
 624  * @adap: the i2c host adapter
 625  */
 626 static u32 ismt_func(struct i2c_adapter *adap)
 627 {
 628         return I2C_FUNC_SMBUS_QUICK             |
 629                I2C_FUNC_SMBUS_BYTE              |
 630                I2C_FUNC_SMBUS_BYTE_DATA         |
 631                I2C_FUNC_SMBUS_WORD_DATA         |
 632                I2C_FUNC_SMBUS_PROC_CALL         |
 633                I2C_FUNC_SMBUS_BLOCK_DATA        |
 634                I2C_FUNC_SMBUS_I2C_BLOCK         |
 635                I2C_FUNC_SMBUS_PEC;
 636 }
 637
 638 static const struct i2c_algorithm smbus_algorithm = {
 639         .smbus_xfer     = ismt_access,
 640         .functionality  = ismt_func,
 641 };
 642
 643 /**
 644  * ismt_handle_isr() - interrupt handler bottom half
 645  * @priv: iSMT private data
 646  */
 647 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
 648 {
 649         complete(&priv->cmp);
 650
 651         return IRQ_HANDLED;
 652 }
 653
 654
 655 /**
 656  * ismt_do_interrupt() - IRQ interrupt handler
 657  * @vec: interrupt vector
 658  * @data: iSMT private data
 659  */
 660 static irqreturn_t ismt_do_interrupt(int vec, void *data)
 661 {
 662         u32 val;
 663         struct ismt_priv *priv = data;
 664
 665         /*
 666          * check to see it's our interrupt, return IRQ_NONE if not ours
 667          * since we are sharing interrupt
 668          */
 669         val = readl(priv->smba + ISMT_MSTR_MSTS);
 670
 671         if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
 672                 return IRQ_NONE;
 673         else
 674                 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
 675                        priv->smba + ISMT_MSTR_MSTS);
 676
 677         return ismt_handle_isr(priv);
 678 }
 679
 680 /**
 681  * ismt_do_msi_interrupt() - MSI interrupt handler
 682  * @vec: interrupt vector
 683  * @data: iSMT private data
 684  */
 685 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
 686 {
 687         return ismt_handle_isr(data);
 688 }
 689
 690 /**
 691  * ismt_hw_init() - initialize the iSMT hardware
 692  * @priv: iSMT private data
 693  */
 694 static void ismt_hw_init(struct ismt_priv *priv)
 695 {
 696         u32 val;
 697         struct device *dev = &priv->pci_dev->dev;
 698
 699         /* initialize the Master Descriptor Base Address (MDBA) */
 700         writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
 701
 702         writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);
 703
 704         /* initialize the Master Control Register (MCTRL) */
 705         writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
 706
 707         /* initialize the Master Status Register (MSTS) */
 708         writel(0, priv->smba + ISMT_MSTR_MSTS);
 709
 710         /* initialize the Master Descriptor Size (MDS) */
 711         val = readl(priv->smba + ISMT_MSTR_MDS);
 712         writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
 713                 priv->smba + ISMT_MSTR_MDS);
 714
 715         /*
 716          * Set the SMBus speed (could use this for slow HW debuggers)
 717          */
 718
 719         val = readl(priv->smba + ISMT_SPGT);
 720
 721         switch (bus_speed) {
 722         case 0:
 723                 break;
 724
 725         case 80:
 726                 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
 727                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
 728                         priv->smba + ISMT_SPGT);
 729                 break;
 730
 731         case 100:
 732                 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
 733                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
 734                         priv->smba + ISMT_SPGT);
 735                 break;
 736
 737         case 400:
 738                 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
 739                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
 740                         priv->smba + ISMT_SPGT);
 741                 break;
 742
 743         case 1000:
 744                 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
 745                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
 746                         priv->smba + ISMT_SPGT);
 747                 break;
 748
 749         default:
 750                 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
 751                 break;
 752         }
 753
 754         val = readl(priv->smba + ISMT_SPGT);
 755
 756         switch (val & ISMT_SPGT_SPD_MASK) {
 757         case ISMT_SPGT_SPD_80K:
 758                 bus_speed = 80;
 759                 break;
 760         case ISMT_SPGT_SPD_100K:
 761                 bus_speed = 100;
 762                 break;
 763         case ISMT_SPGT_SPD_400K:
 764                 bus_speed = 400;
 765                 break;
 766         case ISMT_SPGT_SPD_1M:
 767                 bus_speed = 1000;
 768                 break;
 769         }
 770         dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
 771 }
 772
 773 /**
 774  * ismt_dev_init() - initialize the iSMT data structures
 775  * @priv: iSMT private data
 776  */
 777 static int ismt_dev_init(struct ismt_priv *priv)
 778 {
 779         /* allocate memory for the descriptor */
 780         priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
 781                                        (ISMT_DESC_ENTRIES
 782                                                * sizeof(struct ismt_desc)),
 783                                        &priv->io_rng_dma,
 784                                        GFP_KERNEL);
 785         if (!priv->hw)
 786                 return -ENOMEM;
 787
 788         priv->head = 0;
 789         init_completion(&priv->cmp);
 790
 791         priv->log = dmam_alloc_coherent(&priv->pci_dev->dev,
 792                                         ISMT_LOG_ENTRIES * sizeof(u32),
 793                                         &priv->log_dma, GFP_KERNEL);
 794         if (!priv->log)
 795                 return -ENOMEM;
 796
 797         return 0;
 798 }
 799
 800 /**
 801  * ismt_int_init() - initialize interrupts
 802  * @priv: iSMT private data
 803  */
 804 static int ismt_int_init(struct ismt_priv *priv)
 805 {
 806         int err;
 807
 808         /* Try using MSI interrupts */
 809         err = pci_enable_msi(priv->pci_dev);
 810         if (err)
 811                 goto intx;
 812
 813         err = devm_request_irq(&priv->pci_dev->dev,
 814                                priv->pci_dev->irq,
 815                                ismt_do_msi_interrupt,
 816                                0,
 817                                "ismt-msi",
 818                                priv);
 819         if (err) {
 820                 pci_disable_msi(priv->pci_dev);
 821                 goto intx;
 822         }
 823
 824         return 0;
 825
 826         /* Try using legacy interrupts */
 827 intx:
 828         dev_warn(&priv->pci_dev->dev,
 829                  "Unable to use MSI interrupts, falling back to legacy\n");
 830
 831         err = devm_request_irq(&priv->pci_dev->dev,
 832                                priv->pci_dev->irq,
 833                                ismt_do_interrupt,
 834                                IRQF_SHARED,
 835                                "ismt-intx",
 836                                priv);
 837         if (err) {
 838                 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
 839                 return err;
 840         }
 841
 842         return 0;
 843 }
 844
 845 static struct pci_driver ismt_driver;
 846
 847 /**
 848  * ismt_probe() - probe for iSMT devices
 849  * @pdev: PCI-Express device
 850  * @id: PCI-Express device ID
 851  */
 852 static int
 853 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 854 {
 855         int err;
 856         struct ismt_priv *priv;
 857         unsigned long start, len;
 858
 859         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 860         if (!priv)
 861                 return -ENOMEM;
 862
 863         pci_set_drvdata(pdev, priv);
 864
 865         i2c_set_adapdata(&priv->adapter, priv);
 866         priv->adapter.owner = THIS_MODULE;
 867         priv->adapter.class = I2C_CLASS_HWMON;
 868         priv->adapter.algo = &smbus_algorithm;
 869         priv->adapter.dev.parent = &pdev->dev;
 870         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
 871         priv->adapter.retries = ISMT_MAX_RETRIES;
 872
 873         priv->pci_dev = pdev;
 874
 875         err = pcim_enable_device(pdev);
 876         if (err) {
 877                 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
 878                         err);
 879                 return err;
 880         }
 881
 882         /* enable bus mastering */
 883         pci_set_master(pdev);
 884
 885         /* Determine the address of the SMBus area */
 886         start = pci_resource_start(pdev, SMBBAR);
 887         len = pci_resource_len(pdev, SMBBAR);
 888         if (!start || !len) {
 889                 dev_err(&pdev->dev,
 890                         "SMBus base address uninitialized, upgrade BIOS\n");
 891                 return -ENODEV;
 892         }
 893
 894         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 895                  "SMBus iSMT adapter at %lx", start);
 896
 897         dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
 898         dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
 899
 900         err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
 901         if (err) {
 902                 dev_err(&pdev->dev, "ACPI resource conflict!\n");
 903                 return err;
 904         }
 905
 906         err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
 907         if (err) {
 908                 dev_err(&pdev->dev,
 909                         "Failed to request SMBus region 0x%lx-0x%lx\n",
 910                         start, start + len);
 911                 return err;
 912         }
 913
 914         priv->smba = pcim_iomap(pdev, SMBBAR, len);
 915         if (!priv->smba) {
 916                 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
 917                 return -ENODEV;
 918         }
 919
 920         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
 921             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
 922                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
 923                     (pci_set_consistent_dma_mask(pdev,
 924                                                  DMA_BIT_MASK(32)) != 0)) {
 925                         dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
 926                                 pdev);
 927                         return -ENODEV;
 928                 }
 929         }
 930
 931         err = ismt_dev_init(priv);
 932         if (err)
 933                 return err;
 934
 935         ismt_hw_init(priv);
 936
 937         err = ismt_int_init(priv);
 938         if (err)
 939                 return err;
 940
 941         err = i2c_add_adapter(&priv->adapter);
 942         if (err)
 943                 return -ENODEV;
 944         return 0;
 945 }
 946
 947 /**
 948  * ismt_remove() - release driver resources
 949  * @pdev: PCI-Express device
 950  */
 951 static void ismt_remove(struct pci_dev *pdev)
 952 {
 953         struct ismt_priv *priv = pci_get_drvdata(pdev);
 954
 955         i2c_del_adapter(&priv->adapter);
 956 }
 957
 958 static struct pci_driver ismt_driver = {
 959         .name = "ismt_smbus",
 960         .id_table = ismt_ids,
 961         .probe = ismt_probe,
 962         .remove = ismt_remove,
 963 };
 964
 965 module_pci_driver(ismt_driver);
 966
 967 MODULE_LICENSE("Dual BSD/GPL");
 968 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
 969 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");