2 * Copyright (C) 2002 Motorola GSG-China
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 * Darius Augulis, Teltonika Inc.
18 * Implementation of I2C Adapter/Algorithm Driver
19 * for I2C Bus integrated in Freescale i.MX/MXC processors
21 * Derived from Motorola GSG China I2C example driver
23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
25 * Copyright (C) 2007 RightHand Technologies, Inc.
26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
28 * Copyright 2013 Freescale Semiconductor, Inc.
32 #include <linux/clk.h>
33 #include <linux/completion.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmaengine.h>
37 #include <linux/dmapool.h>
38 #include <linux/err.h>
39 #include <linux/errno.h>
40 #include <linux/i2c.h>
41 #include <linux/init.h>
42 #include <linux/interrupt.h>
44 #include <linux/kernel.h>
45 #include <linux/module.h>
47 #include <linux/of_device.h>
48 #include <linux/of_dma.h>
49 #include <linux/of_gpio.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/platform_data/i2c-imx.h>
52 #include <linux/platform_device.h>
53 #include <linux/pm_runtime.h>
54 #include <linux/sched.h>
55 #include <linux/slab.h>
57 /* This will be the driver name the kernel reports */
58 #define DRIVER_NAME "imx-i2c"
61 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
64 * Enable DMA if transfer byte size is bigger than this threshold.
65 * As the hardware request, it must bigger than 4 bytes.\
66 * I have set '16' here, maybe it's not the best but I think it's
69 #define DMA_THRESHOLD 16
70 #define DMA_TIMEOUT 1000
73 * the I2C register offset is different between SoCs,
74 * to provid support for all these chips, split the
75 * register offset into a fixed base address and a
76 * variable shift value, then the full register offset
77 * will be calculated by
78 * reg_off = ( reg_base_addr << reg_shift)
80 #define IMX_I2C_IADR 0x00 /* i2c slave address */
81 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
82 #define IMX_I2C_I2CR 0x02 /* i2c control */
83 #define IMX_I2C_I2SR 0x03 /* i2c status */
84 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
86 #define IMX_I2C_REGSHIFT 2
87 #define VF610_I2C_REGSHIFT 0
89 /* Bits of IMX I2C registers */
90 #define I2SR_RXAK 0x01
95 #define I2SR_IAAS 0x40
97 #define I2CR_DMAEN 0x02
98 #define I2CR_RSTA 0x04
99 #define I2CR_TXAK 0x08
100 #define I2CR_MTX 0x10
101 #define I2CR_MSTA 0x20
102 #define I2CR_IIEN 0x40
103 #define I2CR_IEN 0x80
105 /* register bits different operating codes definition:
106 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
107 * - write zero to clear(w0c) INT flag on i.MX,
108 * - but write one to clear(w1c) INT flag on Vybrid.
109 * 2) I2CR: I2C module enable operation also differ between SoCs:
110 * - set I2CR_IEN bit enable the module on i.MX,
111 * - but clear I2CR_IEN bit enable the module on Vybrid.
113 #define I2SR_CLR_OPCODE_W0C 0x0
114 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
115 #define I2CR_IEN_OPCODE_0 0x0
116 #define I2CR_IEN_OPCODE_1 I2CR_IEN
118 #define I2C_PM_TIMEOUT 10 /* ms */
121 * sorted list of clock divider, register value pairs
122 * taken from table 26-5, p.26-9, Freescale i.MX
123 * Integrated Portable System Processor Reference Manual
124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
126 * Duplicated divider values removed from list
128 struct imx_i2c_clk_pair {
133 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
134 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
135 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
136 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
137 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
138 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
139 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
140 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
141 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
142 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
143 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
144 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
145 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
146 { 3072, 0x1E }, { 3840, 0x1F }
149 /* Vybrid VF610 clock divider, register value pairs */
150 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
151 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
152 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
153 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
154 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
155 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
156 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
157 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
158 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
159 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
160 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
161 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
162 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
163 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
164 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
165 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
174 struct imx_i2c_hwdata {
175 enum imx_i2c_type devtype;
177 struct imx_i2c_clk_pair *clk_div;
179 unsigned i2sr_clr_opcode;
180 unsigned i2cr_ien_opcode;
184 struct dma_chan *chan_tx;
185 struct dma_chan *chan_rx;
186 struct dma_chan *chan_using;
187 struct completion cmd_complete;
189 unsigned int dma_len;
190 enum dma_transfer_direction dma_transfer_dir;
191 enum dma_data_direction dma_data_dir;
194 struct imx_i2c_struct {
195 struct i2c_adapter adapter;
197 struct notifier_block clk_change_nb;
199 wait_queue_head_t queue;
201 unsigned int disable_delay;
203 unsigned int ifdr; /* IMX_I2C_IFDR */
204 unsigned int cur_clk;
205 unsigned int bitrate;
206 const struct imx_i2c_hwdata *hwdata;
207 struct i2c_bus_recovery_info rinfo;
209 struct pinctrl *pinctrl;
210 struct pinctrl_state *pinctrl_pins_default;
211 struct pinctrl_state *pinctrl_pins_gpio;
213 struct imx_i2c_dma *dma;
216 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
218 .regshift = IMX_I2C_REGSHIFT,
219 .clk_div = imx_i2c_clk_div,
220 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
221 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
222 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
226 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
227 .devtype = IMX21_I2C,
228 .regshift = IMX_I2C_REGSHIFT,
229 .clk_div = imx_i2c_clk_div,
230 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
231 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
232 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
236 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
237 .devtype = VF610_I2C,
238 .regshift = VF610_I2C_REGSHIFT,
239 .clk_div = vf610_i2c_clk_div,
240 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
241 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
242 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
246 static const struct platform_device_id imx_i2c_devtype[] = {
249 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
252 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
257 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
259 static const struct of_device_id i2c_imx_dt_ids[] = {
260 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
261 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
262 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
265 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
267 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
269 return i2c_imx->hwdata->devtype == IMX1_I2C;
272 static inline void imx_i2c_write_reg(unsigned int val,
273 struct imx_i2c_struct *i2c_imx, unsigned int reg)
275 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
278 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
281 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
284 /* Functions for DMA support */
285 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
288 struct imx_i2c_dma *dma;
289 struct dma_slave_config dma_sconfig;
290 struct device *dev = &i2c_imx->adapter.dev;
293 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
297 dma->chan_tx = dma_request_slave_channel(dev, "tx");
299 dev_dbg(dev, "can't request DMA tx channel\n");
303 dma_sconfig.dst_addr = phy_addr +
304 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
305 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
306 dma_sconfig.dst_maxburst = 1;
307 dma_sconfig.direction = DMA_MEM_TO_DEV;
308 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
310 dev_dbg(dev, "can't configure tx channel\n");
314 dma->chan_rx = dma_request_slave_channel(dev, "rx");
316 dev_dbg(dev, "can't request DMA rx channel\n");
320 dma_sconfig.src_addr = phy_addr +
321 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
322 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
323 dma_sconfig.src_maxburst = 1;
324 dma_sconfig.direction = DMA_DEV_TO_MEM;
325 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
327 dev_dbg(dev, "can't configure rx channel\n");
332 init_completion(&dma->cmd_complete);
333 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
334 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
339 dma_release_channel(dma->chan_rx);
341 dma_release_channel(dma->chan_tx);
343 devm_kfree(dev, dma);
344 dev_info(dev, "can't use DMA, using PIO instead.\n");
347 static void i2c_imx_dma_callback(void *arg)
349 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
350 struct imx_i2c_dma *dma = i2c_imx->dma;
352 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
353 dma->dma_len, dma->dma_data_dir);
354 complete(&dma->cmd_complete);
357 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
358 struct i2c_msg *msgs)
360 struct imx_i2c_dma *dma = i2c_imx->dma;
361 struct dma_async_tx_descriptor *txdesc;
362 struct device *dev = &i2c_imx->adapter.dev;
363 struct device *chan_dev = dma->chan_using->device->dev;
365 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
366 dma->dma_len, dma->dma_data_dir);
367 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
368 dev_err(dev, "DMA mapping failed\n");
372 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
373 dma->dma_len, dma->dma_transfer_dir,
374 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
376 dev_err(dev, "Not able to get desc for DMA xfer\n");
380 reinit_completion(&dma->cmd_complete);
381 txdesc->callback = i2c_imx_dma_callback;
382 txdesc->callback_param = i2c_imx;
383 if (dma_submit_error(dmaengine_submit(txdesc))) {
384 dev_err(dev, "DMA submit failed\n");
388 dma_async_issue_pending(dma->chan_using);
392 dmaengine_terminate_all(dma->chan_using);
394 dma_unmap_single(chan_dev, dma->dma_buf,
395 dma->dma_len, dma->dma_data_dir);
400 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
402 struct imx_i2c_dma *dma = i2c_imx->dma;
407 dma_release_channel(dma->chan_tx);
410 dma_release_channel(dma->chan_rx);
413 dma->chan_using = NULL;
416 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
421 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
422 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
423 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
425 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
426 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
429 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
431 unsigned long orig_jiffies = jiffies;
434 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
437 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
439 /* check for arbitration lost */
440 if (temp & I2SR_IAL) {
441 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
445 if (for_busy && (temp & I2SR_IBB))
447 if (!for_busy && !(temp & I2SR_IBB))
449 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
450 dev_dbg(&i2c_imx->adapter.dev,
451 "<%s> I2C bus is busy\n", __func__);
460 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
462 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
464 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
465 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
469 /* check for arbitration lost */
470 if (i2c_imx->i2csr & I2SR_IAL) {
471 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
472 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
478 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
483 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
485 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
486 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
487 return -ENXIO; /* No ACK */
490 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
494 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
495 unsigned int i2c_clk_rate)
497 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
501 /* Divider value calculation */
502 if (i2c_imx->cur_clk == i2c_clk_rate)
505 i2c_imx->cur_clk = i2c_clk_rate;
507 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
508 if (div < i2c_clk_div[0].div)
510 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
511 i = i2c_imx->hwdata->ndivs - 1;
513 for (i = 0; i2c_clk_div[i].div < div; i++)
516 /* Store divider value */
517 i2c_imx->ifdr = i2c_clk_div[i].val;
520 * There dummy delay is calculated.
521 * It should be about one I2C clock period long.
522 * This delay is used in I2C bus disable function
523 * to fix chip hardware bug.
525 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
526 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
528 #ifdef CONFIG_I2C_DEBUG_BUS
529 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
531 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
532 i2c_clk_div[i].val, i2c_clk_div[i].div);
536 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
537 unsigned long action, void *data)
539 struct clk_notifier_data *ndata = data;
540 struct imx_i2c_struct *i2c_imx = container_of(&ndata->clk,
541 struct imx_i2c_struct,
544 if (action & POST_RATE_CHANGE)
545 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
550 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
552 unsigned int temp = 0;
555 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
557 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
558 /* Enable I2C controller */
559 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
560 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
562 /* Wait controller to be stable */
563 usleep_range(50, 150);
565 /* Start I2C transaction */
566 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
568 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
569 result = i2c_imx_bus_busy(i2c_imx, 1);
572 i2c_imx->stopped = 0;
574 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
576 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
580 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
582 unsigned int temp = 0;
584 if (!i2c_imx->stopped) {
585 /* Stop I2C transaction */
586 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
587 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
588 temp &= ~(I2CR_MSTA | I2CR_MTX);
591 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
593 if (is_imx1_i2c(i2c_imx)) {
595 * This delay caused by an i.MXL hardware bug.
596 * If no (or too short) delay, no "STOP" bit will be generated.
598 udelay(i2c_imx->disable_delay);
601 if (!i2c_imx->stopped) {
602 i2c_imx_bus_busy(i2c_imx, 0);
603 i2c_imx->stopped = 1;
606 /* Disable I2C controller */
607 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
608 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
611 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
613 struct imx_i2c_struct *i2c_imx = dev_id;
616 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
617 if (temp & I2SR_IIF) {
618 /* save status register */
619 i2c_imx->i2csr = temp;
620 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
621 wake_up(&i2c_imx->queue);
628 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
629 struct i2c_msg *msgs)
632 unsigned long time_left;
633 unsigned int temp = 0;
634 unsigned long orig_jiffies = jiffies;
635 struct imx_i2c_dma *dma = i2c_imx->dma;
636 struct device *dev = &i2c_imx->adapter.dev;
638 dma->chan_using = dma->chan_tx;
639 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
640 dma->dma_data_dir = DMA_TO_DEVICE;
641 dma->dma_len = msgs->len - 1;
642 result = i2c_imx_dma_xfer(i2c_imx, msgs);
646 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
648 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
651 * Write slave address.
652 * The first byte must be transmitted by the CPU.
654 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
655 time_left = wait_for_completion_timeout(
656 &i2c_imx->dma->cmd_complete,
657 msecs_to_jiffies(DMA_TIMEOUT));
658 if (time_left == 0) {
659 dmaengine_terminate_all(dma->chan_using);
663 /* Waiting for transfer complete. */
665 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
668 if (time_after(jiffies, orig_jiffies +
669 msecs_to_jiffies(DMA_TIMEOUT))) {
670 dev_dbg(dev, "<%s> Timeout\n", __func__);
676 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
678 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
680 /* The last data byte must be transferred by the CPU. */
681 imx_i2c_write_reg(msgs->buf[msgs->len-1],
682 i2c_imx, IMX_I2C_I2DR);
683 result = i2c_imx_trx_complete(i2c_imx);
687 return i2c_imx_acked(i2c_imx);
690 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
691 struct i2c_msg *msgs, bool is_lastmsg)
694 unsigned long time_left;
696 unsigned long orig_jiffies = jiffies;
697 struct imx_i2c_dma *dma = i2c_imx->dma;
698 struct device *dev = &i2c_imx->adapter.dev;
701 dma->chan_using = dma->chan_rx;
702 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
703 dma->dma_data_dir = DMA_FROM_DEVICE;
704 /* The last two data bytes must be transferred by the CPU. */
705 dma->dma_len = msgs->len - 2;
706 result = i2c_imx_dma_xfer(i2c_imx, msgs);
710 time_left = wait_for_completion_timeout(
711 &i2c_imx->dma->cmd_complete,
712 msecs_to_jiffies(DMA_TIMEOUT));
713 if (time_left == 0) {
714 dmaengine_terminate_all(dma->chan_using);
718 /* waiting for transfer complete. */
720 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
723 if (time_after(jiffies, orig_jiffies +
724 msecs_to_jiffies(DMA_TIMEOUT))) {
725 dev_dbg(dev, "<%s> Timeout\n", __func__);
731 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
733 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
735 /* read n-1 byte data */
736 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
738 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
740 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
741 /* read n byte data */
742 result = i2c_imx_trx_complete(i2c_imx);
748 * It must generate STOP before read I2DR to prevent
749 * controller from generating another clock cycle
751 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
752 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
753 temp &= ~(I2CR_MSTA | I2CR_MTX);
754 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
755 i2c_imx_bus_busy(i2c_imx, 0);
756 i2c_imx->stopped = 1;
759 * For i2c master receiver repeat restart operation like:
760 * read -> repeat MSTA -> read/write
761 * The controller must set MTX before read the last byte in
762 * the first read operation, otherwise the first read cost
763 * one extra clock cycle.
765 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
767 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
769 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
774 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
778 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
779 __func__, msgs->addr << 1);
781 /* write slave address */
782 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
783 result = i2c_imx_trx_complete(i2c_imx);
786 result = i2c_imx_acked(i2c_imx);
789 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
792 for (i = 0; i < msgs->len; i++) {
793 dev_dbg(&i2c_imx->adapter.dev,
794 "<%s> write byte: B%d=0x%X\n",
795 __func__, i, msgs->buf[i]);
796 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
797 result = i2c_imx_trx_complete(i2c_imx);
800 result = i2c_imx_acked(i2c_imx);
807 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
811 int block_data = msgs->flags & I2C_M_RECV_LEN;
812 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
814 dev_dbg(&i2c_imx->adapter.dev,
815 "<%s> write slave address: addr=0x%x\n",
816 __func__, (msgs->addr << 1) | 0x01);
818 /* write slave address */
819 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
820 result = i2c_imx_trx_complete(i2c_imx);
823 result = i2c_imx_acked(i2c_imx);
827 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
829 /* setup bus to read data */
830 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
834 * Reset the I2CR_TXAK flag initially for SMBus block read since the
837 if ((msgs->len - 1) || block_data)
841 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
842 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
844 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
847 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
850 for (i = 0; i < msgs->len; i++) {
853 result = i2c_imx_trx_complete(i2c_imx);
857 * First byte is the length of remaining packet
858 * in the SMBus block data read. Add it to
861 if ((!i) && block_data) {
862 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
863 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
865 dev_dbg(&i2c_imx->adapter.dev,
866 "<%s> read length: 0x%X\n",
870 if (i == (msgs->len - 1)) {
873 * It must generate STOP before read I2DR to prevent
874 * controller from generating another clock cycle
876 dev_dbg(&i2c_imx->adapter.dev,
877 "<%s> clear MSTA\n", __func__);
878 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
879 temp &= ~(I2CR_MSTA | I2CR_MTX);
880 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
881 i2c_imx_bus_busy(i2c_imx, 0);
882 i2c_imx->stopped = 1;
885 * For i2c master receiver repeat restart operation like:
886 * read -> repeat MSTA -> read/write
887 * The controller must set MTX before read the last byte in
888 * the first read operation, otherwise the first read cost
889 * one extra clock cycle.
891 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
893 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
895 } else if (i == (msgs->len - 2)) {
896 dev_dbg(&i2c_imx->adapter.dev,
897 "<%s> set TXAK\n", __func__);
898 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
900 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
902 if ((!i) && block_data)
905 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
906 dev_dbg(&i2c_imx->adapter.dev,
907 "<%s> read byte: B%d=0x%X\n",
908 __func__, i, msgs->buf[i]);
913 static int i2c_imx_xfer(struct i2c_adapter *adapter,
914 struct i2c_msg *msgs, int num)
916 unsigned int i, temp;
918 bool is_lastmsg = false;
919 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
921 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
923 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
927 /* Start I2C transfer */
928 result = i2c_imx_start(i2c_imx);
930 if (i2c_imx->adapter.bus_recovery_info) {
931 i2c_recover_bus(&i2c_imx->adapter);
932 result = i2c_imx_start(i2c_imx);
939 /* read/write data */
940 for (i = 0; i < num; i++) {
945 dev_dbg(&i2c_imx->adapter.dev,
946 "<%s> repeated start\n", __func__);
947 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
949 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
950 result = i2c_imx_bus_busy(i2c_imx, 1);
954 dev_dbg(&i2c_imx->adapter.dev,
955 "<%s> transfer message: %d\n", __func__, i);
956 /* write/read data */
957 #ifdef CONFIG_I2C_DEBUG_BUS
958 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
959 dev_dbg(&i2c_imx->adapter.dev,
960 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
962 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
963 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
964 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
965 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
966 dev_dbg(&i2c_imx->adapter.dev,
967 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
969 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
970 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
971 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
972 (temp & I2SR_RXAK ? 1 : 0));
974 if (msgs[i].flags & I2C_M_RD)
975 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
977 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
978 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
980 result = i2c_imx_write(i2c_imx, &msgs[i]);
987 /* Stop I2C transfer */
988 i2c_imx_stop(i2c_imx);
990 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
991 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
994 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
995 (result < 0) ? "error" : "success msg",
996 (result < 0) ? result : num);
997 return (result < 0) ? result : num;
1000 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1002 struct imx_i2c_struct *i2c_imx;
1004 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1006 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1009 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1011 struct imx_i2c_struct *i2c_imx;
1013 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1015 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1019 * We switch SCL and SDA to their GPIO function and do some bitbanging
1020 * for bus recovery. These alternative pinmux settings can be
1021 * described in the device tree by a separate pinctrl state "gpio". If
1022 * this is missing this is not a big problem, the only implication is
1023 * that we can't do bus recovery.
1025 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1026 struct platform_device *pdev)
1028 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1030 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1031 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1032 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1033 return PTR_ERR(i2c_imx->pinctrl);
1036 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1037 PINCTRL_STATE_DEFAULT);
1038 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1040 rinfo->sda_gpio = of_get_named_gpio(pdev->dev.of_node, "sda-gpios", 0);
1041 rinfo->scl_gpio = of_get_named_gpio(pdev->dev.of_node, "scl-gpios", 0);
1043 if (rinfo->sda_gpio == -EPROBE_DEFER ||
1044 rinfo->scl_gpio == -EPROBE_DEFER) {
1045 return -EPROBE_DEFER;
1046 } else if (!gpio_is_valid(rinfo->sda_gpio) ||
1047 !gpio_is_valid(rinfo->scl_gpio) ||
1048 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1049 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1050 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1054 dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n",
1055 rinfo->scl_gpio, rinfo->sda_gpio);
1057 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1058 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1059 rinfo->recover_bus = i2c_generic_gpio_recovery;
1060 i2c_imx->adapter.bus_recovery_info = rinfo;
1065 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1067 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1068 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1071 static const struct i2c_algorithm i2c_imx_algo = {
1072 .master_xfer = i2c_imx_xfer,
1073 .functionality = i2c_imx_func,
1076 static int i2c_imx_probe(struct platform_device *pdev)
1078 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1080 struct imx_i2c_struct *i2c_imx;
1081 struct resource *res;
1082 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1085 dma_addr_t phy_addr;
1087 dev_dbg(&pdev->dev, "<%s>\n", __func__);
1089 irq = platform_get_irq(pdev, 0);
1091 dev_err(&pdev->dev, "can't get irq number\n");
1095 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1096 base = devm_ioremap_resource(&pdev->dev, res);
1098 return PTR_ERR(base);
1100 phy_addr = (dma_addr_t)res->start;
1101 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1106 i2c_imx->hwdata = of_id->data;
1108 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1109 platform_get_device_id(pdev)->driver_data;
1111 /* Setup i2c_imx driver structure */
1112 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1113 i2c_imx->adapter.owner = THIS_MODULE;
1114 i2c_imx->adapter.algo = &i2c_imx_algo;
1115 i2c_imx->adapter.dev.parent = &pdev->dev;
1116 i2c_imx->adapter.nr = pdev->id;
1117 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1118 i2c_imx->base = base;
1121 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1122 if (IS_ERR(i2c_imx->clk)) {
1123 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1124 dev_err(&pdev->dev, "can't get I2C clock\n");
1125 return PTR_ERR(i2c_imx->clk);
1128 ret = clk_prepare_enable(i2c_imx->clk);
1130 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1135 init_waitqueue_head(&i2c_imx->queue);
1137 /* Set up adapter data */
1138 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1140 /* Set up platform driver data */
1141 platform_set_drvdata(pdev, i2c_imx);
1143 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1144 pm_runtime_use_autosuspend(&pdev->dev);
1145 pm_runtime_set_active(&pdev->dev);
1146 pm_runtime_enable(&pdev->dev);
1148 ret = pm_runtime_get_sync(&pdev->dev);
1153 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
1154 pdev->name, i2c_imx);
1156 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1160 /* Set up clock divider */
1161 i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1162 ret = of_property_read_u32(pdev->dev.of_node,
1163 "clock-frequency", &i2c_imx->bitrate);
1164 if (ret < 0 && pdata && pdata->bitrate)
1165 i2c_imx->bitrate = pdata->bitrate;
1166 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1167 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1168 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1170 /* Set up chip registers to defaults */
1171 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1172 i2c_imx, IMX_I2C_I2CR);
1173 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1175 /* Init optional bus recovery function */
1176 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1177 /* Give it another chance if pinctrl used is not ready yet */
1178 if (ret == -EPROBE_DEFER)
1179 goto clk_notifier_unregister;
1181 /* Add I2C adapter */
1182 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1184 goto clk_notifier_unregister;
1186 pm_runtime_mark_last_busy(&pdev->dev);
1187 pm_runtime_put_autosuspend(&pdev->dev);
1189 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1190 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1191 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1192 i2c_imx->adapter.name);
1193 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1195 /* Init DMA config if supported */
1196 i2c_imx_dma_request(i2c_imx, phy_addr);
1198 return 0; /* Return OK */
1200 clk_notifier_unregister:
1201 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1202 free_irq(irq, i2c_imx);
1204 pm_runtime_put_noidle(&pdev->dev);
1205 pm_runtime_disable(&pdev->dev);
1206 pm_runtime_set_suspended(&pdev->dev);
1207 pm_runtime_dont_use_autosuspend(&pdev->dev);
1208 clk_disable_unprepare(i2c_imx->clk);
1212 static int i2c_imx_remove(struct platform_device *pdev)
1214 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1217 ret = pm_runtime_get_sync(&pdev->dev);
1221 /* remove adapter */
1222 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1223 i2c_del_adapter(&i2c_imx->adapter);
1226 i2c_imx_dma_free(i2c_imx);
1228 /* setup chip registers to defaults */
1229 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1230 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1231 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1232 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1234 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1235 irq = platform_get_irq(pdev, 0);
1237 free_irq(irq, i2c_imx);
1238 clk_disable_unprepare(i2c_imx->clk);
1240 pm_runtime_put_noidle(&pdev->dev);
1241 pm_runtime_disable(&pdev->dev);
1247 static int i2c_imx_runtime_suspend(struct device *dev)
1249 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1251 clk_disable_unprepare(i2c_imx->clk);
1256 static int i2c_imx_runtime_resume(struct device *dev)
1258 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1261 ret = clk_prepare_enable(i2c_imx->clk);
1263 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1268 static const struct dev_pm_ops i2c_imx_pm_ops = {
1269 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1270 i2c_imx_runtime_resume, NULL)
1272 #define I2C_IMX_PM_OPS (&i2c_imx_pm_ops)
1274 #define I2C_IMX_PM_OPS NULL
1275 #endif /* CONFIG_PM */
1277 static struct platform_driver i2c_imx_driver = {
1278 .probe = i2c_imx_probe,
1279 .remove = i2c_imx_remove,
1281 .name = DRIVER_NAME,
1282 .pm = I2C_IMX_PM_OPS,
1283 .of_match_table = i2c_imx_dt_ids,
1285 .id_table = imx_i2c_devtype,
1288 static int __init i2c_adap_imx_init(void)
1290 return platform_driver_register(&i2c_imx_driver);
1292 subsys_initcall(i2c_adap_imx_init);
1294 static void __exit i2c_adap_imx_exit(void)
1296 platform_driver_unregister(&i2c_imx_driver);
1298 module_exit(i2c_adap_imx_exit);
1300 MODULE_LICENSE("GPL");
1301 MODULE_AUTHOR("Darius Augulis");
1302 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1303 MODULE_ALIAS("platform:" DRIVER_NAME);