drivers/i2c/busses/i2c-imx.c

   1 /*
   2  *      Copyright (C) 2002 Motorola GSG-China
   3  *
   4  *      This program is free software; you can redistribute it and/or
   5  *      modify it under the terms of the GNU General Public License
   6  *      as published by the Free Software Foundation; either version 2
   7  *      of the License, or (at your option) any later version.
   8  *
   9  *      This program is distributed in the hope that it will be useful,
  10  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *      GNU General Public License for more details.
  13  *
  14  * Author:
  15  *      Darius Augulis, Teltonika Inc.
  16  *
  17  * Desc.:
  18  *      Implementation of I2C Adapter/Algorithm Driver
  19  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  20  *
  21  *      Derived from Motorola GSG China I2C example driver
  22  *
  23  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  24  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  25  *      Copyright (C) 2007 RightHand Technologies, Inc.
  26  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  27  *
  28  *      Copyright 2013 Freescale Semiconductor, Inc.
  29  *
  30  */
  31
  32 /** Includes *******************************************************************
  33 *******************************************************************************/
  34
  35 #include <linux/clk.h>
  36 #include <linux/completion.h>
  37 #include <linux/delay.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmaengine.h>
  40 #include <linux/dmapool.h>
  41 #include <linux/err.h>
  42 #include <linux/errno.h>
  43 #include <linux/i2c.h>
  44 #include <linux/init.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/kernel.h>
  48 #include <linux/module.h>
  49 #include <linux/of.h>
  50 #include <linux/of_device.h>
  51 #include <linux/of_dma.h>
  52 #include <linux/of_gpio.h>
  53 #include <linux/pinctrl/consumer.h>
  54 #include <linux/platform_data/i2c-imx.h>
  55 #include <linux/platform_device.h>
  56 #include <linux/sched.h>
  57 #include <linux/slab.h>
  58
  59 /** Defines ********************************************************************
  60 *******************************************************************************/
  61
  62 /* This will be the driver name the kernel reports */
  63 #define DRIVER_NAME "imx-i2c"
  64
  65 /* Default value */
  66 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
  67
  68 /*
  69  * Enable DMA if transfer byte size is bigger than this threshold.
  70  * As the hardware request, it must bigger than 4 bytes.\
  71  * I have set '16' here, maybe it's not the best but I think it's
  72  * the appropriate.
  73  */
  74 #define DMA_THRESHOLD   16
  75 #define DMA_TIMEOUT     1000
  76
  77 /* IMX I2C registers:
  78  * the I2C register offset is different between SoCs,
  79  * to provid support for all these chips, split the
  80  * register offset into a fixed base address and a
  81  * variable shift value, then the full register offset
  82  * will be calculated by
  83  * reg_off = ( reg_base_addr << reg_shift)
  84  */
  85 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  86 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  87 #define IMX_I2C_I2CR    0x02    /* i2c control */
  88 #define IMX_I2C_I2SR    0x03    /* i2c status */
  89 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  90
  91 #define IMX_I2C_REGSHIFT        2
  92 #define VF610_I2C_REGSHIFT      0
  93
  94 /* Bits of IMX I2C registers */
  95 #define I2SR_RXAK       0x01
  96 #define I2SR_IIF        0x02
  97 #define I2SR_SRW        0x04
  98 #define I2SR_IAL        0x10
  99 #define I2SR_IBB        0x20
 100 #define I2SR_IAAS       0x40
 101 #define I2SR_ICF        0x80
 102 #define I2CR_DMAEN      0x02
 103 #define I2CR_RSTA       0x04
 104 #define I2CR_TXAK       0x08
 105 #define I2CR_MTX        0x10
 106 #define I2CR_MSTA       0x20
 107 #define I2CR_IIEN       0x40
 108 #define I2CR_IEN        0x80
 109
 110 /* register bits different operating codes definition:
 111  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
 112  * - write zero to clear(w0c) INT flag on i.MX,
 113  * - but write one to clear(w1c) INT flag on Vybrid.
 114  * 2) I2CR: I2C module enable operation also differ between SoCs:
 115  * - set I2CR_IEN bit enable the module on i.MX,
 116  * - but clear I2CR_IEN bit enable the module on Vybrid.
 117  */
 118 #define I2SR_CLR_OPCODE_W0C     0x0
 119 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 120 #define I2CR_IEN_OPCODE_0       0x0
 121 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 122
 123 /** Variables ******************************************************************
 124 *******************************************************************************/
 125
 126 /*
 127  * sorted list of clock divider, register value pairs
 128  * taken from table 26-5, p.26-9, Freescale i.MX
 129  * Integrated Portable System Processor Reference Manual
 130  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 131  *
 132  * Duplicated divider values removed from list
 133  */
 134 struct imx_i2c_clk_pair {
 135         u16     div;
 136         u16     val;
 137 };
 138
 139 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 140         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 141         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 142         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 143         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 144         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 145         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 146         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 147         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 148         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 149         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 150         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 151         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 152         { 3072, 0x1E }, { 3840, 0x1F }
 153 };
 154
 155 /* Vybrid VF610 clock divider, register value pairs */
 156 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 157         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 158         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 159         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 160         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 161         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 162         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 163         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 164         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 165         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 166         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 167         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 168         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 169         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 170         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 171         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 172 };
 173
 174 enum imx_i2c_type {
 175         IMX1_I2C,
 176         IMX21_I2C,
 177         VF610_I2C,
 178 };
 179
 180 struct imx_i2c_hwdata {
 181         enum imx_i2c_type       devtype;
 182         unsigned                regshift;
 183         struct imx_i2c_clk_pair *clk_div;
 184         unsigned                ndivs;
 185         unsigned                i2sr_clr_opcode;
 186         unsigned                i2cr_ien_opcode;
 187 };
 188
 189 struct imx_i2c_dma {
 190         struct dma_chan         *chan_tx;
 191         struct dma_chan         *chan_rx;
 192         struct dma_chan         *chan_using;
 193         struct completion       cmd_complete;
 194         dma_addr_t              dma_buf;
 195         unsigned int            dma_len;
 196         enum dma_transfer_direction dma_transfer_dir;
 197         enum dma_data_direction dma_data_dir;
 198 };
 199
 200 struct imx_i2c_struct {
 201         struct i2c_adapter      adapter;
 202         struct clk              *clk;
 203         void __iomem            *base;
 204         wait_queue_head_t       queue;
 205         unsigned long           i2csr;
 206         unsigned int            disable_delay;
 207         int                     stopped;
 208         unsigned int            ifdr; /* IMX_I2C_IFDR */
 209         unsigned int            cur_clk;
 210         unsigned int            bitrate;
 211         const struct imx_i2c_hwdata     *hwdata;
 212         struct i2c_bus_recovery_info rinfo;
 213
 214         struct pinctrl *pinctrl;
 215         struct pinctrl_state *pinctrl_pins_default;
 216         struct pinctrl_state *pinctrl_pins_gpio;
 217
 218         struct imx_i2c_dma      *dma;
 219 };
 220
 221 static const struct imx_i2c_hwdata imx1_i2c_hwdata  = {
 222         .devtype                = IMX1_I2C,
 223         .regshift               = IMX_I2C_REGSHIFT,
 224         .clk_div                = imx_i2c_clk_div,
 225         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 226         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 227         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 228
 229 };
 230
 231 static const struct imx_i2c_hwdata imx21_i2c_hwdata  = {
 232         .devtype                = IMX21_I2C,
 233         .regshift               = IMX_I2C_REGSHIFT,
 234         .clk_div                = imx_i2c_clk_div,
 235         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 236         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 237         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 238
 239 };
 240
 241 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 242         .devtype                = VF610_I2C,
 243         .regshift               = VF610_I2C_REGSHIFT,
 244         .clk_div                = vf610_i2c_clk_div,
 245         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 246         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 247         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 248
 249 };
 250
 251 static const struct platform_device_id imx_i2c_devtype[] = {
 252         {
 253                 .name = "imx1-i2c",
 254                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 255         }, {
 256                 .name = "imx21-i2c",
 257                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 258         }, {
 259                 /* sentinel */
 260         }
 261 };
 262 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 263
 264 static const struct of_device_id i2c_imx_dt_ids[] = {
 265         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 266         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 267         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 268         { /* sentinel */ }
 269 };
 270 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 271
 272 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 273 {
 274         return i2c_imx->hwdata->devtype == IMX1_I2C;
 275 }
 276
 277 static inline void imx_i2c_write_reg(unsigned int val,
 278                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 279 {
 280         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 281 }
 282
 283 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 284                 unsigned int reg)
 285 {
 286         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 287 }
 288
 289 /* Functions for DMA support */
 290 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 291                                                 dma_addr_t phy_addr)
 292 {
 293         struct imx_i2c_dma *dma;
 294         struct dma_slave_config dma_sconfig;
 295         struct device *dev = &i2c_imx->adapter.dev;
 296         int ret;
 297
 298         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 299         if (!dma)
 300                 return;
 301
 302         dma->chan_tx = dma_request_slave_channel(dev, "tx");
 303         if (!dma->chan_tx) {
 304                 dev_dbg(dev, "can't request DMA tx channel\n");
 305                 goto fail_al;
 306         }
 307
 308         dma_sconfig.dst_addr = phy_addr +
 309                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 310         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 311         dma_sconfig.dst_maxburst = 1;
 312         dma_sconfig.direction = DMA_MEM_TO_DEV;
 313         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 314         if (ret < 0) {
 315                 dev_dbg(dev, "can't configure tx channel\n");
 316                 goto fail_tx;
 317         }
 318
 319         dma->chan_rx = dma_request_slave_channel(dev, "rx");
 320         if (!dma->chan_rx) {
 321                 dev_dbg(dev, "can't request DMA rx channel\n");
 322                 goto fail_tx;
 323         }
 324
 325         dma_sconfig.src_addr = phy_addr +
 326                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 327         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 328         dma_sconfig.src_maxburst = 1;
 329         dma_sconfig.direction = DMA_DEV_TO_MEM;
 330         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 331         if (ret < 0) {
 332                 dev_dbg(dev, "can't configure rx channel\n");
 333                 goto fail_rx;
 334         }
 335
 336         i2c_imx->dma = dma;
 337         init_completion(&dma->cmd_complete);
 338         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 339                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 340
 341         return;
 342
 343 fail_rx:
 344         dma_release_channel(dma->chan_rx);
 345 fail_tx:
 346         dma_release_channel(dma->chan_tx);
 347 fail_al:
 348         devm_kfree(dev, dma);
 349         dev_info(dev, "can't use DMA\n");
 350 }
 351
 352 static void i2c_imx_dma_callback(void *arg)
 353 {
 354         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 355         struct imx_i2c_dma *dma = i2c_imx->dma;
 356
 357         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 358                         dma->dma_len, dma->dma_data_dir);
 359         complete(&dma->cmd_complete);
 360 }
 361
 362 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 363                                         struct i2c_msg *msgs)
 364 {
 365         struct imx_i2c_dma *dma = i2c_imx->dma;
 366         struct dma_async_tx_descriptor *txdesc;
 367         struct device *dev = &i2c_imx->adapter.dev;
 368         struct device *chan_dev = dma->chan_using->device->dev;
 369
 370         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 371                                         dma->dma_len, dma->dma_data_dir);
 372         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 373                 dev_err(dev, "DMA mapping failed\n");
 374                 goto err_map;
 375         }
 376
 377         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 378                                         dma->dma_len, dma->dma_transfer_dir,
 379                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 380         if (!txdesc) {
 381                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 382                 goto err_desc;
 383         }
 384
 385         reinit_completion(&dma->cmd_complete);
 386         txdesc->callback = i2c_imx_dma_callback;
 387         txdesc->callback_param = i2c_imx;
 388         if (dma_submit_error(dmaengine_submit(txdesc))) {
 389                 dev_err(dev, "DMA submit failed\n");
 390                 goto err_submit;
 391         }
 392
 393         dma_async_issue_pending(dma->chan_using);
 394         return 0;
 395
 396 err_submit:
 397 err_desc:
 398         dma_unmap_single(chan_dev, dma->dma_buf,
 399                         dma->dma_len, dma->dma_data_dir);
 400 err_map:
 401         return -EINVAL;
 402 }
 403
 404 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 405 {
 406         struct imx_i2c_dma *dma = i2c_imx->dma;
 407
 408         dma->dma_buf = 0;
 409         dma->dma_len = 0;
 410
 411         dma_release_channel(dma->chan_tx);
 412         dma->chan_tx = NULL;
 413
 414         dma_release_channel(dma->chan_rx);
 415         dma->chan_rx = NULL;
 416
 417         dma->chan_using = NULL;
 418 }
 419
 420 /** Functions for IMX I2C adapter driver ***************************************
 421 *******************************************************************************/
 422
 423 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
 424 {
 425         unsigned int temp;
 426
 427         /*
 428          * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
 429          * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
 430          * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
 431          */
 432         temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
 433         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 434 }
 435
 436 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
 437 {
 438         unsigned long orig_jiffies = jiffies;
 439         unsigned int temp;
 440
 441         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 442
 443         while (1) {
 444                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 445
 446                 /* check for arbitration lost */
 447                 if (temp & I2SR_IAL) {
 448                         i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 449                         return -EAGAIN;
 450                 }
 451
 452                 if (for_busy && (temp & I2SR_IBB))
 453                         break;
 454                 if (!for_busy && !(temp & I2SR_IBB))
 455                         break;
 456                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 457                         dev_dbg(&i2c_imx->adapter.dev,
 458                                 "<%s> I2C bus is busy\n", __func__);
 459                         return -ETIMEDOUT;
 460                 }
 461                 schedule();
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
 468 {
 469         wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 470
 471         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 472                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 473                 return -ETIMEDOUT;
 474         }
 475
 476         /* check for arbitration lost */
 477         if (i2c_imx->i2csr & I2SR_IAL) {
 478                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
 479                 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 480
 481                 i2c_imx->i2csr = 0;
 482                 return -EAGAIN;
 483         }
 484
 485         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 486         i2c_imx->i2csr = 0;
 487         return 0;
 488 }
 489
 490 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 491 {
 492         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 493                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 494                 return -ENXIO;  /* No ACK */
 495         }
 496
 497         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 498         return 0;
 499 }
 500
 501 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
 502 {
 503         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 504         unsigned int i2c_clk_rate;
 505         unsigned int div;
 506         int i;
 507
 508         /* Divider value calculation */
 509         i2c_clk_rate = clk_get_rate(i2c_imx->clk);
 510         if (i2c_imx->cur_clk == i2c_clk_rate)
 511                 return;
 512
 513         i2c_imx->cur_clk = i2c_clk_rate;
 514
 515         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 516         if (div < i2c_clk_div[0].div)
 517                 i = 0;
 518         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 519                 i = i2c_imx->hwdata->ndivs - 1;
 520         else
 521                 for (i = 0; i2c_clk_div[i].div < div; i++)
 522                         ;
 523
 524         /* Store divider value */
 525         i2c_imx->ifdr = i2c_clk_div[i].val;
 526
 527         /*
 528          * There dummy delay is calculated.
 529          * It should be about one I2C clock period long.
 530          * This delay is used in I2C bus disable function
 531          * to fix chip hardware bug.
 532          */
 533         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 534                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 535
 536 #ifdef CONFIG_I2C_DEBUG_BUS
 537         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 538                 i2c_clk_rate, div);
 539         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 540                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 541 #endif
 542 }
 543
 544 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
 545 {
 546         unsigned int temp = 0;
 547         int result;
 548
 549         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 550
 551         i2c_imx_set_clk(i2c_imx);
 552
 553         result = clk_prepare_enable(i2c_imx->clk);
 554         if (result)
 555                 return result;
 556         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 557         /* Enable I2C controller */
 558         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 559         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 560
 561         /* Wait controller to be stable */
 562         udelay(50);
 563
 564         /* Start I2C transaction */
 565         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 566         temp |= I2CR_MSTA;
 567         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 568         result = i2c_imx_bus_busy(i2c_imx, 1);
 569         if (result)
 570                 return result;
 571         i2c_imx->stopped = 0;
 572
 573         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 574         temp &= ~I2CR_DMAEN;
 575         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 576         return result;
 577 }
 578
 579 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
 580 {
 581         unsigned int temp = 0;
 582
 583         if (!i2c_imx->stopped) {
 584                 /* Stop I2C transaction */
 585                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 586                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 587                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 588                 if (i2c_imx->dma)
 589                         temp &= ~I2CR_DMAEN;
 590                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 591         }
 592         if (is_imx1_i2c(i2c_imx)) {
 593                 /*
 594                  * This delay caused by an i.MXL hardware bug.
 595                  * If no (or too short) delay, no "STOP" bit will be generated.
 596                  */
 597                 udelay(i2c_imx->disable_delay);
 598         }
 599
 600         if (!i2c_imx->stopped) {
 601                 i2c_imx_bus_busy(i2c_imx, 0);
 602                 i2c_imx->stopped = 1;
 603         }
 604
 605         /* Disable I2C controller */
 606         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 607         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 608         clk_disable_unprepare(i2c_imx->clk);
 609 }
 610
 611 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 612 {
 613         struct imx_i2c_struct *i2c_imx = dev_id;
 614         unsigned int temp;
 615
 616         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 617         if (temp & I2SR_IIF) {
 618                 /* save status register */
 619                 i2c_imx->i2csr = temp;
 620                 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
 621                 wake_up(&i2c_imx->queue);
 622                 return IRQ_HANDLED;
 623         }
 624
 625         return IRQ_NONE;
 626 }
 627
 628 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 629                                         struct i2c_msg *msgs)
 630 {
 631         int result;
 632         unsigned long time_left;
 633         unsigned int temp = 0;
 634         unsigned long orig_jiffies = jiffies;
 635         struct imx_i2c_dma *dma = i2c_imx->dma;
 636         struct device *dev = &i2c_imx->adapter.dev;
 637
 638         dma->chan_using = dma->chan_tx;
 639         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 640         dma->dma_data_dir = DMA_TO_DEVICE;
 641         dma->dma_len = msgs->len - 1;
 642         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 643         if (result)
 644                 return result;
 645
 646         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 647         temp |= I2CR_DMAEN;
 648         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 649
 650         /*
 651          * Write slave address.
 652          * The first byte must be transmitted by the CPU.
 653          */
 654         imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
 655         time_left = wait_for_completion_timeout(
 656                                 &i2c_imx->dma->cmd_complete,
 657                                 msecs_to_jiffies(DMA_TIMEOUT));
 658         if (time_left == 0) {
 659                 dmaengine_terminate_all(dma->chan_using);
 660                 return -ETIMEDOUT;
 661         }
 662
 663         /* Waiting for transfer complete. */
 664         while (1) {
 665                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 666                 if (temp & I2SR_ICF)
 667                         break;
 668                 if (time_after(jiffies, orig_jiffies +
 669                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 670                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 671                         return -ETIMEDOUT;
 672                 }
 673                 schedule();
 674         }
 675
 676         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 677         temp &= ~I2CR_DMAEN;
 678         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 679
 680         /* The last data byte must be transferred by the CPU. */
 681         imx_i2c_write_reg(msgs->buf[msgs->len-1],
 682                                 i2c_imx, IMX_I2C_I2DR);
 683         result = i2c_imx_trx_complete(i2c_imx);
 684         if (result)
 685                 return result;
 686
 687         return i2c_imx_acked(i2c_imx);
 688 }
 689
 690 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 691                         struct i2c_msg *msgs, bool is_lastmsg)
 692 {
 693         int result;
 694         unsigned long time_left;
 695         unsigned int temp;
 696         unsigned long orig_jiffies = jiffies;
 697         struct imx_i2c_dma *dma = i2c_imx->dma;
 698         struct device *dev = &i2c_imx->adapter.dev;
 699
 700
 701         dma->chan_using = dma->chan_rx;
 702         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 703         dma->dma_data_dir = DMA_FROM_DEVICE;
 704         /* The last two data bytes must be transferred by the CPU. */
 705         dma->dma_len = msgs->len - 2;
 706         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 707         if (result)
 708                 return result;
 709
 710         time_left = wait_for_completion_timeout(
 711                                 &i2c_imx->dma->cmd_complete,
 712                                 msecs_to_jiffies(DMA_TIMEOUT));
 713         if (time_left == 0) {
 714                 dmaengine_terminate_all(dma->chan_using);
 715                 return -ETIMEDOUT;
 716         }
 717
 718         /* waiting for transfer complete. */
 719         while (1) {
 720                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 721                 if (temp & I2SR_ICF)
 722                         break;
 723                 if (time_after(jiffies, orig_jiffies +
 724                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 725                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 726                         return -ETIMEDOUT;
 727                 }
 728                 schedule();
 729         }
 730
 731         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 732         temp &= ~I2CR_DMAEN;
 733         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 734
 735         /* read n-1 byte data */
 736         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 737         temp |= I2CR_TXAK;
 738         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 739
 740         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 741         /* read n byte data */
 742         result = i2c_imx_trx_complete(i2c_imx);
 743         if (result)
 744                 return result;
 745
 746         if (is_lastmsg) {
 747                 /*
 748                  * It must generate STOP before read I2DR to prevent
 749                  * controller from generating another clock cycle
 750                  */
 751                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 752                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 753                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 754                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 755                 i2c_imx_bus_busy(i2c_imx, 0);
 756                 i2c_imx->stopped = 1;
 757         } else {
 758                 /*
 759                  * For i2c master receiver repeat restart operation like:
 760                  * read -> repeat MSTA -> read/write
 761                  * The controller must set MTX before read the last byte in
 762                  * the first read operation, otherwise the first read cost
 763                  * one extra clock cycle.
 764                  */
 765                 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
 766                 temp |= I2CR_MTX;
 767                 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
 768         }
 769         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 770
 771         return 0;
 772 }
 773
 774 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
 775 {
 776         int i, result;
 777
 778         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 779                 __func__, msgs->addr << 1);
 780
 781         /* write slave address */
 782         imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
 783         result = i2c_imx_trx_complete(i2c_imx);
 784         if (result)
 785                 return result;
 786         result = i2c_imx_acked(i2c_imx);
 787         if (result)
 788                 return result;
 789         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 790
 791         /* write data */
 792         for (i = 0; i < msgs->len; i++) {
 793                 dev_dbg(&i2c_imx->adapter.dev,
 794                         "<%s> write byte: B%d=0x%X\n",
 795                         __func__, i, msgs->buf[i]);
 796                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 797                 result = i2c_imx_trx_complete(i2c_imx);
 798                 if (result)
 799                         return result;
 800                 result = i2c_imx_acked(i2c_imx);
 801                 if (result)
 802                         return result;
 803         }
 804         return 0;
 805 }
 806
 807 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
 808 {
 809         int i, result;
 810         unsigned int temp;
 811         int block_data = msgs->flags & I2C_M_RECV_LEN;
 812         int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
 813
 814         dev_dbg(&i2c_imx->adapter.dev,
 815                 "<%s> write slave address: addr=0x%x\n",
 816                 __func__, (msgs->addr << 1) | 0x01);
 817
 818         /* write slave address */
 819         imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
 820         result = i2c_imx_trx_complete(i2c_imx);
 821         if (result)
 822                 return result;
 823         result = i2c_imx_acked(i2c_imx);
 824         if (result)
 825                 return result;
 826
 827         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 828
 829         /* setup bus to read data */
 830         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 831         temp &= ~I2CR_MTX;
 832
 833         /*
 834          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 835          * length is unknown
 836          */
 837         if ((msgs->len - 1) || block_data)
 838                 temp &= ~I2CR_TXAK;
 839         if (use_dma)
 840                 temp |= I2CR_DMAEN;
 841         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 842         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 843
 844         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 845
 846         if (use_dma)
 847                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 848
 849         /* read data */
 850         for (i = 0; i < msgs->len; i++) {
 851                 u8 len = 0;
 852
 853                 result = i2c_imx_trx_complete(i2c_imx);
 854                 if (result)
 855                         return result;
 856                 /*
 857                  * First byte is the length of remaining packet
 858                  * in the SMBus block data read. Add it to
 859                  * msgs->len.
 860                  */
 861                 if ((!i) && block_data) {
 862                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 863                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 864                                 return -EPROTO;
 865                         dev_dbg(&i2c_imx->adapter.dev,
 866                                 "<%s> read length: 0x%X\n",
 867                                 __func__, len);
 868                         msgs->len += len;
 869                 }
 870                 if (i == (msgs->len - 1)) {
 871                         if (is_lastmsg) {
 872                                 /*
 873                                  * It must generate STOP before read I2DR to prevent
 874                                  * controller from generating another clock cycle
 875                                  */
 876                                 dev_dbg(&i2c_imx->adapter.dev,
 877                                         "<%s> clear MSTA\n", __func__);
 878                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 879                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 880                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 881                                 i2c_imx_bus_busy(i2c_imx, 0);
 882                                 i2c_imx->stopped = 1;
 883                         } else {
 884                                 /*
 885                                  * For i2c master receiver repeat restart operation like:
 886                                  * read -> repeat MSTA -> read/write
 887                                  * The controller must set MTX before read the last byte in
 888                                  * the first read operation, otherwise the first read cost
 889                                  * one extra clock cycle.
 890                                  */
 891                                 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
 892                                 temp |= I2CR_MTX;
 893                                 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
 894                         }
 895                 } else if (i == (msgs->len - 2)) {
 896                         dev_dbg(&i2c_imx->adapter.dev,
 897                                 "<%s> set TXAK\n", __func__);
 898                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 899                         temp |= I2CR_TXAK;
 900                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 901                 }
 902                 if ((!i) && block_data)
 903                         msgs->buf[0] = len;
 904                 else
 905                         msgs->buf[i] =  imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 906                 dev_dbg(&i2c_imx->adapter.dev,
 907                         "<%s> read byte: B%d=0x%X\n",
 908                         __func__, i, msgs->buf[i]);
 909         }
 910         return 0;
 911 }
 912
 913 static int i2c_imx_xfer(struct i2c_adapter *adapter,
 914                                                 struct i2c_msg *msgs, int num)
 915 {
 916         unsigned int i, temp;
 917         int result;
 918         bool is_lastmsg = false;
 919         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 920
 921         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 922
 923         /* Start I2C transfer */
 924         result = i2c_imx_start(i2c_imx);
 925         if (result) {
 926                 if (i2c_imx->adapter.bus_recovery_info) {
 927                         i2c_recover_bus(&i2c_imx->adapter);
 928                         result = i2c_imx_start(i2c_imx);
 929                 }
 930         }
 931
 932         if (result)
 933                 goto fail0;
 934
 935         /* read/write data */
 936         for (i = 0; i < num; i++) {
 937                 if (i == num - 1)
 938                         is_lastmsg = true;
 939
 940                 if (i) {
 941                         dev_dbg(&i2c_imx->adapter.dev,
 942                                 "<%s> repeated start\n", __func__);
 943                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 944                         temp |= I2CR_RSTA;
 945                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 946                         result =  i2c_imx_bus_busy(i2c_imx, 1);
 947                         if (result)
 948                                 goto fail0;
 949                 }
 950                 dev_dbg(&i2c_imx->adapter.dev,
 951                         "<%s> transfer message: %d\n", __func__, i);
 952                 /* write/read data */
 953 #ifdef CONFIG_I2C_DEBUG_BUS
 954                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 955                 dev_dbg(&i2c_imx->adapter.dev,
 956                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 957                         __func__,
 958                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 959                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 960                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 961                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 962                 dev_dbg(&i2c_imx->adapter.dev,
 963                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 964                         __func__,
 965                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 966                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 967                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 968                         (temp & I2SR_RXAK ? 1 : 0));
 969 #endif
 970                 if (msgs[i].flags & I2C_M_RD)
 971                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
 972                 else {
 973                         if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
 974                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
 975                         else
 976                                 result = i2c_imx_write(i2c_imx, &msgs[i]);
 977                 }
 978                 if (result)
 979                         goto fail0;
 980         }
 981
 982 fail0:
 983         /* Stop I2C transfer */
 984         i2c_imx_stop(i2c_imx);
 985
 986         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
 987                 (result < 0) ? "error" : "success msg",
 988                         (result < 0) ? result : num);
 989         return (result < 0) ? result : num;
 990 }
 991
 992 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
 993 {
 994         struct imx_i2c_struct *i2c_imx;
 995
 996         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
 997
 998         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
 999 }
1000
1001 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1002 {
1003         struct imx_i2c_struct *i2c_imx;
1004
1005         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1006
1007         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1008 }
1009
1010 static void i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1011                 struct platform_device *pdev)
1012 {
1013         struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1014
1015         i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1016                         PINCTRL_STATE_DEFAULT);
1017         i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1018                         "gpio");
1019         rinfo->sda_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1020                         "sda-gpios", 0, NULL);
1021         rinfo->scl_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1022                         "scl-gpios", 0, NULL);
1023
1024         if (!gpio_is_valid(rinfo->sda_gpio) ||
1025             !gpio_is_valid(rinfo->scl_gpio) ||
1026             IS_ERR(i2c_imx->pinctrl_pins_default) ||
1027             IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1028                 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1029                 return;
1030         }
1031
1032         dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n",
1033                         rinfo->sda_gpio, rinfo->scl_gpio);
1034
1035         rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1036         rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1037         rinfo->recover_bus = i2c_generic_gpio_recovery;
1038         i2c_imx->adapter.bus_recovery_info = rinfo;
1039 }
1040
1041 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1042 {
1043         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1044                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1045 }
1046
1047 static struct i2c_algorithm i2c_imx_algo = {
1048         .master_xfer    = i2c_imx_xfer,
1049         .functionality  = i2c_imx_func,
1050 };
1051
1052 static int i2c_imx_probe(struct platform_device *pdev)
1053 {
1054         const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1055                                                            &pdev->dev);
1056         struct imx_i2c_struct *i2c_imx;
1057         struct resource *res;
1058         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1059         void __iomem *base;
1060         int irq, ret;
1061         dma_addr_t phy_addr;
1062
1063         dev_dbg(&pdev->dev, "<%s>\n", __func__);
1064
1065         irq = platform_get_irq(pdev, 0);
1066         if (irq < 0) {
1067                 dev_err(&pdev->dev, "can't get irq number\n");
1068                 return irq;
1069         }
1070
1071         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1072         base = devm_ioremap_resource(&pdev->dev, res);
1073         if (IS_ERR(base))
1074                 return PTR_ERR(base);
1075
1076         phy_addr = (dma_addr_t)res->start;
1077         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1078         if (!i2c_imx)
1079                 return -ENOMEM;
1080
1081         if (of_id)
1082                 i2c_imx->hwdata = of_id->data;
1083         else
1084                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1085                                 platform_get_device_id(pdev)->driver_data;
1086
1087         /* Setup i2c_imx driver structure */
1088         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1089         i2c_imx->adapter.owner          = THIS_MODULE;
1090         i2c_imx->adapter.algo           = &i2c_imx_algo;
1091         i2c_imx->adapter.dev.parent     = &pdev->dev;
1092         i2c_imx->adapter.nr             = pdev->id;
1093         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1094         i2c_imx->base                   = base;
1095
1096         /* Get I2C clock */
1097         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1098         if (IS_ERR(i2c_imx->clk)) {
1099                 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1100                         dev_err(&pdev->dev, "can't get I2C clock\n");
1101                 return PTR_ERR(i2c_imx->clk);
1102         }
1103
1104         ret = clk_prepare_enable(i2c_imx->clk);
1105         if (ret) {
1106                 dev_err(&pdev->dev, "can't enable I2C clock\n");
1107                 return ret;
1108         }
1109
1110         i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1111         if (IS_ERR(i2c_imx->pinctrl)) {
1112                 ret = PTR_ERR(i2c_imx->pinctrl);
1113                 goto clk_disable;
1114         }
1115
1116         /* Init queue */
1117         init_waitqueue_head(&i2c_imx->queue);
1118
1119         /* Set up adapter data */
1120         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1121
1122         /* Request IRQ */
1123         ret = request_threaded_irq(irq, i2c_imx_isr, NULL, 0,
1124                                    pdev->name, i2c_imx);
1125         if (ret) {
1126                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1127                 goto clk_disable;
1128         }
1129
1130         /* Set up clock divider */
1131         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1132         ret = of_property_read_u32(pdev->dev.of_node,
1133                                    "clock-frequency", &i2c_imx->bitrate);
1134         if (ret < 0 && pdata && pdata->bitrate)
1135                 i2c_imx->bitrate = pdata->bitrate;
1136
1137         /* Set up chip registers to defaults */
1138         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1139                         i2c_imx, IMX_I2C_I2CR);
1140         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1141
1142         i2c_imx_init_recovery_info(i2c_imx, pdev);
1143
1144         /* Add I2C adapter */
1145         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1146         if (ret < 0) {
1147                 dev_err(&pdev->dev, "registration failed\n");
1148                 goto clk_free_irq;
1149         }
1150
1151         /* Set up platform driver data */
1152         platform_set_drvdata(pdev, i2c_imx);
1153         clk_disable_unprepare(i2c_imx->clk);
1154
1155         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1156         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1157         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1158                 i2c_imx->adapter.name);
1159         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1160
1161         /* Init DMA config if supported */
1162         i2c_imx_dma_request(i2c_imx, phy_addr);
1163
1164         return 0;   /* Return OK */
1165
1166 clk_free_irq:
1167         free_irq(irq, i2c_imx);
1168 clk_disable:
1169         clk_disable_unprepare(i2c_imx->clk);
1170         return ret;
1171 }
1172
1173 static int i2c_imx_remove(struct platform_device *pdev)
1174 {
1175         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1176         int irq;
1177
1178         /* remove adapter */
1179         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1180         i2c_del_adapter(&i2c_imx->adapter);
1181
1182         if (i2c_imx->dma)
1183                 i2c_imx_dma_free(i2c_imx);
1184
1185         /* setup chip registers to defaults */
1186         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1187         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1188         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1189         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1190
1191         irq = platform_get_irq(pdev, 0);
1192         if (irq >= 0)
1193                 free_irq(irq, i2c_imx);
1194
1195         return 0;
1196 }
1197
1198 static struct platform_driver i2c_imx_driver = {
1199         .probe = i2c_imx_probe,
1200         .remove = i2c_imx_remove,
1201         .driver = {
1202                 .name   = DRIVER_NAME,
1203                 .of_match_table = i2c_imx_dt_ids,
1204         },
1205         .id_table       = imx_i2c_devtype,
1206 };
1207
1208 static int __init i2c_adap_imx_init(void)
1209 {
1210         return platform_driver_register(&i2c_imx_driver);
1211 }
1212 subsys_initcall(i2c_adap_imx_init);
1213
1214 static void __exit i2c_adap_imx_exit(void)
1215 {
1216         platform_driver_unregister(&i2c_imx_driver);
1217 }
1218 module_exit(i2c_adap_imx_exit);
1219
1220 MODULE_LICENSE("GPL");
1221 MODULE_AUTHOR("Darius Augulis");
1222 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1223 MODULE_ALIAS("platform:" DRIVER_NAME);