drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  62  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  63  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  64  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  65  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  66  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  67  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  68  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  69  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  70  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  71  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  72  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  73  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  74  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  75  *
  76  * Features supported by this driver:
  77  * Software PEC                         no
  78  * Hardware PEC                         yes
  79  * Block buffer                         yes
  80  * Block process call transaction       no
  81  * I2C block read transaction           yes (doesn't use the block buffer)
  82  * Slave mode                           no
  83  * SMBus Host Notify                    yes
  84  * Interrupt processing                 yes
  85  *
  86  * See the file Documentation/i2c/busses/i2c-i801 for details.
  87  */
  88
  89 #include <linux/interrupt.h>
  90 #include <linux/module.h>
  91 #include <linux/pci.h>
  92 #include <linux/kernel.h>
  93 #include <linux/stddef.h>
  94 #include <linux/delay.h>
  95 #include <linux/ioport.h>
  96 #include <linux/init.h>
  97 #include <linux/i2c.h>
  98 #include <linux/i2c-smbus.h>
  99 #include <linux/acpi.h>
 100 #include <linux/io.h>
 101 #include <linux/dmi.h>
 102 #include <linux/slab.h>
 103 #include <linux/wait.h>
 104 #include <linux/err.h>
 105 #include <linux/platform_device.h>
 106 #include <linux/platform_data/itco_wdt.h>
 107 #include <linux/pm_runtime.h>
 108
 109 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 110 #include <linux/gpio.h>
 111 #include <linux/platform_data/i2c-mux-gpio.h>
 112 #endif
 113
 114 /* I801 SMBus address offsets */
 115 #define SMBHSTSTS(p)    (0 + (p)->smba)
 116 #define SMBHSTCNT(p)    (2 + (p)->smba)
 117 #define SMBHSTCMD(p)    (3 + (p)->smba)
 118 #define SMBHSTADD(p)    (4 + (p)->smba)
 119 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 120 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 121 #define SMBBLKDAT(p)    (7 + (p)->smba)
 122 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 123 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 124 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 125 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 126 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 127 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 128
 129 /* PCI Address Constants */
 130 #define SMBBAR          4
 131 #define SMBPCICTL       0x004
 132 #define SMBPCISTS       0x006
 133 #define SMBHSTCFG       0x040
 134 #define TCOBASE         0x050
 135 #define TCOCTL          0x054
 136
 137 #define ACPIBASE                0x040
 138 #define ACPIBASE_SMI_OFF        0x030
 139 #define ACPICTRL                0x044
 140 #define ACPICTRL_EN             0x080
 141
 142 #define SBREG_BAR               0x10
 143 #define SBREG_SMBCTRL           0xc6000c
 144 #define SBREG_SMBCTRL_DNV       0xcf000c
 145
 146 /* Host status bits for SMBPCISTS */
 147 #define SMBPCISTS_INTS          BIT(3)
 148
 149 /* Control bits for SMBPCICTL */
 150 #define SMBPCICTL_INTDIS        BIT(10)
 151
 152 /* Host configuration bits for SMBHSTCFG */
 153 #define SMBHSTCFG_HST_EN        BIT(0)
 154 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 155 #define SMBHSTCFG_I2C_EN        BIT(2)
 156 #define SMBHSTCFG_SPD_WD        BIT(4)
 157
 158 /* TCO configuration bits for TCOCTL */
 159 #define TCOCTL_EN               BIT(8)
 160
 161 /* Auxiliary status register bits, ICH4+ only */
 162 #define SMBAUXSTS_CRCE          BIT(0)
 163 #define SMBAUXSTS_STCO          BIT(1)
 164
 165 /* Auxiliary control register bits, ICH4+ only */
 166 #define SMBAUXCTL_CRC           BIT(0)
 167 #define SMBAUXCTL_E32B          BIT(1)
 168
 169 /* Other settings */
 170 #define MAX_RETRIES             400
 171
 172 /* I801 command constants */
 173 #define I801_QUICK              0x00
 174 #define I801_BYTE               0x04
 175 #define I801_BYTE_DATA          0x08
 176 #define I801_WORD_DATA          0x0C
 177 #define I801_PROC_CALL          0x10    /* unimplemented */
 178 #define I801_BLOCK_DATA         0x14
 179 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 180
 181 /* I801 Host Control register bits */
 182 #define SMBHSTCNT_INTREN        BIT(0)
 183 #define SMBHSTCNT_KILL          BIT(1)
 184 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 185 #define SMBHSTCNT_START         BIT(6)
 186 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 187
 188 /* I801 Hosts Status register bits */
 189 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 190 #define SMBHSTSTS_INUSE_STS     BIT(6)
 191 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 192 #define SMBHSTSTS_FAILED        BIT(4)
 193 #define SMBHSTSTS_BUS_ERR       BIT(3)
 194 #define SMBHSTSTS_DEV_ERR       BIT(2)
 195 #define SMBHSTSTS_INTR          BIT(1)
 196 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 197
 198 /* Host Notify Status register bits */
 199 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 200
 201 /* Host Notify Command register bits */
 202 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 203
 204 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 205                                  SMBHSTSTS_DEV_ERR)
 206
 207 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 208                                  STATUS_ERROR_FLAGS)
 209
 210 /* Older devices have their ID defined in <linux/pci_ids.h> */
 211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 228 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 229 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 230 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 242 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 244 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 245
 246 struct i801_mux_config {
 247         char *gpio_chip;
 248         unsigned values[3];
 249         int n_values;
 250         unsigned classes[3];
 251         unsigned gpios[2];              /* Relative to gpio_chip->base */
 252         int n_gpios;
 253 };
 254
 255 struct i801_priv {
 256         struct i2c_adapter adapter;
 257         unsigned long smba;
 258         unsigned char original_hstcfg;
 259         unsigned char original_slvcmd;
 260         struct pci_dev *pci_dev;
 261         unsigned int features;
 262
 263         /* isr processing */
 264         wait_queue_head_t waitq;
 265         u8 status;
 266
 267         /* Command state used by isr for byte-by-byte block transactions */
 268         u8 cmd;
 269         bool is_read;
 270         int count;
 271         int len;
 272         u8 *data;
 273
 274 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 275         const struct i801_mux_config *mux_drvdata;
 276         struct platform_device *mux_pdev;
 277 #endif
 278         struct platform_device *tco_pdev;
 279
 280         /*
 281          * If set to true the host controller registers are reserved for
 282          * ACPI AML use. Protected by acpi_lock.
 283          */
 284         bool acpi_reserved;
 285         struct mutex acpi_lock;
 286 };
 287
 288 #define FEATURE_SMBUS_PEC       BIT(0)
 289 #define FEATURE_BLOCK_BUFFER    BIT(1)
 290 #define FEATURE_BLOCK_PROC      BIT(2)
 291 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 292 #define FEATURE_IRQ             BIT(4)
 293 #define FEATURE_HOST_NOTIFY     BIT(5)
 294 /* Not really a feature, but it's convenient to handle it as such */
 295 #define FEATURE_IDF             BIT(15)
 296 #define FEATURE_TCO             BIT(16)
 297
 298 static const char *i801_feature_names[] = {
 299         "SMBus PEC",
 300         "Block buffer",
 301         "Block process call",
 302         "I2C block read",
 303         "Interrupt",
 304         "SMBus Host Notify",
 305 };
 306
 307 static unsigned int disable_features;
 308 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 309 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 310         "\t\t  0x01  disable SMBus PEC\n"
 311         "\t\t  0x02  disable the block buffer\n"
 312         "\t\t  0x08  disable the I2C block read functionality\n"
 313         "\t\t  0x10  don't use interrupts\n"
 314         "\t\t  0x20  disable SMBus Host Notify ");
 315
 316 /* Make sure the SMBus host is ready to start transmitting.
 317    Return 0 if it is, -EBUSY if it is not. */
 318 static int i801_check_pre(struct i801_priv *priv)
 319 {
 320         int status;
 321
 322         status = inb_p(SMBHSTSTS(priv));
 323         if (status & SMBHSTSTS_HOST_BUSY) {
 324                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 325                 return -EBUSY;
 326         }
 327
 328         status &= STATUS_FLAGS;
 329         if (status) {
 330                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 331                         status);
 332                 outb_p(status, SMBHSTSTS(priv));
 333                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 334                 if (status) {
 335                         dev_err(&priv->pci_dev->dev,
 336                                 "Failed clearing status flags (%02x)\n",
 337                                 status);
 338                         return -EBUSY;
 339                 }
 340         }
 341
 342         /*
 343          * Clear CRC status if needed.
 344          * During normal operation, i801_check_post() takes care
 345          * of it after every operation.  We do it here only in case
 346          * the hardware was already in this state when the driver
 347          * started.
 348          */
 349         if (priv->features & FEATURE_SMBUS_PEC) {
 350                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 351                 if (status) {
 352                         dev_dbg(&priv->pci_dev->dev,
 353                                 "Clearing aux status flags (%02x)\n", status);
 354                         outb_p(status, SMBAUXSTS(priv));
 355                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 356                         if (status) {
 357                                 dev_err(&priv->pci_dev->dev,
 358                                         "Failed clearing aux status flags (%02x)\n",
 359                                         status);
 360                                 return -EBUSY;
 361                         }
 362                 }
 363         }
 364
 365         return 0;
 366 }
 367
 368 /*
 369  * Convert the status register to an error code, and clear it.
 370  * Note that status only contains the bits we want to clear, not the
 371  * actual register value.
 372  */
 373 static int i801_check_post(struct i801_priv *priv, int status)
 374 {
 375         int result = 0;
 376
 377         /*
 378          * If the SMBus is still busy, we give up
 379          * Note: This timeout condition only happens when using polling
 380          * transactions.  For interrupt operation, NAK/timeout is indicated by
 381          * DEV_ERR.
 382          */
 383         if (unlikely(status < 0)) {
 384                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 385                 /* try to stop the current command */
 386                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 387                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 388                 usleep_range(1000, 2000);
 389                 outb_p(0, SMBHSTCNT(priv));
 390
 391                 /* Check if it worked */
 392                 status = inb_p(SMBHSTSTS(priv));
 393                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 394                     !(status & SMBHSTSTS_FAILED))
 395                         dev_err(&priv->pci_dev->dev,
 396                                 "Failed terminating the transaction\n");
 397                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 398                 return -ETIMEDOUT;
 399         }
 400
 401         if (status & SMBHSTSTS_FAILED) {
 402                 result = -EIO;
 403                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 404         }
 405         if (status & SMBHSTSTS_DEV_ERR) {
 406                 /*
 407                  * This may be a PEC error, check and clear it.
 408                  *
 409                  * AUXSTS is handled differently from HSTSTS.
 410                  * For HSTSTS, i801_isr() or i801_wait_intr()
 411                  * has already cleared the error bits in hardware,
 412                  * and we are passed a copy of the original value
 413                  * in "status".
 414                  * For AUXSTS, the hardware register is left
 415                  * for us to handle here.
 416                  * This is asymmetric, slightly iffy, but safe,
 417                  * since all this code is serialized and the CRCE
 418                  * bit is harmless as long as it's cleared before
 419                  * the next operation.
 420                  */
 421                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 422                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 423                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 424                         result = -EBADMSG;
 425                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 426                 } else {
 427                         result = -ENXIO;
 428                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 429                 }
 430         }
 431         if (status & SMBHSTSTS_BUS_ERR) {
 432                 result = -EAGAIN;
 433                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 434         }
 435
 436         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 437         outb_p(status, SMBHSTSTS(priv));
 438
 439         return result;
 440 }
 441
 442 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 443 static int i801_wait_intr(struct i801_priv *priv)
 444 {
 445         int timeout = 0;
 446         int status;
 447
 448         /* We will always wait for a fraction of a second! */
 449         do {
 450                 usleep_range(250, 500);
 451                 status = inb_p(SMBHSTSTS(priv));
 452         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 453                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 454                  (timeout++ < MAX_RETRIES));
 455
 456         if (timeout > MAX_RETRIES) {
 457                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 458                 return -ETIMEDOUT;
 459         }
 460         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 461 }
 462
 463 /* Wait for either BYTE_DONE or an error flag being set */
 464 static int i801_wait_byte_done(struct i801_priv *priv)
 465 {
 466         int timeout = 0;
 467         int status;
 468
 469         /* We will always wait for a fraction of a second! */
 470         do {
 471                 usleep_range(250, 500);
 472                 status = inb_p(SMBHSTSTS(priv));
 473         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 474                  (timeout++ < MAX_RETRIES));
 475
 476         if (timeout > MAX_RETRIES) {
 477                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 478                 return -ETIMEDOUT;
 479         }
 480         return status & STATUS_ERROR_FLAGS;
 481 }
 482
 483 static int i801_transaction(struct i801_priv *priv, int xact)
 484 {
 485         int status;
 486         int result;
 487         const struct i2c_adapter *adap = &priv->adapter;
 488
 489         result = i801_check_pre(priv);
 490         if (result < 0)
 491                 return result;
 492
 493         if (priv->features & FEATURE_IRQ) {
 494                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 495                        SMBHSTCNT(priv));
 496                 result = wait_event_timeout(priv->waitq,
 497                                             (status = priv->status),
 498                                             adap->timeout);
 499                 if (!result) {
 500                         status = -ETIMEDOUT;
 501                         dev_warn(&priv->pci_dev->dev,
 502                                  "Timeout waiting for interrupt!\n");
 503                 }
 504                 priv->status = 0;
 505                 return i801_check_post(priv, status);
 506         }
 507
 508         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 509          * SMBSCMD are passed in xact */
 510         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 511
 512         status = i801_wait_intr(priv);
 513         return i801_check_post(priv, status);
 514 }
 515
 516 static int i801_block_transaction_by_block(struct i801_priv *priv,
 517                                            union i2c_smbus_data *data,
 518                                            char read_write, int hwpec)
 519 {
 520         int i, len;
 521         int status;
 522
 523         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 524
 525         /* Use 32-byte buffer to process this transaction */
 526         if (read_write == I2C_SMBUS_WRITE) {
 527                 len = data->block[0];
 528                 outb_p(len, SMBHSTDAT0(priv));
 529                 for (i = 0; i < len; i++)
 530                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 531         }
 532
 533         status = i801_transaction(priv, I801_BLOCK_DATA |
 534                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 535         if (status)
 536                 return status;
 537
 538         if (read_write == I2C_SMBUS_READ) {
 539                 len = inb_p(SMBHSTDAT0(priv));
 540                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 541                         return -EPROTO;
 542
 543                 data->block[0] = len;
 544                 for (i = 0; i < len; i++)
 545                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 546         }
 547         return 0;
 548 }
 549
 550 static void i801_isr_byte_done(struct i801_priv *priv)
 551 {
 552         if (priv->is_read) {
 553                 /* For SMBus block reads, length is received with first byte */
 554                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 555                     (priv->count == 0)) {
 556                         priv->len = inb_p(SMBHSTDAT0(priv));
 557                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 558                                 dev_err(&priv->pci_dev->dev,
 559                                         "Illegal SMBus block read size %d\n",
 560                                         priv->len);
 561                                 /* FIXME: Recover */
 562                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 563                         } else {
 564                                 dev_dbg(&priv->pci_dev->dev,
 565                                         "SMBus block read size is %d\n",
 566                                         priv->len);
 567                         }
 568                         priv->data[-1] = priv->len;
 569                 }
 570
 571                 /* Read next byte */
 572                 if (priv->count < priv->len)
 573                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 574                 else
 575                         dev_dbg(&priv->pci_dev->dev,
 576                                 "Discarding extra byte on block read\n");
 577
 578                 /* Set LAST_BYTE for last byte of read transaction */
 579                 if (priv->count == priv->len - 1)
 580                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 581                                SMBHSTCNT(priv));
 582         } else if (priv->count < priv->len - 1) {
 583                 /* Write next byte, except for IRQ after last byte */
 584                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 585         }
 586
 587         /* Clear BYTE_DONE to continue with next byte */
 588         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 589 }
 590
 591 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 592 {
 593         unsigned short addr;
 594
 595         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 596
 597         /*
 598          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 599          * always returns 0. Our current implementation doesn't provide
 600          * data, so we just ignore it.
 601          */
 602         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 603
 604         /* clear Host Notify bit and return */
 605         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 606         return IRQ_HANDLED;
 607 }
 608
 609 /*
 610  * There are three kinds of interrupts:
 611  *
 612  * 1) i801 signals transaction completion with one of these interrupts:
 613  *      INTR - Success
 614  *      DEV_ERR - Invalid command, NAK or communication timeout
 615  *      BUS_ERR - SMI# transaction collision
 616  *      FAILED - transaction was canceled due to a KILL request
 617  *    When any of these occur, update ->status and wake up the waitq.
 618  *    ->status must be cleared before kicking off the next transaction.
 619  *
 620  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 621  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 622  *
 623  * 3) Host Notify interrupts
 624  */
 625 static irqreturn_t i801_isr(int irq, void *dev_id)
 626 {
 627         struct i801_priv *priv = dev_id;
 628         u16 pcists;
 629         u8 status;
 630
 631         /* Confirm this is our interrupt */
 632         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 633         if (!(pcists & SMBPCISTS_INTS))
 634                 return IRQ_NONE;
 635
 636         if (priv->features & FEATURE_HOST_NOTIFY) {
 637                 status = inb_p(SMBSLVSTS(priv));
 638                 if (status & SMBSLVSTS_HST_NTFY_STS)
 639                         return i801_host_notify_isr(priv);
 640         }
 641
 642         status = inb_p(SMBHSTSTS(priv));
 643         if (status & SMBHSTSTS_BYTE_DONE)
 644                 i801_isr_byte_done(priv);
 645
 646         /*
 647          * Clear irq sources and report transaction result.
 648          * ->status must be cleared before the next transaction is started.
 649          */
 650         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 651         if (status) {
 652                 outb_p(status, SMBHSTSTS(priv));
 653                 priv->status = status;
 654                 wake_up(&priv->waitq);
 655         }
 656
 657         return IRQ_HANDLED;
 658 }
 659
 660 /*
 661  * For "byte-by-byte" block transactions:
 662  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 663  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 664  */
 665 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 666                                                union i2c_smbus_data *data,
 667                                                char read_write, int command,
 668                                                int hwpec)
 669 {
 670         int i, len;
 671         int smbcmd;
 672         int status;
 673         int result;
 674         const struct i2c_adapter *adap = &priv->adapter;
 675
 676         result = i801_check_pre(priv);
 677         if (result < 0)
 678                 return result;
 679
 680         len = data->block[0];
 681
 682         if (read_write == I2C_SMBUS_WRITE) {
 683                 outb_p(len, SMBHSTDAT0(priv));
 684                 outb_p(data->block[1], SMBBLKDAT(priv));
 685         }
 686
 687         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 688             read_write == I2C_SMBUS_READ)
 689                 smbcmd = I801_I2C_BLOCK_DATA;
 690         else
 691                 smbcmd = I801_BLOCK_DATA;
 692
 693         if (priv->features & FEATURE_IRQ) {
 694                 priv->is_read = (read_write == I2C_SMBUS_READ);
 695                 if (len == 1 && priv->is_read)
 696                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 697                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 698                 priv->len = len;
 699                 priv->count = 0;
 700                 priv->data = &data->block[1];
 701
 702                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 703                 result = wait_event_timeout(priv->waitq,
 704                                             (status = priv->status),
 705                                             adap->timeout);
 706                 if (!result) {
 707                         status = -ETIMEDOUT;
 708                         dev_warn(&priv->pci_dev->dev,
 709                                  "Timeout waiting for interrupt!\n");
 710                 }
 711                 priv->status = 0;
 712                 return i801_check_post(priv, status);
 713         }
 714
 715         if (len == 1 && read_write == I2C_SMBUS_READ)
 716                 smbcmd |= SMBHSTCNT_LAST_BYTE;
 717         outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 718
 719         for (i = 1; i <= len; i++) {
 720                 status = i801_wait_byte_done(priv);
 721                 if (status)
 722                         goto exit;
 723
 724                 if (i == 1 && read_write == I2C_SMBUS_READ
 725                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 726                         len = inb_p(SMBHSTDAT0(priv));
 727                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 728                                 dev_err(&priv->pci_dev->dev,
 729                                         "Illegal SMBus block read size %d\n",
 730                                         len);
 731                                 /* Recover */
 732                                 while (inb_p(SMBHSTSTS(priv)) &
 733                                        SMBHSTSTS_HOST_BUSY)
 734                                         outb_p(SMBHSTSTS_BYTE_DONE,
 735                                                SMBHSTSTS(priv));
 736                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 737                                 return -EPROTO;
 738                         }
 739                         data->block[0] = len;
 740                 }
 741
 742                 if (read_write == I2C_SMBUS_READ) {
 743                         data->block[i] = inb_p(SMBBLKDAT(priv));
 744                         if (i == len - 1)
 745                                 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
 746                 }
 747
 748                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 749                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 750
 751                 /* signals SMBBLKDAT ready */
 752                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 753         }
 754
 755         status = i801_wait_intr(priv);
 756 exit:
 757         return i801_check_post(priv, status);
 758 }
 759
 760 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 761 {
 762         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 763         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 764                 return -EIO;
 765         return 0;
 766 }
 767
 768 /* Block transaction function */
 769 static int i801_block_transaction(struct i801_priv *priv,
 770                                   union i2c_smbus_data *data, char read_write,
 771                                   int command, int hwpec)
 772 {
 773         int result = 0;
 774         unsigned char hostc;
 775
 776         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 777                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 778         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 779                 return -EPROTO;
 780
 781         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 782                 if (read_write == I2C_SMBUS_WRITE) {
 783                         /* set I2C_EN bit in configuration register */
 784                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 785                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 786                                               hostc | SMBHSTCFG_I2C_EN);
 787                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 788                         dev_err(&priv->pci_dev->dev,
 789                                 "I2C block read is unsupported!\n");
 790                         return -EOPNOTSUPP;
 791                 }
 792         }
 793
 794         /* Experience has shown that the block buffer can only be used for
 795            SMBus (not I2C) block transactions, even though the datasheet
 796            doesn't mention this limitation. */
 797         if ((priv->features & FEATURE_BLOCK_BUFFER)
 798          && command != I2C_SMBUS_I2C_BLOCK_DATA
 799          && i801_set_block_buffer_mode(priv) == 0)
 800                 result = i801_block_transaction_by_block(priv, data,
 801                                                          read_write, hwpec);
 802         else
 803                 result = i801_block_transaction_byte_by_byte(priv, data,
 804                                                              read_write,
 805                                                              command, hwpec);
 806
 807         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 808          && read_write == I2C_SMBUS_WRITE) {
 809                 /* restore saved configuration register value */
 810                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 811         }
 812         return result;
 813 }
 814
 815 /* Return negative errno on error. */
 816 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 817                        unsigned short flags, char read_write, u8 command,
 818                        int size, union i2c_smbus_data *data)
 819 {
 820         int hwpec;
 821         int block = 0;
 822         int ret = 0, xact = 0;
 823         struct i801_priv *priv = i2c_get_adapdata(adap);
 824
 825         mutex_lock(&priv->acpi_lock);
 826         if (priv->acpi_reserved) {
 827                 mutex_unlock(&priv->acpi_lock);
 828                 return -EBUSY;
 829         }
 830
 831         pm_runtime_get_sync(&priv->pci_dev->dev);
 832
 833         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 834                 && size != I2C_SMBUS_QUICK
 835                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 836
 837         switch (size) {
 838         case I2C_SMBUS_QUICK:
 839                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 840                        SMBHSTADD(priv));
 841                 xact = I801_QUICK;
 842                 break;
 843         case I2C_SMBUS_BYTE:
 844                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 845                        SMBHSTADD(priv));
 846                 if (read_write == I2C_SMBUS_WRITE)
 847                         outb_p(command, SMBHSTCMD(priv));
 848                 xact = I801_BYTE;
 849                 break;
 850         case I2C_SMBUS_BYTE_DATA:
 851                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 852                        SMBHSTADD(priv));
 853                 outb_p(command, SMBHSTCMD(priv));
 854                 if (read_write == I2C_SMBUS_WRITE)
 855                         outb_p(data->byte, SMBHSTDAT0(priv));
 856                 xact = I801_BYTE_DATA;
 857                 break;
 858         case I2C_SMBUS_WORD_DATA:
 859                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 860                        SMBHSTADD(priv));
 861                 outb_p(command, SMBHSTCMD(priv));
 862                 if (read_write == I2C_SMBUS_WRITE) {
 863                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 864                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 865                 }
 866                 xact = I801_WORD_DATA;
 867                 break;
 868         case I2C_SMBUS_BLOCK_DATA:
 869                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 870                        SMBHSTADD(priv));
 871                 outb_p(command, SMBHSTCMD(priv));
 872                 block = 1;
 873                 break;
 874         case I2C_SMBUS_I2C_BLOCK_DATA:
 875                 /*
 876                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 877                  * bit should be cleared here, even when reading.
 878                  * However if SPD Write Disable is set (Lynx Point and later),
 879                  * the read will fail if we don't set the R/#W bit.
 880                  */
 881                 outb_p(((addr & 0x7f) << 1) |
 882                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 883                         (read_write & 0x01) : 0),
 884                        SMBHSTADD(priv));
 885                 if (read_write == I2C_SMBUS_READ) {
 886                         /* NB: page 240 of ICH5 datasheet also shows
 887                          * that DATA1 is the cmd field when reading */
 888                         outb_p(command, SMBHSTDAT1(priv));
 889                 } else
 890                         outb_p(command, SMBHSTCMD(priv));
 891                 block = 1;
 892                 break;
 893         default:
 894                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 895                         size);
 896                 ret = -EOPNOTSUPP;
 897                 goto out;
 898         }
 899
 900         if (hwpec)      /* enable/disable hardware PEC */
 901                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 902         else
 903                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 904                        SMBAUXCTL(priv));
 905
 906         if (block)
 907                 ret = i801_block_transaction(priv, data, read_write, size,
 908                                              hwpec);
 909         else
 910                 ret = i801_transaction(priv, xact);
 911
 912         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 913            time, so we forcibly disable it after every transaction. Turn off
 914            E32B for the same reason. */
 915         if (hwpec || block)
 916                 outb_p(inb_p(SMBAUXCTL(priv)) &
 917                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 918
 919         if (block)
 920                 goto out;
 921         if (ret)
 922                 goto out;
 923         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 924                 goto out;
 925
 926         switch (xact & 0x7f) {
 927         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 928         case I801_BYTE_DATA:
 929                 data->byte = inb_p(SMBHSTDAT0(priv));
 930                 break;
 931         case I801_WORD_DATA:
 932                 data->word = inb_p(SMBHSTDAT0(priv)) +
 933                              (inb_p(SMBHSTDAT1(priv)) << 8);
 934                 break;
 935         }
 936
 937 out:
 938         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 939         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 940         mutex_unlock(&priv->acpi_lock);
 941         return ret;
 942 }
 943
 944
 945 static u32 i801_func(struct i2c_adapter *adapter)
 946 {
 947         struct i801_priv *priv = i2c_get_adapdata(adapter);
 948
 949         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 950                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 951                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 952                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 953                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 954                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 955                ((priv->features & FEATURE_HOST_NOTIFY) ?
 956                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 957 }
 958
 959 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 960 {
 961         struct i801_priv *priv = i2c_get_adapdata(adapter);
 962
 963         if (!(priv->features & FEATURE_HOST_NOTIFY))
 964                 return;
 965
 966         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 967                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 968                        SMBSLVCMD(priv));
 969
 970         /* clear Host Notify bit to allow a new notification */
 971         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 972 }
 973
 974 static void i801_disable_host_notify(struct i801_priv *priv)
 975 {
 976         if (!(priv->features & FEATURE_HOST_NOTIFY))
 977                 return;
 978
 979         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 980 }
 981
 982 static const struct i2c_algorithm smbus_algorithm = {
 983         .smbus_xfer     = i801_access,
 984         .functionality  = i801_func,
 985 };
 986
 987 static const struct pci_device_id i801_ids[] = {
 988         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 989         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 990         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 991         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 992         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 993         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1012         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1013         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1014         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1015         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1016         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1017         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1018         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1026         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1029         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1030         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1036         { 0, }
1037 };
1038
1039 MODULE_DEVICE_TABLE(pci, i801_ids);
1040
1041 #if defined CONFIG_X86 && defined CONFIG_DMI
1042 static unsigned char apanel_addr;
1043
1044 /* Scan the system ROM for the signature "FJKEYINF" */
1045 static __init const void __iomem *bios_signature(const void __iomem *bios)
1046 {
1047         ssize_t offset;
1048         const unsigned char signature[] = "FJKEYINF";
1049
1050         for (offset = 0; offset < 0x10000; offset += 0x10) {
1051                 if (check_signature(bios + offset, signature,
1052                                     sizeof(signature)-1))
1053                         return bios + offset;
1054         }
1055         return NULL;
1056 }
1057
1058 static void __init input_apanel_init(void)
1059 {
1060         void __iomem *bios;
1061         const void __iomem *p;
1062
1063         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1064         p = bios_signature(bios);
1065         if (p) {
1066                 /* just use the first address */
1067                 apanel_addr = readb(p + 8 + 3) >> 1;
1068         }
1069         iounmap(bios);
1070 }
1071
1072 struct dmi_onboard_device_info {
1073         const char *name;
1074         u8 type;
1075         unsigned short i2c_addr;
1076         const char *i2c_type;
1077 };
1078
1079 static const struct dmi_onboard_device_info dmi_devices[] = {
1080         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1081         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1082         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1083 };
1084
1085 static void dmi_check_onboard_device(u8 type, const char *name,
1086                                      struct i2c_adapter *adap)
1087 {
1088         int i;
1089         struct i2c_board_info info;
1090
1091         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1092                 /* & ~0x80, ignore enabled/disabled bit */
1093                 if ((type & ~0x80) != dmi_devices[i].type)
1094                         continue;
1095                 if (strcasecmp(name, dmi_devices[i].name))
1096                         continue;
1097
1098                 memset(&info, 0, sizeof(struct i2c_board_info));
1099                 info.addr = dmi_devices[i].i2c_addr;
1100                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1101                 i2c_new_device(adap, &info);
1102                 break;
1103         }
1104 }
1105
1106 /* We use our own function to check for onboard devices instead of
1107    dmi_find_device() as some buggy BIOS's have the devices we are interested
1108    in marked as disabled */
1109 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1110 {
1111         int i, count;
1112
1113         if (dm->type != 10)
1114                 return;
1115
1116         count = (dm->length - sizeof(struct dmi_header)) / 2;
1117         for (i = 0; i < count; i++) {
1118                 const u8 *d = (char *)(dm + 1) + (i * 2);
1119                 const char *name = ((char *) dm) + dm->length;
1120                 u8 type = d[0];
1121                 u8 s = d[1];
1122
1123                 if (!s)
1124                         continue;
1125                 s--;
1126                 while (s > 0 && name[0]) {
1127                         name += strlen(name) + 1;
1128                         s--;
1129                 }
1130                 if (name[0] == 0) /* Bogus string reference */
1131                         continue;
1132
1133                 dmi_check_onboard_device(type, name, adap);
1134         }
1135 }
1136
1137 /* Register optional slaves */
1138 static void i801_probe_optional_slaves(struct i801_priv *priv)
1139 {
1140         /* Only register slaves on main SMBus channel */
1141         if (priv->features & FEATURE_IDF)
1142                 return;
1143
1144         if (apanel_addr) {
1145                 struct i2c_board_info info;
1146
1147                 memset(&info, 0, sizeof(struct i2c_board_info));
1148                 info.addr = apanel_addr;
1149                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1150                 i2c_new_device(&priv->adapter, &info);
1151         }
1152
1153         if (dmi_name_in_vendors("FUJITSU"))
1154                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1155 }
1156 #else
1157 static void __init input_apanel_init(void) {}
1158 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1159 #endif  /* CONFIG_X86 && CONFIG_DMI */
1160
1161 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1162 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1163         .gpio_chip = "gpio_ich",
1164         .values = { 0x02, 0x03 },
1165         .n_values = 2,
1166         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1167         .gpios = { 52, 53 },
1168         .n_gpios = 2,
1169 };
1170
1171 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1172         .gpio_chip = "gpio_ich",
1173         .values = { 0x02, 0x03, 0x01 },
1174         .n_values = 3,
1175         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1176         .gpios = { 52, 53 },
1177         .n_gpios = 2,
1178 };
1179
1180 static const struct dmi_system_id mux_dmi_table[] = {
1181         {
1182                 .matches = {
1183                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1184                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1185                 },
1186                 .driver_data = &i801_mux_config_asus_z8_d12,
1187         },
1188         {
1189                 .matches = {
1190                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1191                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1192                 },
1193                 .driver_data = &i801_mux_config_asus_z8_d12,
1194         },
1195         {
1196                 .matches = {
1197                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1198                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1199                 },
1200                 .driver_data = &i801_mux_config_asus_z8_d12,
1201         },
1202         {
1203                 .matches = {
1204                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1205                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1206                 },
1207                 .driver_data = &i801_mux_config_asus_z8_d12,
1208         },
1209         {
1210                 .matches = {
1211                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1212                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1213                 },
1214                 .driver_data = &i801_mux_config_asus_z8_d12,
1215         },
1216         {
1217                 .matches = {
1218                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1219                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1220                 },
1221                 .driver_data = &i801_mux_config_asus_z8_d12,
1222         },
1223         {
1224                 .matches = {
1225                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1226                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1227                 },
1228                 .driver_data = &i801_mux_config_asus_z8_d18,
1229         },
1230         {
1231                 .matches = {
1232                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1233                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1234                 },
1235                 .driver_data = &i801_mux_config_asus_z8_d18,
1236         },
1237         {
1238                 .matches = {
1239                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1240                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1241                 },
1242                 .driver_data = &i801_mux_config_asus_z8_d12,
1243         },
1244         { }
1245 };
1246
1247 /* Setup multiplexing if needed */
1248 static int i801_add_mux(struct i801_priv *priv)
1249 {
1250         struct device *dev = &priv->adapter.dev;
1251         const struct i801_mux_config *mux_config;
1252         struct i2c_mux_gpio_platform_data gpio_data;
1253         int err;
1254
1255         if (!priv->mux_drvdata)
1256                 return 0;
1257         mux_config = priv->mux_drvdata;
1258
1259         /* Prepare the platform data */
1260         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1261         gpio_data.parent = priv->adapter.nr;
1262         gpio_data.values = mux_config->values;
1263         gpio_data.n_values = mux_config->n_values;
1264         gpio_data.classes = mux_config->classes;
1265         gpio_data.gpio_chip = mux_config->gpio_chip;
1266         gpio_data.gpios = mux_config->gpios;
1267         gpio_data.n_gpios = mux_config->n_gpios;
1268         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1269
1270         /* Register the mux device */
1271         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1272                                 PLATFORM_DEVID_AUTO, &gpio_data,
1273                                 sizeof(struct i2c_mux_gpio_platform_data));
1274         if (IS_ERR(priv->mux_pdev)) {
1275                 err = PTR_ERR(priv->mux_pdev);
1276                 priv->mux_pdev = NULL;
1277                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1278                 return err;
1279         }
1280
1281         return 0;
1282 }
1283
1284 static void i801_del_mux(struct i801_priv *priv)
1285 {
1286         if (priv->mux_pdev)
1287                 platform_device_unregister(priv->mux_pdev);
1288 }
1289
1290 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1291 {
1292         const struct dmi_system_id *id;
1293         const struct i801_mux_config *mux_config;
1294         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1295         int i;
1296
1297         id = dmi_first_match(mux_dmi_table);
1298         if (id) {
1299                 /* Remove branch classes from trunk */
1300                 mux_config = id->driver_data;
1301                 for (i = 0; i < mux_config->n_values; i++)
1302                         class &= ~mux_config->classes[i];
1303
1304                 /* Remember for later */
1305                 priv->mux_drvdata = mux_config;
1306         }
1307
1308         return class;
1309 }
1310 #else
1311 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1312 static inline void i801_del_mux(struct i801_priv *priv) { }
1313
1314 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1315 {
1316         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1317 }
1318 #endif
1319
1320 static const struct itco_wdt_platform_data tco_platform_data = {
1321         .name = "Intel PCH",
1322         .version = 4,
1323 };
1324
1325 static DEFINE_SPINLOCK(p2sb_spinlock);
1326
1327 static void i801_add_tco(struct i801_priv *priv)
1328 {
1329         struct pci_dev *pci_dev = priv->pci_dev;
1330         struct resource tco_res[3], *res;
1331         struct platform_device *pdev;
1332         unsigned int devfn;
1333         u32 tco_base, tco_ctl;
1334         u32 base_addr, ctrl_val;
1335         u64 base64_addr;
1336         u8 hidden;
1337
1338         if (!(priv->features & FEATURE_TCO))
1339                 return;
1340
1341         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1342         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1343         if (!(tco_ctl & TCOCTL_EN))
1344                 return;
1345
1346         memset(tco_res, 0, sizeof(tco_res));
1347
1348         res = &tco_res[ICH_RES_IO_TCO];
1349         res->start = tco_base & ~1;
1350         res->end = res->start + 32 - 1;
1351         res->flags = IORESOURCE_IO;
1352
1353         /*
1354          * Power Management registers.
1355          */
1356         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1357         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1358
1359         res = &tco_res[ICH_RES_IO_SMI];
1360         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1361         res->end = res->start + 3;
1362         res->flags = IORESOURCE_IO;
1363
1364         /*
1365          * Enable the ACPI I/O space.
1366          */
1367         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1368         ctrl_val |= ACPICTRL_EN;
1369         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1370
1371         /*
1372          * We must access the NO_REBOOT bit over the Primary to Sideband
1373          * bridge (P2SB). The BIOS prevents the P2SB device from being
1374          * enumerated by the PCI subsystem, so we need to unhide/hide it
1375          * to lookup the P2SB BAR.
1376          */
1377         spin_lock(&p2sb_spinlock);
1378
1379         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1380
1381         /* Unhide the P2SB device, if it is hidden */
1382         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1383         if (hidden)
1384                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1385
1386         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1387         base64_addr = base_addr & 0xfffffff0;
1388
1389         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1390         base64_addr |= (u64)base_addr << 32;
1391
1392         /* Hide the P2SB device, if it was hidden before */
1393         if (hidden)
1394                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1395         spin_unlock(&p2sb_spinlock);
1396
1397         res = &tco_res[ICH_RES_MEM_OFF];
1398         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1399                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1400         else
1401                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1402
1403         res->end = res->start + 3;
1404         res->flags = IORESOURCE_MEM;
1405
1406         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1407                                                  tco_res, 3, &tco_platform_data,
1408                                                  sizeof(tco_platform_data));
1409         if (IS_ERR(pdev)) {
1410                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1411                 return;
1412         }
1413
1414         priv->tco_pdev = pdev;
1415 }
1416
1417 #ifdef CONFIG_ACPI
1418 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1419                                       acpi_physical_address address)
1420 {
1421         return address >= priv->smba &&
1422                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1423 }
1424
1425 static acpi_status
1426 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1427                      u64 *value, void *handler_context, void *region_context)
1428 {
1429         struct i801_priv *priv = handler_context;
1430         struct pci_dev *pdev = priv->pci_dev;
1431         acpi_status status;
1432
1433         /*
1434          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1435          * further access from the driver itself. This device is now owned
1436          * by the system firmware.
1437          */
1438         mutex_lock(&priv->acpi_lock);
1439
1440         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1441                 priv->acpi_reserved = true;
1442
1443                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1444                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1445
1446                 /*
1447                  * BIOS is accessing the host controller so prevent it from
1448                  * suspending automatically from now on.
1449                  */
1450                 pm_runtime_get_sync(&pdev->dev);
1451         }
1452
1453         if ((function & ACPI_IO_MASK) == ACPI_READ)
1454                 status = acpi_os_read_port(address, (u32 *)value, bits);
1455         else
1456                 status = acpi_os_write_port(address, (u32)*value, bits);
1457
1458         mutex_unlock(&priv->acpi_lock);
1459
1460         return status;
1461 }
1462
1463 static int i801_acpi_probe(struct i801_priv *priv)
1464 {
1465         struct acpi_device *adev;
1466         acpi_status status;
1467
1468         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1469         if (adev) {
1470                 status = acpi_install_address_space_handler(adev->handle,
1471                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1472                                 NULL, priv);
1473                 if (ACPI_SUCCESS(status))
1474                         return 0;
1475         }
1476
1477         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1478 }
1479
1480 static void i801_acpi_remove(struct i801_priv *priv)
1481 {
1482         struct acpi_device *adev;
1483
1484         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1485         if (!adev)
1486                 return;
1487
1488         acpi_remove_address_space_handler(adev->handle,
1489                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1490
1491         mutex_lock(&priv->acpi_lock);
1492         if (priv->acpi_reserved)
1493                 pm_runtime_put(&priv->pci_dev->dev);
1494         mutex_unlock(&priv->acpi_lock);
1495 }
1496 #else
1497 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1498 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1499 #endif
1500
1501 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1502 {
1503         unsigned char hstcfg = priv->original_hstcfg;
1504
1505         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1506         hstcfg |= SMBHSTCFG_HST_EN;
1507         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1508         return hstcfg;
1509 }
1510
1511 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1512 {
1513         unsigned char temp;
1514         int err, i;
1515         struct i801_priv *priv;
1516
1517         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1518         if (!priv)
1519                 return -ENOMEM;
1520
1521         i2c_set_adapdata(&priv->adapter, priv);
1522         priv->adapter.owner = THIS_MODULE;
1523         priv->adapter.class = i801_get_adapter_class(priv);
1524         priv->adapter.algo = &smbus_algorithm;
1525         priv->adapter.dev.parent = &dev->dev;
1526         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1527         priv->adapter.retries = 3;
1528         mutex_init(&priv->acpi_lock);
1529
1530         priv->pci_dev = dev;
1531         switch (dev->device) {
1532         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1533         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1534         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1535         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1536         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1537         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1538         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1539         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1540         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1541         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1542         case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1543                 priv->features |= FEATURE_I2C_BLOCK_READ;
1544                 priv->features |= FEATURE_IRQ;
1545                 priv->features |= FEATURE_SMBUS_PEC;
1546                 priv->features |= FEATURE_BLOCK_BUFFER;
1547                 /* If we have ACPI based watchdog use that instead */
1548                 if (!acpi_has_watchdog())
1549                         priv->features |= FEATURE_TCO;
1550                 priv->features |= FEATURE_HOST_NOTIFY;
1551                 break;
1552
1553         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1554         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1555         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1556         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1557         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1558         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1559                 priv->features |= FEATURE_IDF;
1560                 /* fall through */
1561         default:
1562                 priv->features |= FEATURE_I2C_BLOCK_READ;
1563                 priv->features |= FEATURE_IRQ;
1564                 /* fall through */
1565         case PCI_DEVICE_ID_INTEL_82801DB_3:
1566                 priv->features |= FEATURE_SMBUS_PEC;
1567                 priv->features |= FEATURE_BLOCK_BUFFER;
1568                 /* fall through */
1569         case PCI_DEVICE_ID_INTEL_82801CA_3:
1570                 priv->features |= FEATURE_HOST_NOTIFY;
1571                 /* fall through */
1572         case PCI_DEVICE_ID_INTEL_82801BA_2:
1573         case PCI_DEVICE_ID_INTEL_82801AB_3:
1574         case PCI_DEVICE_ID_INTEL_82801AA_3:
1575                 break;
1576         }
1577
1578         /* Disable features on user request */
1579         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1580                 if (priv->features & disable_features & (1 << i))
1581                         dev_notice(&dev->dev, "%s disabled by user\n",
1582                                    i801_feature_names[i]);
1583         }
1584         priv->features &= ~disable_features;
1585
1586         err = pcim_enable_device(dev);
1587         if (err) {
1588                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1589                         err);
1590                 return err;
1591         }
1592         pcim_pin_device(dev);
1593
1594         /* Determine the address of the SMBus area */
1595         priv->smba = pci_resource_start(dev, SMBBAR);
1596         if (!priv->smba) {
1597                 dev_err(&dev->dev,
1598                         "SMBus base address uninitialized, upgrade BIOS\n");
1599                 return -ENODEV;
1600         }
1601
1602         if (i801_acpi_probe(priv))
1603                 return -ENODEV;
1604
1605         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1606                                  dev_driver_string(&dev->dev));
1607         if (err) {
1608                 dev_err(&dev->dev,
1609                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1610                         priv->smba,
1611                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1612                 i801_acpi_remove(priv);
1613                 return err;
1614         }
1615
1616         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1617         temp = i801_setup_hstcfg(priv);
1618         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1619                 dev_info(&dev->dev, "Enabling SMBus device\n");
1620
1621         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1622                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1623                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1624                 priv->features &= ~FEATURE_IRQ;
1625         }
1626         if (temp & SMBHSTCFG_SPD_WD)
1627                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1628
1629         /* Clear special mode bits */
1630         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1631                 outb_p(inb_p(SMBAUXCTL(priv)) &
1632                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1633
1634         /* Remember original Host Notify setting */
1635         if (priv->features & FEATURE_HOST_NOTIFY)
1636                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1637
1638         /* Default timeout in interrupt mode: 200 ms */
1639         priv->adapter.timeout = HZ / 5;
1640
1641         if (dev->irq == IRQ_NOTCONNECTED)
1642                 priv->features &= ~FEATURE_IRQ;
1643
1644         if (priv->features & FEATURE_IRQ) {
1645                 u16 pcictl, pcists;
1646
1647                 /* Complain if an interrupt is already pending */
1648                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1649                 if (pcists & SMBPCISTS_INTS)
1650                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1651
1652                 /* Check if interrupts have been disabled */
1653                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1654                 if (pcictl & SMBPCICTL_INTDIS) {
1655                         dev_info(&dev->dev, "Interrupts are disabled\n");
1656                         priv->features &= ~FEATURE_IRQ;
1657                 }
1658         }
1659
1660         if (priv->features & FEATURE_IRQ) {
1661                 init_waitqueue_head(&priv->waitq);
1662
1663                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1664                                        IRQF_SHARED,
1665                                        dev_driver_string(&dev->dev), priv);
1666                 if (err) {
1667                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1668                                 dev->irq, err);
1669                         priv->features &= ~FEATURE_IRQ;
1670                 }
1671         }
1672         dev_info(&dev->dev, "SMBus using %s\n",
1673                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1674
1675         i801_add_tco(priv);
1676
1677         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1678                 "SMBus I801 adapter at %04lx", priv->smba);
1679         err = i2c_add_adapter(&priv->adapter);
1680         if (err) {
1681                 platform_device_unregister(priv->tco_pdev);
1682                 i801_acpi_remove(priv);
1683                 return err;
1684         }
1685
1686         i801_enable_host_notify(&priv->adapter);
1687
1688         i801_probe_optional_slaves(priv);
1689         /* We ignore errors - multiplexing is optional */
1690         i801_add_mux(priv);
1691
1692         pci_set_drvdata(dev, priv);
1693
1694         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NEVER_SKIP);
1695         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1696         pm_runtime_use_autosuspend(&dev->dev);
1697         pm_runtime_put_autosuspend(&dev->dev);
1698         pm_runtime_allow(&dev->dev);
1699
1700         return 0;
1701 }
1702
1703 static void i801_remove(struct pci_dev *dev)
1704 {
1705         struct i801_priv *priv = pci_get_drvdata(dev);
1706
1707         pm_runtime_forbid(&dev->dev);
1708         pm_runtime_get_noresume(&dev->dev);
1709
1710         i801_disable_host_notify(priv);
1711         i801_del_mux(priv);
1712         i2c_del_adapter(&priv->adapter);
1713         i801_acpi_remove(priv);
1714         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1715
1716         platform_device_unregister(priv->tco_pdev);
1717
1718         /*
1719          * do not call pci_disable_device(dev) since it can cause hard hangs on
1720          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1721          */
1722 }
1723
1724 static void i801_shutdown(struct pci_dev *dev)
1725 {
1726         struct i801_priv *priv = pci_get_drvdata(dev);
1727
1728         /* Restore config registers to avoid hard hang on some systems */
1729         i801_disable_host_notify(priv);
1730         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1731 }
1732
1733 #ifdef CONFIG_PM_SLEEP
1734 static int i801_suspend(struct device *dev)
1735 {
1736         struct pci_dev *pci_dev = to_pci_dev(dev);
1737         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1738
1739         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1740         return 0;
1741 }
1742
1743 static int i801_resume(struct device *dev)
1744 {
1745         struct pci_dev *pci_dev = to_pci_dev(dev);
1746         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1747
1748         i801_setup_hstcfg(priv);
1749         i801_enable_host_notify(&priv->adapter);
1750
1751         return 0;
1752 }
1753 #endif
1754
1755 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1756
1757 static struct pci_driver i801_driver = {
1758         .name           = "i801_smbus",
1759         .id_table       = i801_ids,
1760         .probe          = i801_probe,
1761         .remove         = i801_remove,
1762         .shutdown       = i801_shutdown,
1763         .driver         = {
1764                 .pm     = &i801_pm_ops,
1765         },
1766 };
1767
1768 static int __init i2c_i801_init(void)
1769 {
1770         if (dmi_name_in_vendors("FUJITSU"))
1771                 input_apanel_init();
1772         return pci_register_driver(&i801_driver);
1773 }
1774
1775 static void __exit i2c_i801_exit(void)
1776 {
1777         pci_unregister_driver(&i801_driver);
1778 }
1779
1780 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1781 MODULE_DESCRIPTION("I801 SMBus driver");
1782 MODULE_LICENSE("GPL");
1783
1784 module_init(i2c_i801_init);
1785 module_exit(i2c_i801_exit);