drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  68  *
  69  * Features supported by this driver:
  70  * Software PEC                         no
  71  * Hardware PEC                         yes
  72  * Block buffer                         yes
  73  * Block process call transaction       no
  74  * I2C block read transaction           yes (doesn't use the block buffer)
  75  * Slave mode                           no
  76  * SMBus Host Notify                    yes
  77  * Interrupt processing                 yes
  78  *
  79  * See the file Documentation/i2c/busses/i2c-i801 for details.
  80  */
  81
  82 #include <linux/interrupt.h>
  83 #include <linux/module.h>
  84 #include <linux/pci.h>
  85 #include <linux/kernel.h>
  86 #include <linux/stddef.h>
  87 #include <linux/delay.h>
  88 #include <linux/ioport.h>
  89 #include <linux/init.h>
  90 #include <linux/i2c.h>
  91 #include <linux/i2c-smbus.h>
  92 #include <linux/acpi.h>
  93 #include <linux/io.h>
  94 #include <linux/dmi.h>
  95 #include <linux/slab.h>
  96 #include <linux/wait.h>
  97 #include <linux/err.h>
  98 #include <linux/platform_device.h>
  99 #include <linux/platform_data/itco_wdt.h>
 100 #include <linux/pm_runtime.h>
 101
 102 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 103 #include <linux/gpio.h>
 104 #include <linux/i2c-mux-gpio.h>
 105 #endif
 106
 107 /* I801 SMBus address offsets */
 108 #define SMBHSTSTS(p)    (0 + (p)->smba)
 109 #define SMBHSTCNT(p)    (2 + (p)->smba)
 110 #define SMBHSTCMD(p)    (3 + (p)->smba)
 111 #define SMBHSTADD(p)    (4 + (p)->smba)
 112 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 113 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 114 #define SMBBLKDAT(p)    (7 + (p)->smba)
 115 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 116 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 117 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 118 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 119 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 120 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 121 #define SMBNTFDDAT(p)   (22 + (p)->smba)        /* ICH3 and later */
 122
 123 /* PCI Address Constants */
 124 #define SMBBAR          4
 125 #define SMBPCICTL       0x004
 126 #define SMBPCISTS       0x006
 127 #define SMBHSTCFG       0x040
 128 #define TCOBASE         0x050
 129 #define TCOCTL          0x054
 130
 131 #define ACPIBASE                0x040
 132 #define ACPIBASE_SMI_OFF        0x030
 133 #define ACPICTRL                0x044
 134 #define ACPICTRL_EN             0x080
 135
 136 #define SBREG_BAR               0x10
 137 #define SBREG_SMBCTRL           0xc6000c
 138 #define SBREG_SMBCTRL_DNV       0xcf000c
 139
 140 /* Host status bits for SMBPCISTS */
 141 #define SMBPCISTS_INTS          0x08
 142
 143 /* Control bits for SMBPCICTL */
 144 #define SMBPCICTL_INTDIS        0x0400
 145
 146 /* Host configuration bits for SMBHSTCFG */
 147 #define SMBHSTCFG_HST_EN        1
 148 #define SMBHSTCFG_SMB_SMI_EN    2
 149 #define SMBHSTCFG_I2C_EN        4
 150 #define SMBHSTCFG_SPD_WD        0x10
 151
 152 /* TCO configuration bits for TCOCTL */
 153 #define TCOCTL_EN               0x0100
 154
 155 /* Auxiliary status register bits, ICH4+ only */
 156 #define SMBAUXSTS_CRCE          1
 157 #define SMBAUXSTS_STCO          2
 158
 159 /* Auxiliary control register bits, ICH4+ only */
 160 #define SMBAUXCTL_CRC           1
 161 #define SMBAUXCTL_E32B          2
 162
 163 /* Other settings */
 164 #define MAX_RETRIES             400
 165
 166 /* I801 command constants */
 167 #define I801_QUICK              0x00
 168 #define I801_BYTE               0x04
 169 #define I801_BYTE_DATA          0x08
 170 #define I801_WORD_DATA          0x0C
 171 #define I801_PROC_CALL          0x10    /* unimplemented */
 172 #define I801_BLOCK_DATA         0x14
 173 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 174
 175 /* I801 Host Control register bits */
 176 #define SMBHSTCNT_INTREN        0x01
 177 #define SMBHSTCNT_KILL          0x02
 178 #define SMBHSTCNT_LAST_BYTE     0x20
 179 #define SMBHSTCNT_START         0x40
 180 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 181
 182 /* I801 Hosts Status register bits */
 183 #define SMBHSTSTS_BYTE_DONE     0x80
 184 #define SMBHSTSTS_INUSE_STS     0x40
 185 #define SMBHSTSTS_SMBALERT_STS  0x20
 186 #define SMBHSTSTS_FAILED        0x10
 187 #define SMBHSTSTS_BUS_ERR       0x08
 188 #define SMBHSTSTS_DEV_ERR       0x04
 189 #define SMBHSTSTS_INTR          0x02
 190 #define SMBHSTSTS_HOST_BUSY     0x01
 191
 192 /* Host Notify Status registers bits */
 193 #define SMBSLVSTS_HST_NTFY_STS  1
 194
 195 /* Host Notify Command registers bits */
 196 #define SMBSLVCMD_HST_NTFY_INTREN       0x01
 197
 198 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 199                                  SMBHSTSTS_DEV_ERR)
 200
 201 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 202                                  STATUS_ERROR_FLAGS)
 203
 204 /* Older devices have their ID defined in <linux/pci_ids.h> */
 205 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 206 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 207 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 208 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 209 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 213 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 214 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 215 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 216 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 217 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 218 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 219 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 220 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 221 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 222 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 225 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 226 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 227 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 228 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 229 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 230 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 231 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 232 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 233
 234 struct i801_mux_config {
 235         char *gpio_chip;
 236         unsigned values[3];
 237         int n_values;
 238         unsigned classes[3];
 239         unsigned gpios[2];              /* Relative to gpio_chip->base */
 240         int n_gpios;
 241 };
 242
 243 struct i801_priv {
 244         struct i2c_adapter adapter;
 245         unsigned long smba;
 246         unsigned char original_hstcfg;
 247         unsigned char original_slvcmd;
 248         struct pci_dev *pci_dev;
 249         unsigned int features;
 250
 251         /* isr processing */
 252         wait_queue_head_t waitq;
 253         u8 status;
 254
 255         /* Command state used by isr for byte-by-byte block transactions */
 256         u8 cmd;
 257         bool is_read;
 258         int count;
 259         int len;
 260         u8 *data;
 261
 262 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 263         const struct i801_mux_config *mux_drvdata;
 264         struct platform_device *mux_pdev;
 265 #endif
 266         struct platform_device *tco_pdev;
 267
 268         /*
 269          * If set to true the host controller registers are reserved for
 270          * ACPI AML use. Protected by acpi_lock.
 271          */
 272         bool acpi_reserved;
 273         struct mutex acpi_lock;
 274         struct smbus_host_notify *host_notify;
 275 };
 276
 277 #define SMBHSTNTFY_SIZE         8
 278
 279 #define FEATURE_SMBUS_PEC       (1 << 0)
 280 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 281 #define FEATURE_BLOCK_PROC      (1 << 2)
 282 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 283 #define FEATURE_IRQ             (1 << 4)
 284 #define FEATURE_HOST_NOTIFY     (1 << 5)
 285 /* Not really a feature, but it's convenient to handle it as such */
 286 #define FEATURE_IDF             (1 << 15)
 287 #define FEATURE_TCO             (1 << 16)
 288
 289 static const char *i801_feature_names[] = {
 290         "SMBus PEC",
 291         "Block buffer",
 292         "Block process call",
 293         "I2C block read",
 294         "Interrupt",
 295         "SMBus Host Notify",
 296 };
 297
 298 static unsigned int disable_features;
 299 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 300 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 301         "\t\t  0x01  disable SMBus PEC\n"
 302         "\t\t  0x02  disable the block buffer\n"
 303         "\t\t  0x08  disable the I2C block read functionality\n"
 304         "\t\t  0x10  don't use interrupts\n"
 305         "\t\t  0x20  disable SMBus Host Notify ");
 306
 307 /* Make sure the SMBus host is ready to start transmitting.
 308    Return 0 if it is, -EBUSY if it is not. */
 309 static int i801_check_pre(struct i801_priv *priv)
 310 {
 311         int status;
 312
 313         status = inb_p(SMBHSTSTS(priv));
 314         if (status & SMBHSTSTS_HOST_BUSY) {
 315                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 316                 return -EBUSY;
 317         }
 318
 319         status &= STATUS_FLAGS;
 320         if (status) {
 321                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 322                         status);
 323                 outb_p(status, SMBHSTSTS(priv));
 324                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 325                 if (status) {
 326                         dev_err(&priv->pci_dev->dev,
 327                                 "Failed clearing status flags (%02x)\n",
 328                                 status);
 329                         return -EBUSY;
 330                 }
 331         }
 332
 333         /*
 334          * Clear CRC status if needed.
 335          * During normal operation, i801_check_post() takes care
 336          * of it after every operation.  We do it here only in case
 337          * the hardware was already in this state when the driver
 338          * started.
 339          */
 340         if (priv->features & FEATURE_SMBUS_PEC) {
 341                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 342                 if (status) {
 343                         dev_dbg(&priv->pci_dev->dev,
 344                                 "Clearing aux status flags (%02x)\n", status);
 345                         outb_p(status, SMBAUXSTS(priv));
 346                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 347                         if (status) {
 348                                 dev_err(&priv->pci_dev->dev,
 349                                         "Failed clearing aux status flags (%02x)\n",
 350                                         status);
 351                                 return -EBUSY;
 352                         }
 353                 }
 354         }
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Convert the status register to an error code, and clear it.
 361  * Note that status only contains the bits we want to clear, not the
 362  * actual register value.
 363  */
 364 static int i801_check_post(struct i801_priv *priv, int status)
 365 {
 366         int result = 0;
 367
 368         /*
 369          * If the SMBus is still busy, we give up
 370          * Note: This timeout condition only happens when using polling
 371          * transactions.  For interrupt operation, NAK/timeout is indicated by
 372          * DEV_ERR.
 373          */
 374         if (unlikely(status < 0)) {
 375                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 376                 /* try to stop the current command */
 377                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 378                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 379                 usleep_range(1000, 2000);
 380                 outb_p(0, SMBHSTCNT(priv));
 381
 382                 /* Check if it worked */
 383                 status = inb_p(SMBHSTSTS(priv));
 384                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 385                     !(status & SMBHSTSTS_FAILED))
 386                         dev_err(&priv->pci_dev->dev,
 387                                 "Failed terminating the transaction\n");
 388                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 389                 return -ETIMEDOUT;
 390         }
 391
 392         if (status & SMBHSTSTS_FAILED) {
 393                 result = -EIO;
 394                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 395         }
 396         if (status & SMBHSTSTS_DEV_ERR) {
 397                 /*
 398                  * This may be a PEC error, check and clear it.
 399                  *
 400                  * AUXSTS is handled differently from HSTSTS.
 401                  * For HSTSTS, i801_isr() or i801_wait_intr()
 402                  * has already cleared the error bits in hardware,
 403                  * and we are passed a copy of the original value
 404                  * in "status".
 405                  * For AUXSTS, the hardware register is left
 406                  * for us to handle here.
 407                  * This is asymmetric, slightly iffy, but safe,
 408                  * since all this code is serialized and the CRCE
 409                  * bit is harmless as long as it's cleared before
 410                  * the next operation.
 411                  */
 412                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 413                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 414                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 415                         result = -EBADMSG;
 416                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 417                 } else {
 418                         result = -ENXIO;
 419                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 420                 }
 421         }
 422         if (status & SMBHSTSTS_BUS_ERR) {
 423                 result = -EAGAIN;
 424                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 425         }
 426
 427         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 428         outb_p(status, SMBHSTSTS(priv));
 429
 430         return result;
 431 }
 432
 433 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 434 static int i801_wait_intr(struct i801_priv *priv)
 435 {
 436         int timeout = 0;
 437         int status;
 438
 439         /* We will always wait for a fraction of a second! */
 440         do {
 441                 usleep_range(250, 500);
 442                 status = inb_p(SMBHSTSTS(priv));
 443         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 444                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 445                  (timeout++ < MAX_RETRIES));
 446
 447         if (timeout > MAX_RETRIES) {
 448                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 449                 return -ETIMEDOUT;
 450         }
 451         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 452 }
 453
 454 /* Wait for either BYTE_DONE or an error flag being set */
 455 static int i801_wait_byte_done(struct i801_priv *priv)
 456 {
 457         int timeout = 0;
 458         int status;
 459
 460         /* We will always wait for a fraction of a second! */
 461         do {
 462                 usleep_range(250, 500);
 463                 status = inb_p(SMBHSTSTS(priv));
 464         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 465                  (timeout++ < MAX_RETRIES));
 466
 467         if (timeout > MAX_RETRIES) {
 468                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 469                 return -ETIMEDOUT;
 470         }
 471         return status & STATUS_ERROR_FLAGS;
 472 }
 473
 474 static int i801_transaction(struct i801_priv *priv, int xact)
 475 {
 476         int status;
 477         int result;
 478         const struct i2c_adapter *adap = &priv->adapter;
 479
 480         result = i801_check_pre(priv);
 481         if (result < 0)
 482                 return result;
 483
 484         if (priv->features & FEATURE_IRQ) {
 485                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 486                        SMBHSTCNT(priv));
 487                 result = wait_event_timeout(priv->waitq,
 488                                             (status = priv->status),
 489                                             adap->timeout);
 490                 if (!result) {
 491                         status = -ETIMEDOUT;
 492                         dev_warn(&priv->pci_dev->dev,
 493                                  "Timeout waiting for interrupt!\n");
 494                 }
 495                 priv->status = 0;
 496                 return i801_check_post(priv, status);
 497         }
 498
 499         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 500          * SMBSCMD are passed in xact */
 501         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 502
 503         status = i801_wait_intr(priv);
 504         return i801_check_post(priv, status);
 505 }
 506
 507 static int i801_block_transaction_by_block(struct i801_priv *priv,
 508                                            union i2c_smbus_data *data,
 509                                            char read_write, int hwpec)
 510 {
 511         int i, len;
 512         int status;
 513
 514         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 515
 516         /* Use 32-byte buffer to process this transaction */
 517         if (read_write == I2C_SMBUS_WRITE) {
 518                 len = data->block[0];
 519                 outb_p(len, SMBHSTDAT0(priv));
 520                 for (i = 0; i < len; i++)
 521                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 522         }
 523
 524         status = i801_transaction(priv, I801_BLOCK_DATA |
 525                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 526         if (status)
 527                 return status;
 528
 529         if (read_write == I2C_SMBUS_READ) {
 530                 len = inb_p(SMBHSTDAT0(priv));
 531                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 532                         return -EPROTO;
 533
 534                 data->block[0] = len;
 535                 for (i = 0; i < len; i++)
 536                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 537         }
 538         return 0;
 539 }
 540
 541 static void i801_isr_byte_done(struct i801_priv *priv)
 542 {
 543         if (priv->is_read) {
 544                 /* For SMBus block reads, length is received with first byte */
 545                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 546                     (priv->count == 0)) {
 547                         priv->len = inb_p(SMBHSTDAT0(priv));
 548                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 549                                 dev_err(&priv->pci_dev->dev,
 550                                         "Illegal SMBus block read size %d\n",
 551                                         priv->len);
 552                                 /* FIXME: Recover */
 553                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 554                         } else {
 555                                 dev_dbg(&priv->pci_dev->dev,
 556                                         "SMBus block read size is %d\n",
 557                                         priv->len);
 558                         }
 559                         priv->data[-1] = priv->len;
 560                 }
 561
 562                 /* Read next byte */
 563                 if (priv->count < priv->len)
 564                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 565                 else
 566                         dev_dbg(&priv->pci_dev->dev,
 567                                 "Discarding extra byte on block read\n");
 568
 569                 /* Set LAST_BYTE for last byte of read transaction */
 570                 if (priv->count == priv->len - 1)
 571                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 572                                SMBHSTCNT(priv));
 573         } else if (priv->count < priv->len - 1) {
 574                 /* Write next byte, except for IRQ after last byte */
 575                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 576         }
 577
 578         /* Clear BYTE_DONE to continue with next byte */
 579         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 580 }
 581
 582 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 583 {
 584         unsigned short addr;
 585         unsigned int data;
 586
 587         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 588         data = inw_p(SMBNTFDDAT(priv));
 589
 590         i2c_handle_smbus_host_notify(priv->host_notify, addr, data);
 591
 592         /* clear Host Notify bit and return */
 593         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 594         return IRQ_HANDLED;
 595 }
 596
 597 /*
 598  * There are three kinds of interrupts:
 599  *
 600  * 1) i801 signals transaction completion with one of these interrupts:
 601  *      INTR - Success
 602  *      DEV_ERR - Invalid command, NAK or communication timeout
 603  *      BUS_ERR - SMI# transaction collision
 604  *      FAILED - transaction was canceled due to a KILL request
 605  *    When any of these occur, update ->status and wake up the waitq.
 606  *    ->status must be cleared before kicking off the next transaction.
 607  *
 608  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 609  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 610  *
 611  * 3) Host Notify interrupts
 612  */
 613 static irqreturn_t i801_isr(int irq, void *dev_id)
 614 {
 615         struct i801_priv *priv = dev_id;
 616         u16 pcists;
 617         u8 status;
 618
 619         /* Confirm this is our interrupt */
 620         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 621         if (!(pcists & SMBPCISTS_INTS))
 622                 return IRQ_NONE;
 623
 624         if (priv->features & FEATURE_HOST_NOTIFY) {
 625                 status = inb_p(SMBSLVSTS(priv));
 626                 if (status & SMBSLVSTS_HST_NTFY_STS)
 627                         return i801_host_notify_isr(priv);
 628         }
 629
 630         status = inb_p(SMBHSTSTS(priv));
 631         if (status & SMBHSTSTS_BYTE_DONE)
 632                 i801_isr_byte_done(priv);
 633
 634         /*
 635          * Clear irq sources and report transaction result.
 636          * ->status must be cleared before the next transaction is started.
 637          */
 638         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 639         if (status) {
 640                 outb_p(status, SMBHSTSTS(priv));
 641                 priv->status = status;
 642                 wake_up(&priv->waitq);
 643         }
 644
 645         return IRQ_HANDLED;
 646 }
 647
 648 /*
 649  * For "byte-by-byte" block transactions:
 650  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 651  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 652  */
 653 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 654                                                union i2c_smbus_data *data,
 655                                                char read_write, int command,
 656                                                int hwpec)
 657 {
 658         int i, len;
 659         int smbcmd;
 660         int status;
 661         int result;
 662         const struct i2c_adapter *adap = &priv->adapter;
 663
 664         result = i801_check_pre(priv);
 665         if (result < 0)
 666                 return result;
 667
 668         len = data->block[0];
 669
 670         if (read_write == I2C_SMBUS_WRITE) {
 671                 outb_p(len, SMBHSTDAT0(priv));
 672                 outb_p(data->block[1], SMBBLKDAT(priv));
 673         }
 674
 675         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 676             read_write == I2C_SMBUS_READ)
 677                 smbcmd = I801_I2C_BLOCK_DATA;
 678         else
 679                 smbcmd = I801_BLOCK_DATA;
 680
 681         if (priv->features & FEATURE_IRQ) {
 682                 priv->is_read = (read_write == I2C_SMBUS_READ);
 683                 if (len == 1 && priv->is_read)
 684                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 685                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 686                 priv->len = len;
 687                 priv->count = 0;
 688                 priv->data = &data->block[1];
 689
 690                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 691                 result = wait_event_timeout(priv->waitq,
 692                                             (status = priv->status),
 693                                             adap->timeout);
 694                 if (!result) {
 695                         status = -ETIMEDOUT;
 696                         dev_warn(&priv->pci_dev->dev,
 697                                  "Timeout waiting for interrupt!\n");
 698                 }
 699                 priv->status = 0;
 700                 return i801_check_post(priv, status);
 701         }
 702
 703         for (i = 1; i <= len; i++) {
 704                 if (i == len && read_write == I2C_SMBUS_READ)
 705                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 706                 outb_p(smbcmd, SMBHSTCNT(priv));
 707
 708                 if (i == 1)
 709                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 710                                SMBHSTCNT(priv));
 711
 712                 status = i801_wait_byte_done(priv);
 713                 if (status)
 714                         goto exit;
 715
 716                 if (i == 1 && read_write == I2C_SMBUS_READ
 717                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 718                         len = inb_p(SMBHSTDAT0(priv));
 719                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 720                                 dev_err(&priv->pci_dev->dev,
 721                                         "Illegal SMBus block read size %d\n",
 722                                         len);
 723                                 /* Recover */
 724                                 while (inb_p(SMBHSTSTS(priv)) &
 725                                        SMBHSTSTS_HOST_BUSY)
 726                                         outb_p(SMBHSTSTS_BYTE_DONE,
 727                                                SMBHSTSTS(priv));
 728                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 729                                 return -EPROTO;
 730                         }
 731                         data->block[0] = len;
 732                 }
 733
 734                 /* Retrieve/store value in SMBBLKDAT */
 735                 if (read_write == I2C_SMBUS_READ)
 736                         data->block[i] = inb_p(SMBBLKDAT(priv));
 737                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 738                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 739
 740                 /* signals SMBBLKDAT ready */
 741                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 742         }
 743
 744         status = i801_wait_intr(priv);
 745 exit:
 746         return i801_check_post(priv, status);
 747 }
 748
 749 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 750 {
 751         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 752         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 753                 return -EIO;
 754         return 0;
 755 }
 756
 757 /* Block transaction function */
 758 static int i801_block_transaction(struct i801_priv *priv,
 759                                   union i2c_smbus_data *data, char read_write,
 760                                   int command, int hwpec)
 761 {
 762         int result = 0;
 763         unsigned char hostc;
 764
 765         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 766                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 767         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 768                 return -EPROTO;
 769
 770         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 771                 if (read_write == I2C_SMBUS_WRITE) {
 772                         /* set I2C_EN bit in configuration register */
 773                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 774                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 775                                               hostc | SMBHSTCFG_I2C_EN);
 776                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 777                         dev_err(&priv->pci_dev->dev,
 778                                 "I2C block read is unsupported!\n");
 779                         return -EOPNOTSUPP;
 780                 }
 781         }
 782
 783         /* Experience has shown that the block buffer can only be used for
 784            SMBus (not I2C) block transactions, even though the datasheet
 785            doesn't mention this limitation. */
 786         if ((priv->features & FEATURE_BLOCK_BUFFER)
 787          && command != I2C_SMBUS_I2C_BLOCK_DATA
 788          && i801_set_block_buffer_mode(priv) == 0)
 789                 result = i801_block_transaction_by_block(priv, data,
 790                                                          read_write, hwpec);
 791         else
 792                 result = i801_block_transaction_byte_by_byte(priv, data,
 793                                                              read_write,
 794                                                              command, hwpec);
 795
 796         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 797          && read_write == I2C_SMBUS_WRITE) {
 798                 /* restore saved configuration register value */
 799                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 800         }
 801         return result;
 802 }
 803
 804 /* Return negative errno on error. */
 805 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 806                        unsigned short flags, char read_write, u8 command,
 807                        int size, union i2c_smbus_data *data)
 808 {
 809         int hwpec;
 810         int block = 0;
 811         int ret = 0, xact = 0;
 812         struct i801_priv *priv = i2c_get_adapdata(adap);
 813
 814         mutex_lock(&priv->acpi_lock);
 815         if (priv->acpi_reserved) {
 816                 mutex_unlock(&priv->acpi_lock);
 817                 return -EBUSY;
 818         }
 819
 820         pm_runtime_get_sync(&priv->pci_dev->dev);
 821
 822         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 823                 && size != I2C_SMBUS_QUICK
 824                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 825
 826         switch (size) {
 827         case I2C_SMBUS_QUICK:
 828                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 829                        SMBHSTADD(priv));
 830                 xact = I801_QUICK;
 831                 break;
 832         case I2C_SMBUS_BYTE:
 833                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 834                        SMBHSTADD(priv));
 835                 if (read_write == I2C_SMBUS_WRITE)
 836                         outb_p(command, SMBHSTCMD(priv));
 837                 xact = I801_BYTE;
 838                 break;
 839         case I2C_SMBUS_BYTE_DATA:
 840                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 841                        SMBHSTADD(priv));
 842                 outb_p(command, SMBHSTCMD(priv));
 843                 if (read_write == I2C_SMBUS_WRITE)
 844                         outb_p(data->byte, SMBHSTDAT0(priv));
 845                 xact = I801_BYTE_DATA;
 846                 break;
 847         case I2C_SMBUS_WORD_DATA:
 848                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 849                        SMBHSTADD(priv));
 850                 outb_p(command, SMBHSTCMD(priv));
 851                 if (read_write == I2C_SMBUS_WRITE) {
 852                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 853                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 854                 }
 855                 xact = I801_WORD_DATA;
 856                 break;
 857         case I2C_SMBUS_BLOCK_DATA:
 858                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 859                        SMBHSTADD(priv));
 860                 outb_p(command, SMBHSTCMD(priv));
 861                 block = 1;
 862                 break;
 863         case I2C_SMBUS_I2C_BLOCK_DATA:
 864                 /*
 865                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 866                  * bit should be cleared here, even when reading.
 867                  * However if SPD Write Disable is set (Lynx Point and later),
 868                  * the read will fail if we don't set the R/#W bit.
 869                  */
 870                 outb_p(((addr & 0x7f) << 1) |
 871                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 872                         (read_write & 0x01) : 0),
 873                        SMBHSTADD(priv));
 874                 if (read_write == I2C_SMBUS_READ) {
 875                         /* NB: page 240 of ICH5 datasheet also shows
 876                          * that DATA1 is the cmd field when reading */
 877                         outb_p(command, SMBHSTDAT1(priv));
 878                 } else
 879                         outb_p(command, SMBHSTCMD(priv));
 880                 block = 1;
 881                 break;
 882         default:
 883                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 884                         size);
 885                 ret = -EOPNOTSUPP;
 886                 goto out;
 887         }
 888
 889         if (hwpec)      /* enable/disable hardware PEC */
 890                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 891         else
 892                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 893                        SMBAUXCTL(priv));
 894
 895         if (block)
 896                 ret = i801_block_transaction(priv, data, read_write, size,
 897                                              hwpec);
 898         else
 899                 ret = i801_transaction(priv, xact);
 900
 901         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 902            time, so we forcibly disable it after every transaction. Turn off
 903            E32B for the same reason. */
 904         if (hwpec || block)
 905                 outb_p(inb_p(SMBAUXCTL(priv)) &
 906                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 907
 908         if (block)
 909                 goto out;
 910         if (ret)
 911                 goto out;
 912         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 913                 goto out;
 914
 915         switch (xact & 0x7f) {
 916         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 917         case I801_BYTE_DATA:
 918                 data->byte = inb_p(SMBHSTDAT0(priv));
 919                 break;
 920         case I801_WORD_DATA:
 921                 data->word = inb_p(SMBHSTDAT0(priv)) +
 922                              (inb_p(SMBHSTDAT1(priv)) << 8);
 923                 break;
 924         }
 925
 926 out:
 927         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 928         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 929         mutex_unlock(&priv->acpi_lock);
 930         return ret;
 931 }
 932
 933
 934 static u32 i801_func(struct i2c_adapter *adapter)
 935 {
 936         struct i801_priv *priv = i2c_get_adapdata(adapter);
 937
 938         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 939                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 940                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 941                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 942                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 943                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 944                ((priv->features & FEATURE_HOST_NOTIFY) ?
 945                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 946 }
 947
 948 static int i801_enable_host_notify(struct i2c_adapter *adapter)
 949 {
 950         struct i801_priv *priv = i2c_get_adapdata(adapter);
 951
 952         if (!(priv->features & FEATURE_HOST_NOTIFY))
 953                 return -ENOTSUPP;
 954
 955         if (!priv->host_notify)
 956                 priv->host_notify = i2c_setup_smbus_host_notify(adapter);
 957         if (!priv->host_notify)
 958                 return -ENOMEM;
 959
 960         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 961                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 962                        SMBSLVCMD(priv));
 963
 964         /* clear Host Notify bit to allow a new notification */
 965         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 966
 967         return 0;
 968 }
 969
 970 static void i801_disable_host_notify(struct i801_priv *priv)
 971 {
 972         if (!(priv->features & FEATURE_HOST_NOTIFY))
 973                 return;
 974
 975         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 976 }
 977
 978 static const struct i2c_algorithm smbus_algorithm = {
 979         .smbus_xfer     = i801_access,
 980         .functionality  = i801_func,
 981 };
 982
 983 static const struct pci_device_id i801_ids[] = {
 984         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 985         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 986         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 987         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 988         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 989         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 990         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 991         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 992         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 993         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1012         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1013         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1014         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1015         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1016         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1017         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1018         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1026         { 0, }
1027 };
1028
1029 MODULE_DEVICE_TABLE(pci, i801_ids);
1030
1031 #if defined CONFIG_X86 && defined CONFIG_DMI
1032 static unsigned char apanel_addr;
1033
1034 /* Scan the system ROM for the signature "FJKEYINF" */
1035 static __init const void __iomem *bios_signature(const void __iomem *bios)
1036 {
1037         ssize_t offset;
1038         const unsigned char signature[] = "FJKEYINF";
1039
1040         for (offset = 0; offset < 0x10000; offset += 0x10) {
1041                 if (check_signature(bios + offset, signature,
1042                                     sizeof(signature)-1))
1043                         return bios + offset;
1044         }
1045         return NULL;
1046 }
1047
1048 static void __init input_apanel_init(void)
1049 {
1050         void __iomem *bios;
1051         const void __iomem *p;
1052
1053         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1054         p = bios_signature(bios);
1055         if (p) {
1056                 /* just use the first address */
1057                 apanel_addr = readb(p + 8 + 3) >> 1;
1058         }
1059         iounmap(bios);
1060 }
1061
1062 struct dmi_onboard_device_info {
1063         const char *name;
1064         u8 type;
1065         unsigned short i2c_addr;
1066         const char *i2c_type;
1067 };
1068
1069 static const struct dmi_onboard_device_info dmi_devices[] = {
1070         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1071         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1072         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1073 };
1074
1075 static void dmi_check_onboard_device(u8 type, const char *name,
1076                                      struct i2c_adapter *adap)
1077 {
1078         int i;
1079         struct i2c_board_info info;
1080
1081         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1082                 /* & ~0x80, ignore enabled/disabled bit */
1083                 if ((type & ~0x80) != dmi_devices[i].type)
1084                         continue;
1085                 if (strcasecmp(name, dmi_devices[i].name))
1086                         continue;
1087
1088                 memset(&info, 0, sizeof(struct i2c_board_info));
1089                 info.addr = dmi_devices[i].i2c_addr;
1090                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1091                 i2c_new_device(adap, &info);
1092                 break;
1093         }
1094 }
1095
1096 /* We use our own function to check for onboard devices instead of
1097    dmi_find_device() as some buggy BIOS's have the devices we are interested
1098    in marked as disabled */
1099 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1100 {
1101         int i, count;
1102
1103         if (dm->type != 10)
1104                 return;
1105
1106         count = (dm->length - sizeof(struct dmi_header)) / 2;
1107         for (i = 0; i < count; i++) {
1108                 const u8 *d = (char *)(dm + 1) + (i * 2);
1109                 const char *name = ((char *) dm) + dm->length;
1110                 u8 type = d[0];
1111                 u8 s = d[1];
1112
1113                 if (!s)
1114                         continue;
1115                 s--;
1116                 while (s > 0 && name[0]) {
1117                         name += strlen(name) + 1;
1118                         s--;
1119                 }
1120                 if (name[0] == 0) /* Bogus string reference */
1121                         continue;
1122
1123                 dmi_check_onboard_device(type, name, adap);
1124         }
1125 }
1126
1127 /* Register optional slaves */
1128 static void i801_probe_optional_slaves(struct i801_priv *priv)
1129 {
1130         /* Only register slaves on main SMBus channel */
1131         if (priv->features & FEATURE_IDF)
1132                 return;
1133
1134         if (apanel_addr) {
1135                 struct i2c_board_info info;
1136
1137                 memset(&info, 0, sizeof(struct i2c_board_info));
1138                 info.addr = apanel_addr;
1139                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1140                 i2c_new_device(&priv->adapter, &info);
1141         }
1142
1143         if (dmi_name_in_vendors("FUJITSU"))
1144                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1145 }
1146 #else
1147 static void __init input_apanel_init(void) {}
1148 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1149 #endif  /* CONFIG_X86 && CONFIG_DMI */
1150
1151 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1152 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1153         .gpio_chip = "gpio_ich",
1154         .values = { 0x02, 0x03 },
1155         .n_values = 2,
1156         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1157         .gpios = { 52, 53 },
1158         .n_gpios = 2,
1159 };
1160
1161 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1162         .gpio_chip = "gpio_ich",
1163         .values = { 0x02, 0x03, 0x01 },
1164         .n_values = 3,
1165         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1166         .gpios = { 52, 53 },
1167         .n_gpios = 2,
1168 };
1169
1170 static const struct dmi_system_id mux_dmi_table[] = {
1171         {
1172                 .matches = {
1173                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1174                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1175                 },
1176                 .driver_data = &i801_mux_config_asus_z8_d12,
1177         },
1178         {
1179                 .matches = {
1180                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1181                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1182                 },
1183                 .driver_data = &i801_mux_config_asus_z8_d12,
1184         },
1185         {
1186                 .matches = {
1187                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1188                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1189                 },
1190                 .driver_data = &i801_mux_config_asus_z8_d12,
1191         },
1192         {
1193                 .matches = {
1194                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1195                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1196                 },
1197                 .driver_data = &i801_mux_config_asus_z8_d12,
1198         },
1199         {
1200                 .matches = {
1201                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1202                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1203                 },
1204                 .driver_data = &i801_mux_config_asus_z8_d12,
1205         },
1206         {
1207                 .matches = {
1208                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1209                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1210                 },
1211                 .driver_data = &i801_mux_config_asus_z8_d12,
1212         },
1213         {
1214                 .matches = {
1215                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1216                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1217                 },
1218                 .driver_data = &i801_mux_config_asus_z8_d18,
1219         },
1220         {
1221                 .matches = {
1222                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1223                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1224                 },
1225                 .driver_data = &i801_mux_config_asus_z8_d18,
1226         },
1227         {
1228                 .matches = {
1229                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1230                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1231                 },
1232                 .driver_data = &i801_mux_config_asus_z8_d12,
1233         },
1234         { }
1235 };
1236
1237 /* Setup multiplexing if needed */
1238 static int i801_add_mux(struct i801_priv *priv)
1239 {
1240         struct device *dev = &priv->adapter.dev;
1241         const struct i801_mux_config *mux_config;
1242         struct i2c_mux_gpio_platform_data gpio_data;
1243         int err;
1244
1245         if (!priv->mux_drvdata)
1246                 return 0;
1247         mux_config = priv->mux_drvdata;
1248
1249         /* Prepare the platform data */
1250         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1251         gpio_data.parent = priv->adapter.nr;
1252         gpio_data.values = mux_config->values;
1253         gpio_data.n_values = mux_config->n_values;
1254         gpio_data.classes = mux_config->classes;
1255         gpio_data.gpio_chip = mux_config->gpio_chip;
1256         gpio_data.gpios = mux_config->gpios;
1257         gpio_data.n_gpios = mux_config->n_gpios;
1258         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1259
1260         /* Register the mux device */
1261         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1262                                 PLATFORM_DEVID_AUTO, &gpio_data,
1263                                 sizeof(struct i2c_mux_gpio_platform_data));
1264         if (IS_ERR(priv->mux_pdev)) {
1265                 err = PTR_ERR(priv->mux_pdev);
1266                 priv->mux_pdev = NULL;
1267                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1268                 return err;
1269         }
1270
1271         return 0;
1272 }
1273
1274 static void i801_del_mux(struct i801_priv *priv)
1275 {
1276         if (priv->mux_pdev)
1277                 platform_device_unregister(priv->mux_pdev);
1278 }
1279
1280 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1281 {
1282         const struct dmi_system_id *id;
1283         const struct i801_mux_config *mux_config;
1284         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1285         int i;
1286
1287         id = dmi_first_match(mux_dmi_table);
1288         if (id) {
1289                 /* Remove branch classes from trunk */
1290                 mux_config = id->driver_data;
1291                 for (i = 0; i < mux_config->n_values; i++)
1292                         class &= ~mux_config->classes[i];
1293
1294                 /* Remember for later */
1295                 priv->mux_drvdata = mux_config;
1296         }
1297
1298         return class;
1299 }
1300 #else
1301 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1302 static inline void i801_del_mux(struct i801_priv *priv) { }
1303
1304 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1305 {
1306         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1307 }
1308 #endif
1309
1310 static const struct itco_wdt_platform_data tco_platform_data = {
1311         .name = "Intel PCH",
1312         .version = 4,
1313 };
1314
1315 static DEFINE_SPINLOCK(p2sb_spinlock);
1316
1317 static void i801_add_tco(struct i801_priv *priv)
1318 {
1319         struct pci_dev *pci_dev = priv->pci_dev;
1320         struct resource tco_res[3], *res;
1321         struct platform_device *pdev;
1322         unsigned int devfn;
1323         u32 tco_base, tco_ctl;
1324         u32 base_addr, ctrl_val;
1325         u64 base64_addr;
1326
1327         if (!(priv->features & FEATURE_TCO))
1328                 return;
1329
1330         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1331         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1332         if (!(tco_ctl & TCOCTL_EN))
1333                 return;
1334
1335         memset(tco_res, 0, sizeof(tco_res));
1336
1337         res = &tco_res[ICH_RES_IO_TCO];
1338         res->start = tco_base & ~1;
1339         res->end = res->start + 32 - 1;
1340         res->flags = IORESOURCE_IO;
1341
1342         /*
1343          * Power Management registers.
1344          */
1345         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1346         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1347
1348         res = &tco_res[ICH_RES_IO_SMI];
1349         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1350         res->end = res->start + 3;
1351         res->flags = IORESOURCE_IO;
1352
1353         /*
1354          * Enable the ACPI I/O space.
1355          */
1356         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1357         ctrl_val |= ACPICTRL_EN;
1358         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1359
1360         /*
1361          * We must access the NO_REBOOT bit over the Primary to Sideband
1362          * bridge (P2SB). The BIOS prevents the P2SB device from being
1363          * enumerated by the PCI subsystem, so we need to unhide/hide it
1364          * to lookup the P2SB BAR.
1365          */
1366         spin_lock(&p2sb_spinlock);
1367
1368         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1369
1370         /* Unhide the P2SB device */
1371         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1372
1373         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1374         base64_addr = base_addr & 0xfffffff0;
1375
1376         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1377         base64_addr |= (u64)base_addr << 32;
1378
1379         /* Hide the P2SB device */
1380         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1381         spin_unlock(&p2sb_spinlock);
1382
1383         res = &tco_res[ICH_RES_MEM_OFF];
1384         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1385                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1386         else
1387                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1388
1389         res->end = res->start + 3;
1390         res->flags = IORESOURCE_MEM;
1391
1392         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1393                                                  tco_res, 3, &tco_platform_data,
1394                                                  sizeof(tco_platform_data));
1395         if (IS_ERR(pdev)) {
1396                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1397                 return;
1398         }
1399
1400         priv->tco_pdev = pdev;
1401 }
1402
1403 #ifdef CONFIG_ACPI
1404 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1405                                       acpi_physical_address address)
1406 {
1407         return address >= priv->smba &&
1408                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1409 }
1410
1411 static acpi_status
1412 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1413                      u64 *value, void *handler_context, void *region_context)
1414 {
1415         struct i801_priv *priv = handler_context;
1416         struct pci_dev *pdev = priv->pci_dev;
1417         acpi_status status;
1418
1419         /*
1420          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1421          * further access from the driver itself. This device is now owned
1422          * by the system firmware.
1423          */
1424         mutex_lock(&priv->acpi_lock);
1425
1426         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1427                 priv->acpi_reserved = true;
1428
1429                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1430                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1431
1432                 /*
1433                  * BIOS is accessing the host controller so prevent it from
1434                  * suspending automatically from now on.
1435                  */
1436                 pm_runtime_get_sync(&pdev->dev);
1437         }
1438
1439         if ((function & ACPI_IO_MASK) == ACPI_READ)
1440                 status = acpi_os_read_port(address, (u32 *)value, bits);
1441         else
1442                 status = acpi_os_write_port(address, (u32)*value, bits);
1443
1444         mutex_unlock(&priv->acpi_lock);
1445
1446         return status;
1447 }
1448
1449 static int i801_acpi_probe(struct i801_priv *priv)
1450 {
1451         struct acpi_device *adev;
1452         acpi_status status;
1453
1454         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1455         if (adev) {
1456                 status = acpi_install_address_space_handler(adev->handle,
1457                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1458                                 NULL, priv);
1459                 if (ACPI_SUCCESS(status))
1460                         return 0;
1461         }
1462
1463         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1464 }
1465
1466 static void i801_acpi_remove(struct i801_priv *priv)
1467 {
1468         struct acpi_device *adev;
1469
1470         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1471         if (!adev)
1472                 return;
1473
1474         acpi_remove_address_space_handler(adev->handle,
1475                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1476
1477         mutex_lock(&priv->acpi_lock);
1478         if (priv->acpi_reserved)
1479                 pm_runtime_put(&priv->pci_dev->dev);
1480         mutex_unlock(&priv->acpi_lock);
1481 }
1482 #else
1483 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1484 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1485 #endif
1486
1487 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1488 {
1489         unsigned char temp;
1490         int err, i;
1491         struct i801_priv *priv;
1492
1493         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1494         if (!priv)
1495                 return -ENOMEM;
1496
1497         i2c_set_adapdata(&priv->adapter, priv);
1498         priv->adapter.owner = THIS_MODULE;
1499         priv->adapter.class = i801_get_adapter_class(priv);
1500         priv->adapter.algo = &smbus_algorithm;
1501         priv->adapter.dev.parent = &dev->dev;
1502         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1503         priv->adapter.retries = 3;
1504         mutex_init(&priv->acpi_lock);
1505
1506         priv->pci_dev = dev;
1507         switch (dev->device) {
1508         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1509         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1510         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1511         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1512         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1513         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1514                 priv->features |= FEATURE_I2C_BLOCK_READ;
1515                 priv->features |= FEATURE_IRQ;
1516                 priv->features |= FEATURE_SMBUS_PEC;
1517                 priv->features |= FEATURE_BLOCK_BUFFER;
1518                 /* If we have ACPI based watchdog use that instead */
1519                 if (!acpi_has_watchdog())
1520                         priv->features |= FEATURE_TCO;
1521                 priv->features |= FEATURE_HOST_NOTIFY;
1522                 break;
1523
1524         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1525         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1526         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1527         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1528         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1529         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1530                 priv->features |= FEATURE_IDF;
1531                 /* fall through */
1532         default:
1533                 priv->features |= FEATURE_I2C_BLOCK_READ;
1534                 priv->features |= FEATURE_IRQ;
1535                 /* fall through */
1536         case PCI_DEVICE_ID_INTEL_82801DB_3:
1537                 priv->features |= FEATURE_SMBUS_PEC;
1538                 priv->features |= FEATURE_BLOCK_BUFFER;
1539                 /* fall through */
1540         case PCI_DEVICE_ID_INTEL_82801CA_3:
1541                 priv->features |= FEATURE_HOST_NOTIFY;
1542                 /* fall through */
1543         case PCI_DEVICE_ID_INTEL_82801BA_2:
1544         case PCI_DEVICE_ID_INTEL_82801AB_3:
1545         case PCI_DEVICE_ID_INTEL_82801AA_3:
1546                 break;
1547         }
1548
1549         /* Disable features on user request */
1550         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1551                 if (priv->features & disable_features & (1 << i))
1552                         dev_notice(&dev->dev, "%s disabled by user\n",
1553                                    i801_feature_names[i]);
1554         }
1555         priv->features &= ~disable_features;
1556
1557         err = pcim_enable_device(dev);
1558         if (err) {
1559                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1560                         err);
1561                 return err;
1562         }
1563         pcim_pin_device(dev);
1564
1565         /* Determine the address of the SMBus area */
1566         priv->smba = pci_resource_start(dev, SMBBAR);
1567         if (!priv->smba) {
1568                 dev_err(&dev->dev,
1569                         "SMBus base address uninitialized, upgrade BIOS\n");
1570                 return -ENODEV;
1571         }
1572
1573         if (i801_acpi_probe(priv))
1574                 return -ENODEV;
1575
1576         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1577                                  dev_driver_string(&dev->dev));
1578         if (err) {
1579                 dev_err(&dev->dev,
1580                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1581                         priv->smba,
1582                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1583                 i801_acpi_remove(priv);
1584                 return err;
1585         }
1586
1587         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1588         priv->original_hstcfg = temp;
1589         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1590         if (!(temp & SMBHSTCFG_HST_EN)) {
1591                 dev_info(&dev->dev, "Enabling SMBus device\n");
1592                 temp |= SMBHSTCFG_HST_EN;
1593         }
1594         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1595
1596         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1597                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1598                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1599                 priv->features &= ~FEATURE_IRQ;
1600         }
1601         if (temp & SMBHSTCFG_SPD_WD)
1602                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1603
1604         /* Clear special mode bits */
1605         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1606                 outb_p(inb_p(SMBAUXCTL(priv)) &
1607                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1608
1609         /* Remember original Host Notify setting */
1610         if (priv->features & FEATURE_HOST_NOTIFY)
1611                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1612
1613         /* Default timeout in interrupt mode: 200 ms */
1614         priv->adapter.timeout = HZ / 5;
1615
1616         if (dev->irq == IRQ_NOTCONNECTED)
1617                 priv->features &= ~FEATURE_IRQ;
1618
1619         if (priv->features & FEATURE_IRQ) {
1620                 u16 pcictl, pcists;
1621
1622                 /* Complain if an interrupt is already pending */
1623                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1624                 if (pcists & SMBPCISTS_INTS)
1625                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1626
1627                 /* Check if interrupts have been disabled */
1628                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1629                 if (pcictl & SMBPCICTL_INTDIS) {
1630                         dev_info(&dev->dev, "Interrupts are disabled\n");
1631                         priv->features &= ~FEATURE_IRQ;
1632                 }
1633         }
1634
1635         if (priv->features & FEATURE_IRQ) {
1636                 init_waitqueue_head(&priv->waitq);
1637
1638                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1639                                        IRQF_SHARED,
1640                                        dev_driver_string(&dev->dev), priv);
1641                 if (err) {
1642                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1643                                 dev->irq, err);
1644                         priv->features &= ~FEATURE_IRQ;
1645                 }
1646         }
1647         dev_info(&dev->dev, "SMBus using %s\n",
1648                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1649
1650         i801_add_tco(priv);
1651
1652         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1653                 "SMBus I801 adapter at %04lx", priv->smba);
1654         err = i2c_add_adapter(&priv->adapter);
1655         if (err) {
1656                 i801_acpi_remove(priv);
1657                 return err;
1658         }
1659
1660         /*
1661          * Enable Host Notify for chips that supports it.
1662          * It is done after i2c_add_adapter() so that we are sure the work queue
1663          * is not used if i2c_add_adapter() fails.
1664          */
1665         err = i801_enable_host_notify(&priv->adapter);
1666         if (err && err != -ENOTSUPP)
1667                 dev_warn(&dev->dev, "Unable to enable SMBus Host Notify\n");
1668
1669         i801_probe_optional_slaves(priv);
1670         /* We ignore errors - multiplexing is optional */
1671         i801_add_mux(priv);
1672
1673         pci_set_drvdata(dev, priv);
1674
1675         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1676         pm_runtime_use_autosuspend(&dev->dev);
1677         pm_runtime_put_autosuspend(&dev->dev);
1678         pm_runtime_allow(&dev->dev);
1679
1680         return 0;
1681 }
1682
1683 static void i801_remove(struct pci_dev *dev)
1684 {
1685         struct i801_priv *priv = pci_get_drvdata(dev);
1686
1687         pm_runtime_forbid(&dev->dev);
1688         pm_runtime_get_noresume(&dev->dev);
1689
1690         i801_disable_host_notify(priv);
1691         i801_del_mux(priv);
1692         i2c_del_adapter(&priv->adapter);
1693         i801_acpi_remove(priv);
1694         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1695
1696         platform_device_unregister(priv->tco_pdev);
1697
1698         /*
1699          * do not call pci_disable_device(dev) since it can cause hard hangs on
1700          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1701          */
1702 }
1703
1704 static void i801_shutdown(struct pci_dev *dev)
1705 {
1706         struct i801_priv *priv = pci_get_drvdata(dev);
1707
1708         /* Restore config registers to avoid hard hang on some systems */
1709         i801_disable_host_notify(priv);
1710         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1711 }
1712
1713 #ifdef CONFIG_PM
1714 static int i801_suspend(struct device *dev)
1715 {
1716         struct pci_dev *pci_dev = to_pci_dev(dev);
1717         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1718
1719         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1720         return 0;
1721 }
1722
1723 static int i801_resume(struct device *dev)
1724 {
1725         struct pci_dev *pci_dev = to_pci_dev(dev);
1726         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1727         int err;
1728
1729         err = i801_enable_host_notify(&priv->adapter);
1730         if (err && err != -ENOTSUPP)
1731                 dev_warn(dev, "Unable to enable SMBus Host Notify\n");
1732
1733         return 0;
1734 }
1735 #endif
1736
1737 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1738                             i801_resume, NULL);
1739
1740 static struct pci_driver i801_driver = {
1741         .name           = "i801_smbus",
1742         .id_table       = i801_ids,
1743         .probe          = i801_probe,
1744         .remove         = i801_remove,
1745         .shutdown       = i801_shutdown,
1746         .driver         = {
1747                 .pm     = &i801_pm_ops,
1748         },
1749 };
1750
1751 static int __init i2c_i801_init(void)
1752 {
1753         if (dmi_name_in_vendors("FUJITSU"))
1754                 input_apanel_init();
1755         return pci_register_driver(&i801_driver);
1756 }
1757
1758 static void __exit i2c_i801_exit(void)
1759 {
1760         pci_unregister_driver(&i801_driver);
1761 }
1762
1763 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1764 MODULE_DESCRIPTION("I801 SMBus driver");
1765 MODULE_LICENSE("GPL");
1766
1767 module_init(i2c_i801_init);
1768 module_exit(i2c_i801_exit);