2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
68 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
69 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
70 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
71 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
73 * Features supported by this driver:
77 * Block process call transaction no
78 * I2C block read transaction yes (doesn't use the block buffer)
80 * SMBus Host Notify yes
81 * Interrupt processing yes
83 * See the file Documentation/i2c/busses/i2c-i801 for details.
86 #include <linux/interrupt.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
90 #include <linux/stddef.h>
91 #include <linux/delay.h>
92 #include <linux/ioport.h>
93 #include <linux/init.h>
94 #include <linux/i2c.h>
95 #include <linux/i2c-smbus.h>
96 #include <linux/acpi.h>
98 #include <linux/dmi.h>
99 #include <linux/slab.h>
100 #include <linux/wait.h>
101 #include <linux/err.h>
102 #include <linux/platform_device.h>
103 #include <linux/platform_data/itco_wdt.h>
104 #include <linux/pm_runtime.h>
106 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
107 #include <linux/gpio.h>
108 #include <linux/i2c-mux-gpio.h>
111 /* I801 SMBus address offsets */
112 #define SMBHSTSTS(p) (0 + (p)->smba)
113 #define SMBHSTCNT(p) (2 + (p)->smba)
114 #define SMBHSTCMD(p) (3 + (p)->smba)
115 #define SMBHSTADD(p) (4 + (p)->smba)
116 #define SMBHSTDAT0(p) (5 + (p)->smba)
117 #define SMBHSTDAT1(p) (6 + (p)->smba)
118 #define SMBBLKDAT(p) (7 + (p)->smba)
119 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
120 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
121 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
122 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
123 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
124 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
126 /* PCI Address Constants */
128 #define SMBPCICTL 0x004
129 #define SMBPCISTS 0x006
130 #define SMBHSTCFG 0x040
131 #define TCOBASE 0x050
134 #define ACPIBASE 0x040
135 #define ACPIBASE_SMI_OFF 0x030
136 #define ACPICTRL 0x044
137 #define ACPICTRL_EN 0x080
139 #define SBREG_BAR 0x10
140 #define SBREG_SMBCTRL 0xc6000c
141 #define SBREG_SMBCTRL_DNV 0xcf000c
143 /* Host status bits for SMBPCISTS */
144 #define SMBPCISTS_INTS BIT(3)
146 /* Control bits for SMBPCICTL */
147 #define SMBPCICTL_INTDIS BIT(10)
149 /* Host configuration bits for SMBHSTCFG */
150 #define SMBHSTCFG_HST_EN BIT(0)
151 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
152 #define SMBHSTCFG_I2C_EN BIT(2)
153 #define SMBHSTCFG_SPD_WD BIT(4)
155 /* TCO configuration bits for TCOCTL */
156 #define TCOCTL_EN BIT(8)
158 /* Auxiliary status register bits, ICH4+ only */
159 #define SMBAUXSTS_CRCE BIT(0)
160 #define SMBAUXSTS_STCO BIT(1)
162 /* Auxiliary control register bits, ICH4+ only */
163 #define SMBAUXCTL_CRC BIT(0)
164 #define SMBAUXCTL_E32B BIT(1)
167 #define MAX_RETRIES 400
169 /* I801 command constants */
170 #define I801_QUICK 0x00
171 #define I801_BYTE 0x04
172 #define I801_BYTE_DATA 0x08
173 #define I801_WORD_DATA 0x0C
174 #define I801_PROC_CALL 0x10 /* unimplemented */
175 #define I801_BLOCK_DATA 0x14
176 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
178 /* I801 Host Control register bits */
179 #define SMBHSTCNT_INTREN BIT(0)
180 #define SMBHSTCNT_KILL BIT(1)
181 #define SMBHSTCNT_LAST_BYTE BIT(5)
182 #define SMBHSTCNT_START BIT(6)
183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
185 /* I801 Hosts Status register bits */
186 #define SMBHSTSTS_BYTE_DONE BIT(7)
187 #define SMBHSTSTS_INUSE_STS BIT(6)
188 #define SMBHSTSTS_SMBALERT_STS BIT(5)
189 #define SMBHSTSTS_FAILED BIT(4)
190 #define SMBHSTSTS_BUS_ERR BIT(3)
191 #define SMBHSTSTS_DEV_ERR BIT(2)
192 #define SMBHSTSTS_INTR BIT(1)
193 #define SMBHSTSTS_HOST_BUSY BIT(0)
195 /* Host Notify Status register bits */
196 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
198 /* Host Notify Command register bits */
199 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
201 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
204 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
207 /* Older devices have their ID defined in <linux/pci_ids.h> */
208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
224 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
225 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
226 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
228 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
233 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
234 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
236 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
237 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
238 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
239 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
241 struct i801_mux_config {
246 unsigned gpios[2]; /* Relative to gpio_chip->base */
251 struct i2c_adapter adapter;
253 unsigned char original_hstcfg;
254 unsigned char original_slvcmd;
255 struct pci_dev *pci_dev;
256 unsigned int features;
259 wait_queue_head_t waitq;
262 /* Command state used by isr for byte-by-byte block transactions */
269 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
270 const struct i801_mux_config *mux_drvdata;
271 struct platform_device *mux_pdev;
273 struct platform_device *tco_pdev;
276 * If set to true the host controller registers are reserved for
277 * ACPI AML use. Protected by acpi_lock.
280 struct mutex acpi_lock;
283 #define FEATURE_SMBUS_PEC BIT(0)
284 #define FEATURE_BLOCK_BUFFER BIT(1)
285 #define FEATURE_BLOCK_PROC BIT(2)
286 #define FEATURE_I2C_BLOCK_READ BIT(3)
287 #define FEATURE_IRQ BIT(4)
288 #define FEATURE_HOST_NOTIFY BIT(5)
289 /* Not really a feature, but it's convenient to handle it as such */
290 #define FEATURE_IDF BIT(15)
291 #define FEATURE_TCO BIT(16)
293 static const char *i801_feature_names[] = {
296 "Block process call",
302 static unsigned int disable_features;
303 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
304 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
305 "\t\t 0x01 disable SMBus PEC\n"
306 "\t\t 0x02 disable the block buffer\n"
307 "\t\t 0x08 disable the I2C block read functionality\n"
308 "\t\t 0x10 don't use interrupts\n"
309 "\t\t 0x20 disable SMBus Host Notify ");
311 /* Make sure the SMBus host is ready to start transmitting.
312 Return 0 if it is, -EBUSY if it is not. */
313 static int i801_check_pre(struct i801_priv *priv)
317 status = inb_p(SMBHSTSTS(priv));
318 if (status & SMBHSTSTS_HOST_BUSY) {
319 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
323 status &= STATUS_FLAGS;
325 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
327 outb_p(status, SMBHSTSTS(priv));
328 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
330 dev_err(&priv->pci_dev->dev,
331 "Failed clearing status flags (%02x)\n",
338 * Clear CRC status if needed.
339 * During normal operation, i801_check_post() takes care
340 * of it after every operation. We do it here only in case
341 * the hardware was already in this state when the driver
344 if (priv->features & FEATURE_SMBUS_PEC) {
345 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
347 dev_dbg(&priv->pci_dev->dev,
348 "Clearing aux status flags (%02x)\n", status);
349 outb_p(status, SMBAUXSTS(priv));
350 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
352 dev_err(&priv->pci_dev->dev,
353 "Failed clearing aux status flags (%02x)\n",
364 * Convert the status register to an error code, and clear it.
365 * Note that status only contains the bits we want to clear, not the
366 * actual register value.
368 static int i801_check_post(struct i801_priv *priv, int status)
373 * If the SMBus is still busy, we give up
374 * Note: This timeout condition only happens when using polling
375 * transactions. For interrupt operation, NAK/timeout is indicated by
378 if (unlikely(status < 0)) {
379 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
380 /* try to stop the current command */
381 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
382 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
383 usleep_range(1000, 2000);
384 outb_p(0, SMBHSTCNT(priv));
386 /* Check if it worked */
387 status = inb_p(SMBHSTSTS(priv));
388 if ((status & SMBHSTSTS_HOST_BUSY) ||
389 !(status & SMBHSTSTS_FAILED))
390 dev_err(&priv->pci_dev->dev,
391 "Failed terminating the transaction\n");
392 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
396 if (status & SMBHSTSTS_FAILED) {
398 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
400 if (status & SMBHSTSTS_DEV_ERR) {
402 * This may be a PEC error, check and clear it.
404 * AUXSTS is handled differently from HSTSTS.
405 * For HSTSTS, i801_isr() or i801_wait_intr()
406 * has already cleared the error bits in hardware,
407 * and we are passed a copy of the original value
409 * For AUXSTS, the hardware register is left
410 * for us to handle here.
411 * This is asymmetric, slightly iffy, but safe,
412 * since all this code is serialized and the CRCE
413 * bit is harmless as long as it's cleared before
414 * the next operation.
416 if ((priv->features & FEATURE_SMBUS_PEC) &&
417 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
418 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
420 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
423 dev_dbg(&priv->pci_dev->dev, "No response\n");
426 if (status & SMBHSTSTS_BUS_ERR) {
428 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
431 /* Clear status flags except BYTE_DONE, to be cleared by caller */
432 outb_p(status, SMBHSTSTS(priv));
437 /* Wait for BUSY being cleared and either INTR or an error flag being set */
438 static int i801_wait_intr(struct i801_priv *priv)
443 /* We will always wait for a fraction of a second! */
445 usleep_range(250, 500);
446 status = inb_p(SMBHSTSTS(priv));
447 } while (((status & SMBHSTSTS_HOST_BUSY) ||
448 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
449 (timeout++ < MAX_RETRIES));
451 if (timeout > MAX_RETRIES) {
452 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
455 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
458 /* Wait for either BYTE_DONE or an error flag being set */
459 static int i801_wait_byte_done(struct i801_priv *priv)
464 /* We will always wait for a fraction of a second! */
466 usleep_range(250, 500);
467 status = inb_p(SMBHSTSTS(priv));
468 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
469 (timeout++ < MAX_RETRIES));
471 if (timeout > MAX_RETRIES) {
472 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
475 return status & STATUS_ERROR_FLAGS;
478 static int i801_transaction(struct i801_priv *priv, int xact)
482 const struct i2c_adapter *adap = &priv->adapter;
484 result = i801_check_pre(priv);
488 if (priv->features & FEATURE_IRQ) {
489 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
491 result = wait_event_timeout(priv->waitq,
492 (status = priv->status),
496 dev_warn(&priv->pci_dev->dev,
497 "Timeout waiting for interrupt!\n");
500 return i801_check_post(priv, status);
503 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
504 * SMBSCMD are passed in xact */
505 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
507 status = i801_wait_intr(priv);
508 return i801_check_post(priv, status);
511 static int i801_block_transaction_by_block(struct i801_priv *priv,
512 union i2c_smbus_data *data,
513 char read_write, int hwpec)
518 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
520 /* Use 32-byte buffer to process this transaction */
521 if (read_write == I2C_SMBUS_WRITE) {
522 len = data->block[0];
523 outb_p(len, SMBHSTDAT0(priv));
524 for (i = 0; i < len; i++)
525 outb_p(data->block[i+1], SMBBLKDAT(priv));
528 status = i801_transaction(priv, I801_BLOCK_DATA |
529 (hwpec ? SMBHSTCNT_PEC_EN : 0));
533 if (read_write == I2C_SMBUS_READ) {
534 len = inb_p(SMBHSTDAT0(priv));
535 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
538 data->block[0] = len;
539 for (i = 0; i < len; i++)
540 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
545 static void i801_isr_byte_done(struct i801_priv *priv)
548 /* For SMBus block reads, length is received with first byte */
549 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
550 (priv->count == 0)) {
551 priv->len = inb_p(SMBHSTDAT0(priv));
552 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
553 dev_err(&priv->pci_dev->dev,
554 "Illegal SMBus block read size %d\n",
557 priv->len = I2C_SMBUS_BLOCK_MAX;
559 dev_dbg(&priv->pci_dev->dev,
560 "SMBus block read size is %d\n",
563 priv->data[-1] = priv->len;
567 if (priv->count < priv->len)
568 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
570 dev_dbg(&priv->pci_dev->dev,
571 "Discarding extra byte on block read\n");
573 /* Set LAST_BYTE for last byte of read transaction */
574 if (priv->count == priv->len - 1)
575 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
577 } else if (priv->count < priv->len - 1) {
578 /* Write next byte, except for IRQ after last byte */
579 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
582 /* Clear BYTE_DONE to continue with next byte */
583 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
586 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
590 addr = inb_p(SMBNTFDADD(priv)) >> 1;
593 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
594 * always returns 0. Our current implementation doesn't provide
595 * data, so we just ignore it.
597 i2c_handle_smbus_host_notify(&priv->adapter, addr);
599 /* clear Host Notify bit and return */
600 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
605 * There are three kinds of interrupts:
607 * 1) i801 signals transaction completion with one of these interrupts:
609 * DEV_ERR - Invalid command, NAK or communication timeout
610 * BUS_ERR - SMI# transaction collision
611 * FAILED - transaction was canceled due to a KILL request
612 * When any of these occur, update ->status and wake up the waitq.
613 * ->status must be cleared before kicking off the next transaction.
615 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
616 * occurs for each byte of a byte-by-byte to prepare the next byte.
618 * 3) Host Notify interrupts
620 static irqreturn_t i801_isr(int irq, void *dev_id)
622 struct i801_priv *priv = dev_id;
626 /* Confirm this is our interrupt */
627 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
628 if (!(pcists & SMBPCISTS_INTS))
631 if (priv->features & FEATURE_HOST_NOTIFY) {
632 status = inb_p(SMBSLVSTS(priv));
633 if (status & SMBSLVSTS_HST_NTFY_STS)
634 return i801_host_notify_isr(priv);
637 status = inb_p(SMBHSTSTS(priv));
638 if (status & SMBHSTSTS_BYTE_DONE)
639 i801_isr_byte_done(priv);
642 * Clear irq sources and report transaction result.
643 * ->status must be cleared before the next transaction is started.
645 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
647 outb_p(status, SMBHSTSTS(priv));
648 priv->status = status;
649 wake_up(&priv->waitq);
656 * For "byte-by-byte" block transactions:
657 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
658 * I2C read uses cmd=I801_I2C_BLOCK_DATA
660 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
661 union i2c_smbus_data *data,
662 char read_write, int command,
669 const struct i2c_adapter *adap = &priv->adapter;
671 result = i801_check_pre(priv);
675 len = data->block[0];
677 if (read_write == I2C_SMBUS_WRITE) {
678 outb_p(len, SMBHSTDAT0(priv));
679 outb_p(data->block[1], SMBBLKDAT(priv));
682 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
683 read_write == I2C_SMBUS_READ)
684 smbcmd = I801_I2C_BLOCK_DATA;
686 smbcmd = I801_BLOCK_DATA;
688 if (priv->features & FEATURE_IRQ) {
689 priv->is_read = (read_write == I2C_SMBUS_READ);
690 if (len == 1 && priv->is_read)
691 smbcmd |= SMBHSTCNT_LAST_BYTE;
692 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
695 priv->data = &data->block[1];
697 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
698 result = wait_event_timeout(priv->waitq,
699 (status = priv->status),
703 dev_warn(&priv->pci_dev->dev,
704 "Timeout waiting for interrupt!\n");
707 return i801_check_post(priv, status);
710 for (i = 1; i <= len; i++) {
711 if (i == len && read_write == I2C_SMBUS_READ)
712 smbcmd |= SMBHSTCNT_LAST_BYTE;
713 outb_p(smbcmd, SMBHSTCNT(priv));
716 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
719 status = i801_wait_byte_done(priv);
723 if (i == 1 && read_write == I2C_SMBUS_READ
724 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
725 len = inb_p(SMBHSTDAT0(priv));
726 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
727 dev_err(&priv->pci_dev->dev,
728 "Illegal SMBus block read size %d\n",
731 while (inb_p(SMBHSTSTS(priv)) &
733 outb_p(SMBHSTSTS_BYTE_DONE,
735 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
738 data->block[0] = len;
741 /* Retrieve/store value in SMBBLKDAT */
742 if (read_write == I2C_SMBUS_READ)
743 data->block[i] = inb_p(SMBBLKDAT(priv));
744 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
745 outb_p(data->block[i+1], SMBBLKDAT(priv));
747 /* signals SMBBLKDAT ready */
748 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
751 status = i801_wait_intr(priv);
753 return i801_check_post(priv, status);
756 static int i801_set_block_buffer_mode(struct i801_priv *priv)
758 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
759 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
764 /* Block transaction function */
765 static int i801_block_transaction(struct i801_priv *priv,
766 union i2c_smbus_data *data, char read_write,
767 int command, int hwpec)
772 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
773 if (read_write == I2C_SMBUS_WRITE) {
774 /* set I2C_EN bit in configuration register */
775 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
776 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
777 hostc | SMBHSTCFG_I2C_EN);
778 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
779 dev_err(&priv->pci_dev->dev,
780 "I2C block read is unsupported!\n");
785 if (read_write == I2C_SMBUS_WRITE
786 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
787 if (data->block[0] < 1)
789 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
790 data->block[0] = I2C_SMBUS_BLOCK_MAX;
792 data->block[0] = 32; /* max for SMBus block reads */
795 /* Experience has shown that the block buffer can only be used for
796 SMBus (not I2C) block transactions, even though the datasheet
797 doesn't mention this limitation. */
798 if ((priv->features & FEATURE_BLOCK_BUFFER)
799 && command != I2C_SMBUS_I2C_BLOCK_DATA
800 && i801_set_block_buffer_mode(priv) == 0)
801 result = i801_block_transaction_by_block(priv, data,
804 result = i801_block_transaction_byte_by_byte(priv, data,
808 if (command == I2C_SMBUS_I2C_BLOCK_DATA
809 && read_write == I2C_SMBUS_WRITE) {
810 /* restore saved configuration register value */
811 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
816 /* Return negative errno on error. */
817 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
818 unsigned short flags, char read_write, u8 command,
819 int size, union i2c_smbus_data *data)
823 int ret = 0, xact = 0;
824 struct i801_priv *priv = i2c_get_adapdata(adap);
826 mutex_lock(&priv->acpi_lock);
827 if (priv->acpi_reserved) {
828 mutex_unlock(&priv->acpi_lock);
832 pm_runtime_get_sync(&priv->pci_dev->dev);
834 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
835 && size != I2C_SMBUS_QUICK
836 && size != I2C_SMBUS_I2C_BLOCK_DATA;
839 case I2C_SMBUS_QUICK:
840 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
845 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
847 if (read_write == I2C_SMBUS_WRITE)
848 outb_p(command, SMBHSTCMD(priv));
851 case I2C_SMBUS_BYTE_DATA:
852 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
854 outb_p(command, SMBHSTCMD(priv));
855 if (read_write == I2C_SMBUS_WRITE)
856 outb_p(data->byte, SMBHSTDAT0(priv));
857 xact = I801_BYTE_DATA;
859 case I2C_SMBUS_WORD_DATA:
860 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
862 outb_p(command, SMBHSTCMD(priv));
863 if (read_write == I2C_SMBUS_WRITE) {
864 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
865 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
867 xact = I801_WORD_DATA;
869 case I2C_SMBUS_BLOCK_DATA:
870 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
872 outb_p(command, SMBHSTCMD(priv));
875 case I2C_SMBUS_I2C_BLOCK_DATA:
877 * NB: page 240 of ICH5 datasheet shows that the R/#W
878 * bit should be cleared here, even when reading.
879 * However if SPD Write Disable is set (Lynx Point and later),
880 * the read will fail if we don't set the R/#W bit.
882 outb_p(((addr & 0x7f) << 1) |
883 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
884 (read_write & 0x01) : 0),
886 if (read_write == I2C_SMBUS_READ) {
887 /* NB: page 240 of ICH5 datasheet also shows
888 * that DATA1 is the cmd field when reading */
889 outb_p(command, SMBHSTDAT1(priv));
891 outb_p(command, SMBHSTCMD(priv));
895 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
901 if (hwpec) /* enable/disable hardware PEC */
902 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
904 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
908 ret = i801_block_transaction(priv, data, read_write, size,
911 ret = i801_transaction(priv, xact);
913 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
914 time, so we forcibly disable it after every transaction. Turn off
915 E32B for the same reason. */
917 outb_p(inb_p(SMBAUXCTL(priv)) &
918 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
924 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
927 switch (xact & 0x7f) {
928 case I801_BYTE: /* Result put in SMBHSTDAT0 */
930 data->byte = inb_p(SMBHSTDAT0(priv));
933 data->word = inb_p(SMBHSTDAT0(priv)) +
934 (inb_p(SMBHSTDAT1(priv)) << 8);
939 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
940 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
941 mutex_unlock(&priv->acpi_lock);
946 static u32 i801_func(struct i2c_adapter *adapter)
948 struct i801_priv *priv = i2c_get_adapdata(adapter);
950 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
951 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
952 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
953 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
954 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
955 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
956 ((priv->features & FEATURE_HOST_NOTIFY) ?
957 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
960 static void i801_enable_host_notify(struct i2c_adapter *adapter)
962 struct i801_priv *priv = i2c_get_adapdata(adapter);
964 if (!(priv->features & FEATURE_HOST_NOTIFY))
967 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
968 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
971 /* clear Host Notify bit to allow a new notification */
972 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
975 static void i801_disable_host_notify(struct i801_priv *priv)
977 if (!(priv->features & FEATURE_HOST_NOTIFY))
980 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
983 static const struct i2c_algorithm smbus_algorithm = {
984 .smbus_xfer = i801_access,
985 .functionality = i801_func,
988 static const struct pci_device_id i801_ids[] = {
989 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1038 MODULE_DEVICE_TABLE(pci, i801_ids);
1040 #if defined CONFIG_X86 && defined CONFIG_DMI
1041 static unsigned char apanel_addr;
1043 /* Scan the system ROM for the signature "FJKEYINF" */
1044 static __init const void __iomem *bios_signature(const void __iomem *bios)
1047 const unsigned char signature[] = "FJKEYINF";
1049 for (offset = 0; offset < 0x10000; offset += 0x10) {
1050 if (check_signature(bios + offset, signature,
1051 sizeof(signature)-1))
1052 return bios + offset;
1057 static void __init input_apanel_init(void)
1060 const void __iomem *p;
1062 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1063 p = bios_signature(bios);
1065 /* just use the first address */
1066 apanel_addr = readb(p + 8 + 3) >> 1;
1071 struct dmi_onboard_device_info {
1074 unsigned short i2c_addr;
1075 const char *i2c_type;
1078 static const struct dmi_onboard_device_info dmi_devices[] = {
1079 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1080 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1081 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1084 static void dmi_check_onboard_device(u8 type, const char *name,
1085 struct i2c_adapter *adap)
1088 struct i2c_board_info info;
1090 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1091 /* & ~0x80, ignore enabled/disabled bit */
1092 if ((type & ~0x80) != dmi_devices[i].type)
1094 if (strcasecmp(name, dmi_devices[i].name))
1097 memset(&info, 0, sizeof(struct i2c_board_info));
1098 info.addr = dmi_devices[i].i2c_addr;
1099 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1100 i2c_new_device(adap, &info);
1105 /* We use our own function to check for onboard devices instead of
1106 dmi_find_device() as some buggy BIOS's have the devices we are interested
1107 in marked as disabled */
1108 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1115 count = (dm->length - sizeof(struct dmi_header)) / 2;
1116 for (i = 0; i < count; i++) {
1117 const u8 *d = (char *)(dm + 1) + (i * 2);
1118 const char *name = ((char *) dm) + dm->length;
1125 while (s > 0 && name[0]) {
1126 name += strlen(name) + 1;
1129 if (name[0] == 0) /* Bogus string reference */
1132 dmi_check_onboard_device(type, name, adap);
1136 /* Register optional slaves */
1137 static void i801_probe_optional_slaves(struct i801_priv *priv)
1139 /* Only register slaves on main SMBus channel */
1140 if (priv->features & FEATURE_IDF)
1144 struct i2c_board_info info;
1146 memset(&info, 0, sizeof(struct i2c_board_info));
1147 info.addr = apanel_addr;
1148 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1149 i2c_new_device(&priv->adapter, &info);
1152 if (dmi_name_in_vendors("FUJITSU"))
1153 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1156 static void __init input_apanel_init(void) {}
1157 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1158 #endif /* CONFIG_X86 && CONFIG_DMI */
1160 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1161 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1162 .gpio_chip = "gpio_ich",
1163 .values = { 0x02, 0x03 },
1165 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1166 .gpios = { 52, 53 },
1170 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1171 .gpio_chip = "gpio_ich",
1172 .values = { 0x02, 0x03, 0x01 },
1174 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1175 .gpios = { 52, 53 },
1179 static const struct dmi_system_id mux_dmi_table[] = {
1182 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1183 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1185 .driver_data = &i801_mux_config_asus_z8_d12,
1189 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1190 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1192 .driver_data = &i801_mux_config_asus_z8_d12,
1196 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1197 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1199 .driver_data = &i801_mux_config_asus_z8_d12,
1203 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1204 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1206 .driver_data = &i801_mux_config_asus_z8_d12,
1210 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1211 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1213 .driver_data = &i801_mux_config_asus_z8_d12,
1217 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1218 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1220 .driver_data = &i801_mux_config_asus_z8_d12,
1224 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1225 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1227 .driver_data = &i801_mux_config_asus_z8_d18,
1231 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1232 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1234 .driver_data = &i801_mux_config_asus_z8_d18,
1238 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1239 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1241 .driver_data = &i801_mux_config_asus_z8_d12,
1246 /* Setup multiplexing if needed */
1247 static int i801_add_mux(struct i801_priv *priv)
1249 struct device *dev = &priv->adapter.dev;
1250 const struct i801_mux_config *mux_config;
1251 struct i2c_mux_gpio_platform_data gpio_data;
1254 if (!priv->mux_drvdata)
1256 mux_config = priv->mux_drvdata;
1258 /* Prepare the platform data */
1259 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1260 gpio_data.parent = priv->adapter.nr;
1261 gpio_data.values = mux_config->values;
1262 gpio_data.n_values = mux_config->n_values;
1263 gpio_data.classes = mux_config->classes;
1264 gpio_data.gpio_chip = mux_config->gpio_chip;
1265 gpio_data.gpios = mux_config->gpios;
1266 gpio_data.n_gpios = mux_config->n_gpios;
1267 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1269 /* Register the mux device */
1270 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1271 PLATFORM_DEVID_AUTO, &gpio_data,
1272 sizeof(struct i2c_mux_gpio_platform_data));
1273 if (IS_ERR(priv->mux_pdev)) {
1274 err = PTR_ERR(priv->mux_pdev);
1275 priv->mux_pdev = NULL;
1276 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1283 static void i801_del_mux(struct i801_priv *priv)
1286 platform_device_unregister(priv->mux_pdev);
1289 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1291 const struct dmi_system_id *id;
1292 const struct i801_mux_config *mux_config;
1293 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1296 id = dmi_first_match(mux_dmi_table);
1298 /* Remove branch classes from trunk */
1299 mux_config = id->driver_data;
1300 for (i = 0; i < mux_config->n_values; i++)
1301 class &= ~mux_config->classes[i];
1303 /* Remember for later */
1304 priv->mux_drvdata = mux_config;
1310 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1311 static inline void i801_del_mux(struct i801_priv *priv) { }
1313 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1315 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1319 static const struct itco_wdt_platform_data tco_platform_data = {
1320 .name = "Intel PCH",
1324 static DEFINE_SPINLOCK(p2sb_spinlock);
1326 static void i801_add_tco(struct i801_priv *priv)
1328 struct pci_dev *pci_dev = priv->pci_dev;
1329 struct resource tco_res[3], *res;
1330 struct platform_device *pdev;
1332 u32 tco_base, tco_ctl;
1333 u32 base_addr, ctrl_val;
1337 if (!(priv->features & FEATURE_TCO))
1340 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1341 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1342 if (!(tco_ctl & TCOCTL_EN))
1345 memset(tco_res, 0, sizeof(tco_res));
1347 res = &tco_res[ICH_RES_IO_TCO];
1348 res->start = tco_base & ~1;
1349 res->end = res->start + 32 - 1;
1350 res->flags = IORESOURCE_IO;
1353 * Power Management registers.
1355 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1356 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1358 res = &tco_res[ICH_RES_IO_SMI];
1359 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1360 res->end = res->start + 3;
1361 res->flags = IORESOURCE_IO;
1364 * Enable the ACPI I/O space.
1366 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1367 ctrl_val |= ACPICTRL_EN;
1368 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1371 * We must access the NO_REBOOT bit over the Primary to Sideband
1372 * bridge (P2SB). The BIOS prevents the P2SB device from being
1373 * enumerated by the PCI subsystem, so we need to unhide/hide it
1374 * to lookup the P2SB BAR.
1376 spin_lock(&p2sb_spinlock);
1378 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1380 /* Unhide the P2SB device, if it is hidden */
1381 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1383 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1385 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1386 base64_addr = base_addr & 0xfffffff0;
1388 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1389 base64_addr |= (u64)base_addr << 32;
1391 /* Hide the P2SB device, if it was hidden before */
1393 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1394 spin_unlock(&p2sb_spinlock);
1396 res = &tco_res[ICH_RES_MEM_OFF];
1397 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1398 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1400 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1402 res->end = res->start + 3;
1403 res->flags = IORESOURCE_MEM;
1405 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1406 tco_res, 3, &tco_platform_data,
1407 sizeof(tco_platform_data));
1409 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1413 priv->tco_pdev = pdev;
1417 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1418 acpi_physical_address address)
1420 return address >= priv->smba &&
1421 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1425 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1426 u64 *value, void *handler_context, void *region_context)
1428 struct i801_priv *priv = handler_context;
1429 struct pci_dev *pdev = priv->pci_dev;
1433 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1434 * further access from the driver itself. This device is now owned
1435 * by the system firmware.
1437 mutex_lock(&priv->acpi_lock);
1439 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1440 priv->acpi_reserved = true;
1442 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1443 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1446 * BIOS is accessing the host controller so prevent it from
1447 * suspending automatically from now on.
1449 pm_runtime_get_sync(&pdev->dev);
1452 if ((function & ACPI_IO_MASK) == ACPI_READ)
1453 status = acpi_os_read_port(address, (u32 *)value, bits);
1455 status = acpi_os_write_port(address, (u32)*value, bits);
1457 mutex_unlock(&priv->acpi_lock);
1462 static int i801_acpi_probe(struct i801_priv *priv)
1464 struct acpi_device *adev;
1467 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1469 status = acpi_install_address_space_handler(adev->handle,
1470 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1472 if (ACPI_SUCCESS(status))
1476 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1479 static void i801_acpi_remove(struct i801_priv *priv)
1481 struct acpi_device *adev;
1483 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1487 acpi_remove_address_space_handler(adev->handle,
1488 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1490 mutex_lock(&priv->acpi_lock);
1491 if (priv->acpi_reserved)
1492 pm_runtime_put(&priv->pci_dev->dev);
1493 mutex_unlock(&priv->acpi_lock);
1496 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1497 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1500 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1502 unsigned char hstcfg = priv->original_hstcfg;
1504 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1505 hstcfg |= SMBHSTCFG_HST_EN;
1506 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1510 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1514 struct i801_priv *priv;
1516 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1520 i2c_set_adapdata(&priv->adapter, priv);
1521 priv->adapter.owner = THIS_MODULE;
1522 priv->adapter.class = i801_get_adapter_class(priv);
1523 priv->adapter.algo = &smbus_algorithm;
1524 priv->adapter.dev.parent = &dev->dev;
1525 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1526 priv->adapter.retries = 3;
1527 mutex_init(&priv->acpi_lock);
1529 priv->pci_dev = dev;
1530 switch (dev->device) {
1531 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1532 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1533 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1534 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1535 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1536 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1537 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1538 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1539 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1540 priv->features |= FEATURE_I2C_BLOCK_READ;
1541 priv->features |= FEATURE_IRQ;
1542 priv->features |= FEATURE_SMBUS_PEC;
1543 priv->features |= FEATURE_BLOCK_BUFFER;
1544 /* If we have ACPI based watchdog use that instead */
1545 if (!acpi_has_watchdog())
1546 priv->features |= FEATURE_TCO;
1547 priv->features |= FEATURE_HOST_NOTIFY;
1550 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1551 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1552 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1553 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1554 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1555 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1556 priv->features |= FEATURE_IDF;
1559 priv->features |= FEATURE_I2C_BLOCK_READ;
1560 priv->features |= FEATURE_IRQ;
1562 case PCI_DEVICE_ID_INTEL_82801DB_3:
1563 priv->features |= FEATURE_SMBUS_PEC;
1564 priv->features |= FEATURE_BLOCK_BUFFER;
1566 case PCI_DEVICE_ID_INTEL_82801CA_3:
1567 priv->features |= FEATURE_HOST_NOTIFY;
1569 case PCI_DEVICE_ID_INTEL_82801BA_2:
1570 case PCI_DEVICE_ID_INTEL_82801AB_3:
1571 case PCI_DEVICE_ID_INTEL_82801AA_3:
1575 /* Disable features on user request */
1576 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1577 if (priv->features & disable_features & (1 << i))
1578 dev_notice(&dev->dev, "%s disabled by user\n",
1579 i801_feature_names[i]);
1581 priv->features &= ~disable_features;
1583 err = pcim_enable_device(dev);
1585 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1589 pcim_pin_device(dev);
1591 /* Determine the address of the SMBus area */
1592 priv->smba = pci_resource_start(dev, SMBBAR);
1595 "SMBus base address uninitialized, upgrade BIOS\n");
1599 if (i801_acpi_probe(priv))
1602 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1603 dev_driver_string(&dev->dev));
1606 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1608 (unsigned long long)pci_resource_end(dev, SMBBAR));
1609 i801_acpi_remove(priv);
1613 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1614 temp = i801_setup_hstcfg(priv);
1615 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1616 dev_info(&dev->dev, "Enabling SMBus device\n");
1618 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1619 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1620 /* Disable SMBus interrupt feature if SMBus using SMI# */
1621 priv->features &= ~FEATURE_IRQ;
1623 if (temp & SMBHSTCFG_SPD_WD)
1624 dev_info(&dev->dev, "SPD Write Disable is set\n");
1626 /* Clear special mode bits */
1627 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1628 outb_p(inb_p(SMBAUXCTL(priv)) &
1629 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1631 /* Remember original Host Notify setting */
1632 if (priv->features & FEATURE_HOST_NOTIFY)
1633 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1635 /* Default timeout in interrupt mode: 200 ms */
1636 priv->adapter.timeout = HZ / 5;
1638 if (dev->irq == IRQ_NOTCONNECTED)
1639 priv->features &= ~FEATURE_IRQ;
1641 if (priv->features & FEATURE_IRQ) {
1644 /* Complain if an interrupt is already pending */
1645 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1646 if (pcists & SMBPCISTS_INTS)
1647 dev_warn(&dev->dev, "An interrupt is pending!\n");
1649 /* Check if interrupts have been disabled */
1650 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1651 if (pcictl & SMBPCICTL_INTDIS) {
1652 dev_info(&dev->dev, "Interrupts are disabled\n");
1653 priv->features &= ~FEATURE_IRQ;
1657 if (priv->features & FEATURE_IRQ) {
1658 init_waitqueue_head(&priv->waitq);
1660 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1662 dev_driver_string(&dev->dev), priv);
1664 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1666 priv->features &= ~FEATURE_IRQ;
1669 dev_info(&dev->dev, "SMBus using %s\n",
1670 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1674 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1675 "SMBus I801 adapter at %04lx", priv->smba);
1676 err = i2c_add_adapter(&priv->adapter);
1678 i801_acpi_remove(priv);
1682 i801_enable_host_notify(&priv->adapter);
1684 i801_probe_optional_slaves(priv);
1685 /* We ignore errors - multiplexing is optional */
1688 pci_set_drvdata(dev, priv);
1690 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1691 pm_runtime_use_autosuspend(&dev->dev);
1692 pm_runtime_put_autosuspend(&dev->dev);
1693 pm_runtime_allow(&dev->dev);
1698 static void i801_remove(struct pci_dev *dev)
1700 struct i801_priv *priv = pci_get_drvdata(dev);
1702 pm_runtime_forbid(&dev->dev);
1703 pm_runtime_get_noresume(&dev->dev);
1705 i801_disable_host_notify(priv);
1707 i2c_del_adapter(&priv->adapter);
1708 i801_acpi_remove(priv);
1709 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1711 platform_device_unregister(priv->tco_pdev);
1714 * do not call pci_disable_device(dev) since it can cause hard hangs on
1715 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1719 static void i801_shutdown(struct pci_dev *dev)
1721 struct i801_priv *priv = pci_get_drvdata(dev);
1723 /* Restore config registers to avoid hard hang on some systems */
1724 i801_disable_host_notify(priv);
1725 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1729 static int i801_suspend(struct device *dev)
1731 struct pci_dev *pci_dev = to_pci_dev(dev);
1732 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1734 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1738 static int i801_resume(struct device *dev)
1740 struct pci_dev *pci_dev = to_pci_dev(dev);
1741 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1743 i801_setup_hstcfg(priv);
1744 i801_enable_host_notify(&priv->adapter);
1750 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1753 static struct pci_driver i801_driver = {
1754 .name = "i801_smbus",
1755 .id_table = i801_ids,
1756 .probe = i801_probe,
1757 .remove = i801_remove,
1758 .shutdown = i801_shutdown,
1764 static int __init i2c_i801_init(void)
1766 if (dmi_name_in_vendors("FUJITSU"))
1767 input_apanel_init();
1768 return pci_register_driver(&i801_driver);
1771 static void __exit i2c_i801_exit(void)
1773 pci_unregister_driver(&i801_driver);
1776 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1777 MODULE_DESCRIPTION("I801 SMBus driver");
1778 MODULE_LICENSE("GPL");
1780 module_init(i2c_i801_init);
1781 module_exit(i2c_i801_exit);