drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  68  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  69  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  70  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  71  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  72  *
  73  * Features supported by this driver:
  74  * Software PEC                         no
  75  * Hardware PEC                         yes
  76  * Block buffer                         yes
  77  * Block process call transaction       no
  78  * I2C block read transaction           yes (doesn't use the block buffer)
  79  * Slave mode                           no
  80  * SMBus Host Notify                    yes
  81  * Interrupt processing                 yes
  82  *
  83  * See the file Documentation/i2c/busses/i2c-i801 for details.
  84  */
  85
  86 #include <linux/interrupt.h>
  87 #include <linux/module.h>
  88 #include <linux/pci.h>
  89 #include <linux/kernel.h>
  90 #include <linux/stddef.h>
  91 #include <linux/delay.h>
  92 #include <linux/ioport.h>
  93 #include <linux/init.h>
  94 #include <linux/i2c.h>
  95 #include <linux/i2c-smbus.h>
  96 #include <linux/acpi.h>
  97 #include <linux/io.h>
  98 #include <linux/dmi.h>
  99 #include <linux/slab.h>
 100 #include <linux/wait.h>
 101 #include <linux/err.h>
 102 #include <linux/platform_device.h>
 103 #include <linux/platform_data/itco_wdt.h>
 104 #include <linux/pm_runtime.h>
 105
 106 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 107 #include <linux/gpio.h>
 108 #include <linux/i2c-mux-gpio.h>
 109 #endif
 110
 111 /* I801 SMBus address offsets */
 112 #define SMBHSTSTS(p)    (0 + (p)->smba)
 113 #define SMBHSTCNT(p)    (2 + (p)->smba)
 114 #define SMBHSTCMD(p)    (3 + (p)->smba)
 115 #define SMBHSTADD(p)    (4 + (p)->smba)
 116 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 117 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 118 #define SMBBLKDAT(p)    (7 + (p)->smba)
 119 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 120 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 121 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 122 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 123 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 124 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 125
 126 /* PCI Address Constants */
 127 #define SMBBAR          4
 128 #define SMBPCICTL       0x004
 129 #define SMBPCISTS       0x006
 130 #define SMBHSTCFG       0x040
 131 #define TCOBASE         0x050
 132 #define TCOCTL          0x054
 133
 134 #define ACPIBASE                0x040
 135 #define ACPIBASE_SMI_OFF        0x030
 136 #define ACPICTRL                0x044
 137 #define ACPICTRL_EN             0x080
 138
 139 #define SBREG_BAR               0x10
 140 #define SBREG_SMBCTRL           0xc6000c
 141 #define SBREG_SMBCTRL_DNV       0xcf000c
 142
 143 /* Host status bits for SMBPCISTS */
 144 #define SMBPCISTS_INTS          BIT(3)
 145
 146 /* Control bits for SMBPCICTL */
 147 #define SMBPCICTL_INTDIS        BIT(10)
 148
 149 /* Host configuration bits for SMBHSTCFG */
 150 #define SMBHSTCFG_HST_EN        BIT(0)
 151 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 152 #define SMBHSTCFG_I2C_EN        BIT(2)
 153 #define SMBHSTCFG_SPD_WD        BIT(4)
 154
 155 /* TCO configuration bits for TCOCTL */
 156 #define TCOCTL_EN               BIT(8)
 157
 158 /* Auxiliary status register bits, ICH4+ only */
 159 #define SMBAUXSTS_CRCE          BIT(0)
 160 #define SMBAUXSTS_STCO          BIT(1)
 161
 162 /* Auxiliary control register bits, ICH4+ only */
 163 #define SMBAUXCTL_CRC           BIT(0)
 164 #define SMBAUXCTL_E32B          BIT(1)
 165
 166 /* Other settings */
 167 #define MAX_RETRIES             400
 168
 169 /* I801 command constants */
 170 #define I801_QUICK              0x00
 171 #define I801_BYTE               0x04
 172 #define I801_BYTE_DATA          0x08
 173 #define I801_WORD_DATA          0x0C
 174 #define I801_PROC_CALL          0x10    /* unimplemented */
 175 #define I801_BLOCK_DATA         0x14
 176 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 177
 178 /* I801 Host Control register bits */
 179 #define SMBHSTCNT_INTREN        BIT(0)
 180 #define SMBHSTCNT_KILL          BIT(1)
 181 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 182 #define SMBHSTCNT_START         BIT(6)
 183 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 184
 185 /* I801 Hosts Status register bits */
 186 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 187 #define SMBHSTSTS_INUSE_STS     BIT(6)
 188 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 189 #define SMBHSTSTS_FAILED        BIT(4)
 190 #define SMBHSTSTS_BUS_ERR       BIT(3)
 191 #define SMBHSTSTS_DEV_ERR       BIT(2)
 192 #define SMBHSTSTS_INTR          BIT(1)
 193 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 194
 195 /* Host Notify Status register bits */
 196 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 197
 198 /* Host Notify Command register bits */
 199 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 200
 201 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 202                                  SMBHSTSTS_DEV_ERR)
 203
 204 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 205                                  STATUS_ERROR_FLAGS)
 206
 207 /* Older devices have their ID defined in <linux/pci_ids.h> */
 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 224 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 225 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 226 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 228 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 233 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 234 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 236 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 237 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 238 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 239 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 240
 241 struct i801_mux_config {
 242         char *gpio_chip;
 243         unsigned values[3];
 244         int n_values;
 245         unsigned classes[3];
 246         unsigned gpios[2];              /* Relative to gpio_chip->base */
 247         int n_gpios;
 248 };
 249
 250 struct i801_priv {
 251         struct i2c_adapter adapter;
 252         unsigned long smba;
 253         unsigned char original_hstcfg;
 254         unsigned char original_slvcmd;
 255         struct pci_dev *pci_dev;
 256         unsigned int features;
 257
 258         /* isr processing */
 259         wait_queue_head_t waitq;
 260         u8 status;
 261
 262         /* Command state used by isr for byte-by-byte block transactions */
 263         u8 cmd;
 264         bool is_read;
 265         int count;
 266         int len;
 267         u8 *data;
 268
 269 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 270         const struct i801_mux_config *mux_drvdata;
 271         struct platform_device *mux_pdev;
 272 #endif
 273         struct platform_device *tco_pdev;
 274
 275         /*
 276          * If set to true the host controller registers are reserved for
 277          * ACPI AML use. Protected by acpi_lock.
 278          */
 279         bool acpi_reserved;
 280         struct mutex acpi_lock;
 281 };
 282
 283 #define FEATURE_SMBUS_PEC       BIT(0)
 284 #define FEATURE_BLOCK_BUFFER    BIT(1)
 285 #define FEATURE_BLOCK_PROC      BIT(2)
 286 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 287 #define FEATURE_IRQ             BIT(4)
 288 #define FEATURE_HOST_NOTIFY     BIT(5)
 289 /* Not really a feature, but it's convenient to handle it as such */
 290 #define FEATURE_IDF             BIT(15)
 291 #define FEATURE_TCO             BIT(16)
 292
 293 static const char *i801_feature_names[] = {
 294         "SMBus PEC",
 295         "Block buffer",
 296         "Block process call",
 297         "I2C block read",
 298         "Interrupt",
 299         "SMBus Host Notify",
 300 };
 301
 302 static unsigned int disable_features;
 303 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 304 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 305         "\t\t  0x01  disable SMBus PEC\n"
 306         "\t\t  0x02  disable the block buffer\n"
 307         "\t\t  0x08  disable the I2C block read functionality\n"
 308         "\t\t  0x10  don't use interrupts\n"
 309         "\t\t  0x20  disable SMBus Host Notify ");
 310
 311 /* Make sure the SMBus host is ready to start transmitting.
 312    Return 0 if it is, -EBUSY if it is not. */
 313 static int i801_check_pre(struct i801_priv *priv)
 314 {
 315         int status;
 316
 317         status = inb_p(SMBHSTSTS(priv));
 318         if (status & SMBHSTSTS_HOST_BUSY) {
 319                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 320                 return -EBUSY;
 321         }
 322
 323         status &= STATUS_FLAGS;
 324         if (status) {
 325                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 326                         status);
 327                 outb_p(status, SMBHSTSTS(priv));
 328                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 329                 if (status) {
 330                         dev_err(&priv->pci_dev->dev,
 331                                 "Failed clearing status flags (%02x)\n",
 332                                 status);
 333                         return -EBUSY;
 334                 }
 335         }
 336
 337         /*
 338          * Clear CRC status if needed.
 339          * During normal operation, i801_check_post() takes care
 340          * of it after every operation.  We do it here only in case
 341          * the hardware was already in this state when the driver
 342          * started.
 343          */
 344         if (priv->features & FEATURE_SMBUS_PEC) {
 345                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 346                 if (status) {
 347                         dev_dbg(&priv->pci_dev->dev,
 348                                 "Clearing aux status flags (%02x)\n", status);
 349                         outb_p(status, SMBAUXSTS(priv));
 350                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 351                         if (status) {
 352                                 dev_err(&priv->pci_dev->dev,
 353                                         "Failed clearing aux status flags (%02x)\n",
 354                                         status);
 355                                 return -EBUSY;
 356                         }
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362
 363 /*
 364  * Convert the status register to an error code, and clear it.
 365  * Note that status only contains the bits we want to clear, not the
 366  * actual register value.
 367  */
 368 static int i801_check_post(struct i801_priv *priv, int status)
 369 {
 370         int result = 0;
 371
 372         /*
 373          * If the SMBus is still busy, we give up
 374          * Note: This timeout condition only happens when using polling
 375          * transactions.  For interrupt operation, NAK/timeout is indicated by
 376          * DEV_ERR.
 377          */
 378         if (unlikely(status < 0)) {
 379                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 380                 /* try to stop the current command */
 381                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 382                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 383                 usleep_range(1000, 2000);
 384                 outb_p(0, SMBHSTCNT(priv));
 385
 386                 /* Check if it worked */
 387                 status = inb_p(SMBHSTSTS(priv));
 388                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 389                     !(status & SMBHSTSTS_FAILED))
 390                         dev_err(&priv->pci_dev->dev,
 391                                 "Failed terminating the transaction\n");
 392                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 393                 return -ETIMEDOUT;
 394         }
 395
 396         if (status & SMBHSTSTS_FAILED) {
 397                 result = -EIO;
 398                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 399         }
 400         if (status & SMBHSTSTS_DEV_ERR) {
 401                 /*
 402                  * This may be a PEC error, check and clear it.
 403                  *
 404                  * AUXSTS is handled differently from HSTSTS.
 405                  * For HSTSTS, i801_isr() or i801_wait_intr()
 406                  * has already cleared the error bits in hardware,
 407                  * and we are passed a copy of the original value
 408                  * in "status".
 409                  * For AUXSTS, the hardware register is left
 410                  * for us to handle here.
 411                  * This is asymmetric, slightly iffy, but safe,
 412                  * since all this code is serialized and the CRCE
 413                  * bit is harmless as long as it's cleared before
 414                  * the next operation.
 415                  */
 416                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 417                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 418                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 419                         result = -EBADMSG;
 420                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 421                 } else {
 422                         result = -ENXIO;
 423                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 424                 }
 425         }
 426         if (status & SMBHSTSTS_BUS_ERR) {
 427                 result = -EAGAIN;
 428                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 429         }
 430
 431         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 432         outb_p(status, SMBHSTSTS(priv));
 433
 434         return result;
 435 }
 436
 437 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 438 static int i801_wait_intr(struct i801_priv *priv)
 439 {
 440         int timeout = 0;
 441         int status;
 442
 443         /* We will always wait for a fraction of a second! */
 444         do {
 445                 usleep_range(250, 500);
 446                 status = inb_p(SMBHSTSTS(priv));
 447         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 448                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 449                  (timeout++ < MAX_RETRIES));
 450
 451         if (timeout > MAX_RETRIES) {
 452                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 453                 return -ETIMEDOUT;
 454         }
 455         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 456 }
 457
 458 /* Wait for either BYTE_DONE or an error flag being set */
 459 static int i801_wait_byte_done(struct i801_priv *priv)
 460 {
 461         int timeout = 0;
 462         int status;
 463
 464         /* We will always wait for a fraction of a second! */
 465         do {
 466                 usleep_range(250, 500);
 467                 status = inb_p(SMBHSTSTS(priv));
 468         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 469                  (timeout++ < MAX_RETRIES));
 470
 471         if (timeout > MAX_RETRIES) {
 472                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 473                 return -ETIMEDOUT;
 474         }
 475         return status & STATUS_ERROR_FLAGS;
 476 }
 477
 478 static int i801_transaction(struct i801_priv *priv, int xact)
 479 {
 480         int status;
 481         int result;
 482         const struct i2c_adapter *adap = &priv->adapter;
 483
 484         result = i801_check_pre(priv);
 485         if (result < 0)
 486                 return result;
 487
 488         if (priv->features & FEATURE_IRQ) {
 489                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 490                        SMBHSTCNT(priv));
 491                 result = wait_event_timeout(priv->waitq,
 492                                             (status = priv->status),
 493                                             adap->timeout);
 494                 if (!result) {
 495                         status = -ETIMEDOUT;
 496                         dev_warn(&priv->pci_dev->dev,
 497                                  "Timeout waiting for interrupt!\n");
 498                 }
 499                 priv->status = 0;
 500                 return i801_check_post(priv, status);
 501         }
 502
 503         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 504          * SMBSCMD are passed in xact */
 505         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 506
 507         status = i801_wait_intr(priv);
 508         return i801_check_post(priv, status);
 509 }
 510
 511 static int i801_block_transaction_by_block(struct i801_priv *priv,
 512                                            union i2c_smbus_data *data,
 513                                            char read_write, int hwpec)
 514 {
 515         int i, len;
 516         int status;
 517
 518         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 519
 520         /* Use 32-byte buffer to process this transaction */
 521         if (read_write == I2C_SMBUS_WRITE) {
 522                 len = data->block[0];
 523                 outb_p(len, SMBHSTDAT0(priv));
 524                 for (i = 0; i < len; i++)
 525                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 526         }
 527
 528         status = i801_transaction(priv, I801_BLOCK_DATA |
 529                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 530         if (status)
 531                 return status;
 532
 533         if (read_write == I2C_SMBUS_READ) {
 534                 len = inb_p(SMBHSTDAT0(priv));
 535                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 536                         return -EPROTO;
 537
 538                 data->block[0] = len;
 539                 for (i = 0; i < len; i++)
 540                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 541         }
 542         return 0;
 543 }
 544
 545 static void i801_isr_byte_done(struct i801_priv *priv)
 546 {
 547         if (priv->is_read) {
 548                 /* For SMBus block reads, length is received with first byte */
 549                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 550                     (priv->count == 0)) {
 551                         priv->len = inb_p(SMBHSTDAT0(priv));
 552                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 553                                 dev_err(&priv->pci_dev->dev,
 554                                         "Illegal SMBus block read size %d\n",
 555                                         priv->len);
 556                                 /* FIXME: Recover */
 557                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 558                         } else {
 559                                 dev_dbg(&priv->pci_dev->dev,
 560                                         "SMBus block read size is %d\n",
 561                                         priv->len);
 562                         }
 563                         priv->data[-1] = priv->len;
 564                 }
 565
 566                 /* Read next byte */
 567                 if (priv->count < priv->len)
 568                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 569                 else
 570                         dev_dbg(&priv->pci_dev->dev,
 571                                 "Discarding extra byte on block read\n");
 572
 573                 /* Set LAST_BYTE for last byte of read transaction */
 574                 if (priv->count == priv->len - 1)
 575                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 576                                SMBHSTCNT(priv));
 577         } else if (priv->count < priv->len - 1) {
 578                 /* Write next byte, except for IRQ after last byte */
 579                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 580         }
 581
 582         /* Clear BYTE_DONE to continue with next byte */
 583         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 584 }
 585
 586 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 587 {
 588         unsigned short addr;
 589
 590         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 591
 592         /*
 593          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 594          * always returns 0. Our current implementation doesn't provide
 595          * data, so we just ignore it.
 596          */
 597         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 598
 599         /* clear Host Notify bit and return */
 600         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 601         return IRQ_HANDLED;
 602 }
 603
 604 /*
 605  * There are three kinds of interrupts:
 606  *
 607  * 1) i801 signals transaction completion with one of these interrupts:
 608  *      INTR - Success
 609  *      DEV_ERR - Invalid command, NAK or communication timeout
 610  *      BUS_ERR - SMI# transaction collision
 611  *      FAILED - transaction was canceled due to a KILL request
 612  *    When any of these occur, update ->status and wake up the waitq.
 613  *    ->status must be cleared before kicking off the next transaction.
 614  *
 615  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 616  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 617  *
 618  * 3) Host Notify interrupts
 619  */
 620 static irqreturn_t i801_isr(int irq, void *dev_id)
 621 {
 622         struct i801_priv *priv = dev_id;
 623         u16 pcists;
 624         u8 status;
 625
 626         /* Confirm this is our interrupt */
 627         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 628         if (!(pcists & SMBPCISTS_INTS))
 629                 return IRQ_NONE;
 630
 631         if (priv->features & FEATURE_HOST_NOTIFY) {
 632                 status = inb_p(SMBSLVSTS(priv));
 633                 if (status & SMBSLVSTS_HST_NTFY_STS)
 634                         return i801_host_notify_isr(priv);
 635         }
 636
 637         status = inb_p(SMBHSTSTS(priv));
 638         if (status & SMBHSTSTS_BYTE_DONE)
 639                 i801_isr_byte_done(priv);
 640
 641         /*
 642          * Clear irq sources and report transaction result.
 643          * ->status must be cleared before the next transaction is started.
 644          */
 645         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 646         if (status) {
 647                 outb_p(status, SMBHSTSTS(priv));
 648                 priv->status = status;
 649                 wake_up(&priv->waitq);
 650         }
 651
 652         return IRQ_HANDLED;
 653 }
 654
 655 /*
 656  * For "byte-by-byte" block transactions:
 657  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 658  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 659  */
 660 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 661                                                union i2c_smbus_data *data,
 662                                                char read_write, int command,
 663                                                int hwpec)
 664 {
 665         int i, len;
 666         int smbcmd;
 667         int status;
 668         int result;
 669         const struct i2c_adapter *adap = &priv->adapter;
 670
 671         result = i801_check_pre(priv);
 672         if (result < 0)
 673                 return result;
 674
 675         len = data->block[0];
 676
 677         if (read_write == I2C_SMBUS_WRITE) {
 678                 outb_p(len, SMBHSTDAT0(priv));
 679                 outb_p(data->block[1], SMBBLKDAT(priv));
 680         }
 681
 682         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 683             read_write == I2C_SMBUS_READ)
 684                 smbcmd = I801_I2C_BLOCK_DATA;
 685         else
 686                 smbcmd = I801_BLOCK_DATA;
 687
 688         if (priv->features & FEATURE_IRQ) {
 689                 priv->is_read = (read_write == I2C_SMBUS_READ);
 690                 if (len == 1 && priv->is_read)
 691                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 692                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 693                 priv->len = len;
 694                 priv->count = 0;
 695                 priv->data = &data->block[1];
 696
 697                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 698                 result = wait_event_timeout(priv->waitq,
 699                                             (status = priv->status),
 700                                             adap->timeout);
 701                 if (!result) {
 702                         status = -ETIMEDOUT;
 703                         dev_warn(&priv->pci_dev->dev,
 704                                  "Timeout waiting for interrupt!\n");
 705                 }
 706                 priv->status = 0;
 707                 return i801_check_post(priv, status);
 708         }
 709
 710         if (len == 1 && read_write == I2C_SMBUS_READ)
 711                 smbcmd |= SMBHSTCNT_LAST_BYTE;
 712         outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 713
 714         for (i = 1; i <= len; i++) {
 715                 status = i801_wait_byte_done(priv);
 716                 if (status)
 717                         goto exit;
 718
 719                 if (i == 1 && read_write == I2C_SMBUS_READ
 720                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 721                         len = inb_p(SMBHSTDAT0(priv));
 722                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 723                                 dev_err(&priv->pci_dev->dev,
 724                                         "Illegal SMBus block read size %d\n",
 725                                         len);
 726                                 /* Recover */
 727                                 while (inb_p(SMBHSTSTS(priv)) &
 728                                        SMBHSTSTS_HOST_BUSY)
 729                                         outb_p(SMBHSTSTS_BYTE_DONE,
 730                                                SMBHSTSTS(priv));
 731                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 732                                 return -EPROTO;
 733                         }
 734                         data->block[0] = len;
 735                 }
 736
 737                 if (read_write == I2C_SMBUS_READ) {
 738                         data->block[i] = inb_p(SMBBLKDAT(priv));
 739                         if (i == len - 1)
 740                                 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
 741                 }
 742
 743                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 744                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 745
 746                 /* signals SMBBLKDAT ready */
 747                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 748         }
 749
 750         status = i801_wait_intr(priv);
 751 exit:
 752         return i801_check_post(priv, status);
 753 }
 754
 755 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 756 {
 757         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 758         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 759                 return -EIO;
 760         return 0;
 761 }
 762
 763 /* Block transaction function */
 764 static int i801_block_transaction(struct i801_priv *priv,
 765                                   union i2c_smbus_data *data, char read_write,
 766                                   int command, int hwpec)
 767 {
 768         int result = 0;
 769         unsigned char hostc;
 770
 771         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 772                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 773         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 774                 return -EPROTO;
 775
 776         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 777                 if (read_write == I2C_SMBUS_WRITE) {
 778                         /* set I2C_EN bit in configuration register */
 779                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 780                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 781                                               hostc | SMBHSTCFG_I2C_EN);
 782                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 783                         dev_err(&priv->pci_dev->dev,
 784                                 "I2C block read is unsupported!\n");
 785                         return -EOPNOTSUPP;
 786                 }
 787         }
 788
 789         /* Experience has shown that the block buffer can only be used for
 790            SMBus (not I2C) block transactions, even though the datasheet
 791            doesn't mention this limitation. */
 792         if ((priv->features & FEATURE_BLOCK_BUFFER)
 793          && command != I2C_SMBUS_I2C_BLOCK_DATA
 794          && i801_set_block_buffer_mode(priv) == 0)
 795                 result = i801_block_transaction_by_block(priv, data,
 796                                                          read_write, hwpec);
 797         else
 798                 result = i801_block_transaction_byte_by_byte(priv, data,
 799                                                              read_write,
 800                                                              command, hwpec);
 801
 802         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 803          && read_write == I2C_SMBUS_WRITE) {
 804                 /* restore saved configuration register value */
 805                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 806         }
 807         return result;
 808 }
 809
 810 /* Return negative errno on error. */
 811 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 812                        unsigned short flags, char read_write, u8 command,
 813                        int size, union i2c_smbus_data *data)
 814 {
 815         int hwpec;
 816         int block = 0;
 817         int ret = 0, xact = 0;
 818         struct i801_priv *priv = i2c_get_adapdata(adap);
 819
 820         mutex_lock(&priv->acpi_lock);
 821         if (priv->acpi_reserved) {
 822                 mutex_unlock(&priv->acpi_lock);
 823                 return -EBUSY;
 824         }
 825
 826         pm_runtime_get_sync(&priv->pci_dev->dev);
 827
 828         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 829                 && size != I2C_SMBUS_QUICK
 830                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 831
 832         switch (size) {
 833         case I2C_SMBUS_QUICK:
 834                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 835                        SMBHSTADD(priv));
 836                 xact = I801_QUICK;
 837                 break;
 838         case I2C_SMBUS_BYTE:
 839                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 840                        SMBHSTADD(priv));
 841                 if (read_write == I2C_SMBUS_WRITE)
 842                         outb_p(command, SMBHSTCMD(priv));
 843                 xact = I801_BYTE;
 844                 break;
 845         case I2C_SMBUS_BYTE_DATA:
 846                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 847                        SMBHSTADD(priv));
 848                 outb_p(command, SMBHSTCMD(priv));
 849                 if (read_write == I2C_SMBUS_WRITE)
 850                         outb_p(data->byte, SMBHSTDAT0(priv));
 851                 xact = I801_BYTE_DATA;
 852                 break;
 853         case I2C_SMBUS_WORD_DATA:
 854                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 855                        SMBHSTADD(priv));
 856                 outb_p(command, SMBHSTCMD(priv));
 857                 if (read_write == I2C_SMBUS_WRITE) {
 858                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 859                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 860                 }
 861                 xact = I801_WORD_DATA;
 862                 break;
 863         case I2C_SMBUS_BLOCK_DATA:
 864                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 865                        SMBHSTADD(priv));
 866                 outb_p(command, SMBHSTCMD(priv));
 867                 block = 1;
 868                 break;
 869         case I2C_SMBUS_I2C_BLOCK_DATA:
 870                 /*
 871                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 872                  * bit should be cleared here, even when reading.
 873                  * However if SPD Write Disable is set (Lynx Point and later),
 874                  * the read will fail if we don't set the R/#W bit.
 875                  */
 876                 outb_p(((addr & 0x7f) << 1) |
 877                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 878                         (read_write & 0x01) : 0),
 879                        SMBHSTADD(priv));
 880                 if (read_write == I2C_SMBUS_READ) {
 881                         /* NB: page 240 of ICH5 datasheet also shows
 882                          * that DATA1 is the cmd field when reading */
 883                         outb_p(command, SMBHSTDAT1(priv));
 884                 } else
 885                         outb_p(command, SMBHSTCMD(priv));
 886                 block = 1;
 887                 break;
 888         default:
 889                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 890                         size);
 891                 ret = -EOPNOTSUPP;
 892                 goto out;
 893         }
 894
 895         if (hwpec)      /* enable/disable hardware PEC */
 896                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 897         else
 898                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 899                        SMBAUXCTL(priv));
 900
 901         if (block)
 902                 ret = i801_block_transaction(priv, data, read_write, size,
 903                                              hwpec);
 904         else
 905                 ret = i801_transaction(priv, xact);
 906
 907         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 908            time, so we forcibly disable it after every transaction. Turn off
 909            E32B for the same reason. */
 910         if (hwpec || block)
 911                 outb_p(inb_p(SMBAUXCTL(priv)) &
 912                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 913
 914         if (block)
 915                 goto out;
 916         if (ret)
 917                 goto out;
 918         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 919                 goto out;
 920
 921         switch (xact & 0x7f) {
 922         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 923         case I801_BYTE_DATA:
 924                 data->byte = inb_p(SMBHSTDAT0(priv));
 925                 break;
 926         case I801_WORD_DATA:
 927                 data->word = inb_p(SMBHSTDAT0(priv)) +
 928                              (inb_p(SMBHSTDAT1(priv)) << 8);
 929                 break;
 930         }
 931
 932 out:
 933         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 934         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 935         mutex_unlock(&priv->acpi_lock);
 936         return ret;
 937 }
 938
 939
 940 static u32 i801_func(struct i2c_adapter *adapter)
 941 {
 942         struct i801_priv *priv = i2c_get_adapdata(adapter);
 943
 944         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 945                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 946                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 947                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 948                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 949                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 950                ((priv->features & FEATURE_HOST_NOTIFY) ?
 951                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 952 }
 953
 954 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 955 {
 956         struct i801_priv *priv = i2c_get_adapdata(adapter);
 957
 958         if (!(priv->features & FEATURE_HOST_NOTIFY))
 959                 return;
 960
 961         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 962                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 963                        SMBSLVCMD(priv));
 964
 965         /* clear Host Notify bit to allow a new notification */
 966         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 967 }
 968
 969 static void i801_disable_host_notify(struct i801_priv *priv)
 970 {
 971         if (!(priv->features & FEATURE_HOST_NOTIFY))
 972                 return;
 973
 974         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 975 }
 976
 977 static const struct i2c_algorithm smbus_algorithm = {
 978         .smbus_xfer     = i801_access,
 979         .functionality  = i801_func,
 980 };
 981
 982 static const struct pci_device_id i801_ids[] = {
 983         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 984         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 985         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 986         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 987         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 988         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 989         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 990         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 991         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 992         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 993         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1012         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1013         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1014         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1015         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1016         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1017         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1018         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1026         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1029         { 0, }
1030 };
1031
1032 MODULE_DEVICE_TABLE(pci, i801_ids);
1033
1034 #if defined CONFIG_X86 && defined CONFIG_DMI
1035 static unsigned char apanel_addr;
1036
1037 /* Scan the system ROM for the signature "FJKEYINF" */
1038 static __init const void __iomem *bios_signature(const void __iomem *bios)
1039 {
1040         ssize_t offset;
1041         const unsigned char signature[] = "FJKEYINF";
1042
1043         for (offset = 0; offset < 0x10000; offset += 0x10) {
1044                 if (check_signature(bios + offset, signature,
1045                                     sizeof(signature)-1))
1046                         return bios + offset;
1047         }
1048         return NULL;
1049 }
1050
1051 static void __init input_apanel_init(void)
1052 {
1053         void __iomem *bios;
1054         const void __iomem *p;
1055
1056         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1057         p = bios_signature(bios);
1058         if (p) {
1059                 /* just use the first address */
1060                 apanel_addr = readb(p + 8 + 3) >> 1;
1061         }
1062         iounmap(bios);
1063 }
1064
1065 struct dmi_onboard_device_info {
1066         const char *name;
1067         u8 type;
1068         unsigned short i2c_addr;
1069         const char *i2c_type;
1070 };
1071
1072 static const struct dmi_onboard_device_info dmi_devices[] = {
1073         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1074         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1075         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1076 };
1077
1078 static void dmi_check_onboard_device(u8 type, const char *name,
1079                                      struct i2c_adapter *adap)
1080 {
1081         int i;
1082         struct i2c_board_info info;
1083
1084         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1085                 /* & ~0x80, ignore enabled/disabled bit */
1086                 if ((type & ~0x80) != dmi_devices[i].type)
1087                         continue;
1088                 if (strcasecmp(name, dmi_devices[i].name))
1089                         continue;
1090
1091                 memset(&info, 0, sizeof(struct i2c_board_info));
1092                 info.addr = dmi_devices[i].i2c_addr;
1093                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1094                 i2c_new_device(adap, &info);
1095                 break;
1096         }
1097 }
1098
1099 /* We use our own function to check for onboard devices instead of
1100    dmi_find_device() as some buggy BIOS's have the devices we are interested
1101    in marked as disabled */
1102 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1103 {
1104         int i, count;
1105
1106         if (dm->type != 10)
1107                 return;
1108
1109         count = (dm->length - sizeof(struct dmi_header)) / 2;
1110         for (i = 0; i < count; i++) {
1111                 const u8 *d = (char *)(dm + 1) + (i * 2);
1112                 const char *name = ((char *) dm) + dm->length;
1113                 u8 type = d[0];
1114                 u8 s = d[1];
1115
1116                 if (!s)
1117                         continue;
1118                 s--;
1119                 while (s > 0 && name[0]) {
1120                         name += strlen(name) + 1;
1121                         s--;
1122                 }
1123                 if (name[0] == 0) /* Bogus string reference */
1124                         continue;
1125
1126                 dmi_check_onboard_device(type, name, adap);
1127         }
1128 }
1129
1130 /* Register optional slaves */
1131 static void i801_probe_optional_slaves(struct i801_priv *priv)
1132 {
1133         /* Only register slaves on main SMBus channel */
1134         if (priv->features & FEATURE_IDF)
1135                 return;
1136
1137         if (apanel_addr) {
1138                 struct i2c_board_info info;
1139
1140                 memset(&info, 0, sizeof(struct i2c_board_info));
1141                 info.addr = apanel_addr;
1142                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1143                 i2c_new_device(&priv->adapter, &info);
1144         }
1145
1146         if (dmi_name_in_vendors("FUJITSU"))
1147                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1148 }
1149 #else
1150 static void __init input_apanel_init(void) {}
1151 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1152 #endif  /* CONFIG_X86 && CONFIG_DMI */
1153
1154 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1155 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1156         .gpio_chip = "gpio_ich",
1157         .values = { 0x02, 0x03 },
1158         .n_values = 2,
1159         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1160         .gpios = { 52, 53 },
1161         .n_gpios = 2,
1162 };
1163
1164 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1165         .gpio_chip = "gpio_ich",
1166         .values = { 0x02, 0x03, 0x01 },
1167         .n_values = 3,
1168         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1169         .gpios = { 52, 53 },
1170         .n_gpios = 2,
1171 };
1172
1173 static const struct dmi_system_id mux_dmi_table[] = {
1174         {
1175                 .matches = {
1176                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1177                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1178                 },
1179                 .driver_data = &i801_mux_config_asus_z8_d12,
1180         },
1181         {
1182                 .matches = {
1183                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1184                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1185                 },
1186                 .driver_data = &i801_mux_config_asus_z8_d12,
1187         },
1188         {
1189                 .matches = {
1190                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1191                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1192                 },
1193                 .driver_data = &i801_mux_config_asus_z8_d12,
1194         },
1195         {
1196                 .matches = {
1197                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1198                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1199                 },
1200                 .driver_data = &i801_mux_config_asus_z8_d12,
1201         },
1202         {
1203                 .matches = {
1204                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1205                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1206                 },
1207                 .driver_data = &i801_mux_config_asus_z8_d12,
1208         },
1209         {
1210                 .matches = {
1211                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1212                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1213                 },
1214                 .driver_data = &i801_mux_config_asus_z8_d12,
1215         },
1216         {
1217                 .matches = {
1218                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1219                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1220                 },
1221                 .driver_data = &i801_mux_config_asus_z8_d18,
1222         },
1223         {
1224                 .matches = {
1225                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1226                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1227                 },
1228                 .driver_data = &i801_mux_config_asus_z8_d18,
1229         },
1230         {
1231                 .matches = {
1232                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1233                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1234                 },
1235                 .driver_data = &i801_mux_config_asus_z8_d12,
1236         },
1237         { }
1238 };
1239
1240 /* Setup multiplexing if needed */
1241 static int i801_add_mux(struct i801_priv *priv)
1242 {
1243         struct device *dev = &priv->adapter.dev;
1244         const struct i801_mux_config *mux_config;
1245         struct i2c_mux_gpio_platform_data gpio_data;
1246         int err;
1247
1248         if (!priv->mux_drvdata)
1249                 return 0;
1250         mux_config = priv->mux_drvdata;
1251
1252         /* Prepare the platform data */
1253         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1254         gpio_data.parent = priv->adapter.nr;
1255         gpio_data.values = mux_config->values;
1256         gpio_data.n_values = mux_config->n_values;
1257         gpio_data.classes = mux_config->classes;
1258         gpio_data.gpio_chip = mux_config->gpio_chip;
1259         gpio_data.gpios = mux_config->gpios;
1260         gpio_data.n_gpios = mux_config->n_gpios;
1261         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1262
1263         /* Register the mux device */
1264         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1265                                 PLATFORM_DEVID_AUTO, &gpio_data,
1266                                 sizeof(struct i2c_mux_gpio_platform_data));
1267         if (IS_ERR(priv->mux_pdev)) {
1268                 err = PTR_ERR(priv->mux_pdev);
1269                 priv->mux_pdev = NULL;
1270                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1271                 return err;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static void i801_del_mux(struct i801_priv *priv)
1278 {
1279         if (priv->mux_pdev)
1280                 platform_device_unregister(priv->mux_pdev);
1281 }
1282
1283 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1284 {
1285         const struct dmi_system_id *id;
1286         const struct i801_mux_config *mux_config;
1287         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1288         int i;
1289
1290         id = dmi_first_match(mux_dmi_table);
1291         if (id) {
1292                 /* Remove branch classes from trunk */
1293                 mux_config = id->driver_data;
1294                 for (i = 0; i < mux_config->n_values; i++)
1295                         class &= ~mux_config->classes[i];
1296
1297                 /* Remember for later */
1298                 priv->mux_drvdata = mux_config;
1299         }
1300
1301         return class;
1302 }
1303 #else
1304 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1305 static inline void i801_del_mux(struct i801_priv *priv) { }
1306
1307 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1308 {
1309         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1310 }
1311 #endif
1312
1313 static const struct itco_wdt_platform_data tco_platform_data = {
1314         .name = "Intel PCH",
1315         .version = 4,
1316 };
1317
1318 static DEFINE_SPINLOCK(p2sb_spinlock);
1319
1320 static void i801_add_tco(struct i801_priv *priv)
1321 {
1322         struct pci_dev *pci_dev = priv->pci_dev;
1323         struct resource tco_res[3], *res;
1324         struct platform_device *pdev;
1325         unsigned int devfn;
1326         u32 tco_base, tco_ctl;
1327         u32 base_addr, ctrl_val;
1328         u64 base64_addr;
1329         u8 hidden;
1330
1331         if (!(priv->features & FEATURE_TCO))
1332                 return;
1333
1334         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1335         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1336         if (!(tco_ctl & TCOCTL_EN))
1337                 return;
1338
1339         memset(tco_res, 0, sizeof(tco_res));
1340
1341         res = &tco_res[ICH_RES_IO_TCO];
1342         res->start = tco_base & ~1;
1343         res->end = res->start + 32 - 1;
1344         res->flags = IORESOURCE_IO;
1345
1346         /*
1347          * Power Management registers.
1348          */
1349         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1350         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1351
1352         res = &tco_res[ICH_RES_IO_SMI];
1353         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1354         res->end = res->start + 3;
1355         res->flags = IORESOURCE_IO;
1356
1357         /*
1358          * Enable the ACPI I/O space.
1359          */
1360         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1361         ctrl_val |= ACPICTRL_EN;
1362         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1363
1364         /*
1365          * We must access the NO_REBOOT bit over the Primary to Sideband
1366          * bridge (P2SB). The BIOS prevents the P2SB device from being
1367          * enumerated by the PCI subsystem, so we need to unhide/hide it
1368          * to lookup the P2SB BAR.
1369          */
1370         spin_lock(&p2sb_spinlock);
1371
1372         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1373
1374         /* Unhide the P2SB device, if it is hidden */
1375         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1376         if (hidden)
1377                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1378
1379         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1380         base64_addr = base_addr & 0xfffffff0;
1381
1382         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1383         base64_addr |= (u64)base_addr << 32;
1384
1385         /* Hide the P2SB device, if it was hidden before */
1386         if (hidden)
1387                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1388         spin_unlock(&p2sb_spinlock);
1389
1390         res = &tco_res[ICH_RES_MEM_OFF];
1391         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1392                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1393         else
1394                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1395
1396         res->end = res->start + 3;
1397         res->flags = IORESOURCE_MEM;
1398
1399         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1400                                                  tco_res, 3, &tco_platform_data,
1401                                                  sizeof(tco_platform_data));
1402         if (IS_ERR(pdev)) {
1403                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1404                 return;
1405         }
1406
1407         priv->tco_pdev = pdev;
1408 }
1409
1410 #ifdef CONFIG_ACPI
1411 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1412                                       acpi_physical_address address)
1413 {
1414         return address >= priv->smba &&
1415                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1416 }
1417
1418 static acpi_status
1419 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1420                      u64 *value, void *handler_context, void *region_context)
1421 {
1422         struct i801_priv *priv = handler_context;
1423         struct pci_dev *pdev = priv->pci_dev;
1424         acpi_status status;
1425
1426         /*
1427          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1428          * further access from the driver itself. This device is now owned
1429          * by the system firmware.
1430          */
1431         mutex_lock(&priv->acpi_lock);
1432
1433         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1434                 priv->acpi_reserved = true;
1435
1436                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1437                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1438
1439                 /*
1440                  * BIOS is accessing the host controller so prevent it from
1441                  * suspending automatically from now on.
1442                  */
1443                 pm_runtime_get_sync(&pdev->dev);
1444         }
1445
1446         if ((function & ACPI_IO_MASK) == ACPI_READ)
1447                 status = acpi_os_read_port(address, (u32 *)value, bits);
1448         else
1449                 status = acpi_os_write_port(address, (u32)*value, bits);
1450
1451         mutex_unlock(&priv->acpi_lock);
1452
1453         return status;
1454 }
1455
1456 static int i801_acpi_probe(struct i801_priv *priv)
1457 {
1458         struct acpi_device *adev;
1459         acpi_status status;
1460
1461         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1462         if (adev) {
1463                 status = acpi_install_address_space_handler(adev->handle,
1464                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1465                                 NULL, priv);
1466                 if (ACPI_SUCCESS(status))
1467                         return 0;
1468         }
1469
1470         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1471 }
1472
1473 static void i801_acpi_remove(struct i801_priv *priv)
1474 {
1475         struct acpi_device *adev;
1476
1477         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1478         if (!adev)
1479                 return;
1480
1481         acpi_remove_address_space_handler(adev->handle,
1482                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1483
1484         mutex_lock(&priv->acpi_lock);
1485         if (priv->acpi_reserved)
1486                 pm_runtime_put(&priv->pci_dev->dev);
1487         mutex_unlock(&priv->acpi_lock);
1488 }
1489 #else
1490 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1491 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1492 #endif
1493
1494 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1495 {
1496         unsigned char hstcfg = priv->original_hstcfg;
1497
1498         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1499         hstcfg |= SMBHSTCFG_HST_EN;
1500         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1501         return hstcfg;
1502 }
1503
1504 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1505 {
1506         unsigned char temp;
1507         int err, i;
1508         struct i801_priv *priv;
1509
1510         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1511         if (!priv)
1512                 return -ENOMEM;
1513
1514         i2c_set_adapdata(&priv->adapter, priv);
1515         priv->adapter.owner = THIS_MODULE;
1516         priv->adapter.class = i801_get_adapter_class(priv);
1517         priv->adapter.algo = &smbus_algorithm;
1518         priv->adapter.dev.parent = &dev->dev;
1519         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1520         priv->adapter.retries = 3;
1521         mutex_init(&priv->acpi_lock);
1522
1523         priv->pci_dev = dev;
1524         switch (dev->device) {
1525         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1526         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1527         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1528         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1529         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1530         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1531         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1532         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1533         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1534                 priv->features |= FEATURE_I2C_BLOCK_READ;
1535                 priv->features |= FEATURE_IRQ;
1536                 priv->features |= FEATURE_SMBUS_PEC;
1537                 priv->features |= FEATURE_BLOCK_BUFFER;
1538                 /* If we have ACPI based watchdog use that instead */
1539                 if (!acpi_has_watchdog())
1540                         priv->features |= FEATURE_TCO;
1541                 priv->features |= FEATURE_HOST_NOTIFY;
1542                 break;
1543
1544         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1545         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1546         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1547         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1548         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1549         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1550                 priv->features |= FEATURE_IDF;
1551                 /* fall through */
1552         default:
1553                 priv->features |= FEATURE_I2C_BLOCK_READ;
1554                 priv->features |= FEATURE_IRQ;
1555                 /* fall through */
1556         case PCI_DEVICE_ID_INTEL_82801DB_3:
1557                 priv->features |= FEATURE_SMBUS_PEC;
1558                 priv->features |= FEATURE_BLOCK_BUFFER;
1559                 /* fall through */
1560         case PCI_DEVICE_ID_INTEL_82801CA_3:
1561                 priv->features |= FEATURE_HOST_NOTIFY;
1562                 /* fall through */
1563         case PCI_DEVICE_ID_INTEL_82801BA_2:
1564         case PCI_DEVICE_ID_INTEL_82801AB_3:
1565         case PCI_DEVICE_ID_INTEL_82801AA_3:
1566                 break;
1567         }
1568
1569         /* Disable features on user request */
1570         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1571                 if (priv->features & disable_features & (1 << i))
1572                         dev_notice(&dev->dev, "%s disabled by user\n",
1573                                    i801_feature_names[i]);
1574         }
1575         priv->features &= ~disable_features;
1576
1577         err = pcim_enable_device(dev);
1578         if (err) {
1579                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1580                         err);
1581                 return err;
1582         }
1583         pcim_pin_device(dev);
1584
1585         /* Determine the address of the SMBus area */
1586         priv->smba = pci_resource_start(dev, SMBBAR);
1587         if (!priv->smba) {
1588                 dev_err(&dev->dev,
1589                         "SMBus base address uninitialized, upgrade BIOS\n");
1590                 return -ENODEV;
1591         }
1592
1593         if (i801_acpi_probe(priv))
1594                 return -ENODEV;
1595
1596         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1597                                  dev_driver_string(&dev->dev));
1598         if (err) {
1599                 dev_err(&dev->dev,
1600                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1601                         priv->smba,
1602                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1603                 i801_acpi_remove(priv);
1604                 return err;
1605         }
1606
1607         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1608         temp = i801_setup_hstcfg(priv);
1609         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1610                 dev_info(&dev->dev, "Enabling SMBus device\n");
1611
1612         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1613                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1614                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1615                 priv->features &= ~FEATURE_IRQ;
1616         }
1617         if (temp & SMBHSTCFG_SPD_WD)
1618                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1619
1620         /* Clear special mode bits */
1621         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1622                 outb_p(inb_p(SMBAUXCTL(priv)) &
1623                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1624
1625         /* Remember original Host Notify setting */
1626         if (priv->features & FEATURE_HOST_NOTIFY)
1627                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1628
1629         /* Default timeout in interrupt mode: 200 ms */
1630         priv->adapter.timeout = HZ / 5;
1631
1632         if (dev->irq == IRQ_NOTCONNECTED)
1633                 priv->features &= ~FEATURE_IRQ;
1634
1635         if (priv->features & FEATURE_IRQ) {
1636                 u16 pcictl, pcists;
1637
1638                 /* Complain if an interrupt is already pending */
1639                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1640                 if (pcists & SMBPCISTS_INTS)
1641                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1642
1643                 /* Check if interrupts have been disabled */
1644                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1645                 if (pcictl & SMBPCICTL_INTDIS) {
1646                         dev_info(&dev->dev, "Interrupts are disabled\n");
1647                         priv->features &= ~FEATURE_IRQ;
1648                 }
1649         }
1650
1651         if (priv->features & FEATURE_IRQ) {
1652                 init_waitqueue_head(&priv->waitq);
1653
1654                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1655                                        IRQF_SHARED,
1656                                        dev_driver_string(&dev->dev), priv);
1657                 if (err) {
1658                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1659                                 dev->irq, err);
1660                         priv->features &= ~FEATURE_IRQ;
1661                 }
1662         }
1663         dev_info(&dev->dev, "SMBus using %s\n",
1664                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1665
1666         i801_add_tco(priv);
1667
1668         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1669                 "SMBus I801 adapter at %04lx", priv->smba);
1670         err = i2c_add_adapter(&priv->adapter);
1671         if (err) {
1672                 platform_device_unregister(priv->tco_pdev);
1673                 i801_acpi_remove(priv);
1674                 return err;
1675         }
1676
1677         i801_enable_host_notify(&priv->adapter);
1678
1679         i801_probe_optional_slaves(priv);
1680         /* We ignore errors - multiplexing is optional */
1681         i801_add_mux(priv);
1682
1683         pci_set_drvdata(dev, priv);
1684
1685         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1686         pm_runtime_use_autosuspend(&dev->dev);
1687         pm_runtime_put_autosuspend(&dev->dev);
1688         pm_runtime_allow(&dev->dev);
1689
1690         return 0;
1691 }
1692
1693 static void i801_remove(struct pci_dev *dev)
1694 {
1695         struct i801_priv *priv = pci_get_drvdata(dev);
1696
1697         pm_runtime_forbid(&dev->dev);
1698         pm_runtime_get_noresume(&dev->dev);
1699
1700         i801_disable_host_notify(priv);
1701         i801_del_mux(priv);
1702         i2c_del_adapter(&priv->adapter);
1703         i801_acpi_remove(priv);
1704         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1705
1706         platform_device_unregister(priv->tco_pdev);
1707
1708         /*
1709          * do not call pci_disable_device(dev) since it can cause hard hangs on
1710          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1711          */
1712 }
1713
1714 static void i801_shutdown(struct pci_dev *dev)
1715 {
1716         struct i801_priv *priv = pci_get_drvdata(dev);
1717
1718         /* Restore config registers to avoid hard hang on some systems */
1719         i801_disable_host_notify(priv);
1720         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1721 }
1722
1723 #ifdef CONFIG_PM
1724 static int i801_suspend(struct device *dev)
1725 {
1726         struct pci_dev *pci_dev = to_pci_dev(dev);
1727         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1728
1729         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1730         return 0;
1731 }
1732
1733 static int i801_resume(struct device *dev)
1734 {
1735         struct pci_dev *pci_dev = to_pci_dev(dev);
1736         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1737
1738         i801_setup_hstcfg(priv);
1739         i801_enable_host_notify(&priv->adapter);
1740
1741         return 0;
1742 }
1743 #endif
1744
1745 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1746                             i801_resume, NULL);
1747
1748 static struct pci_driver i801_driver = {
1749         .name           = "i801_smbus",
1750         .id_table       = i801_ids,
1751         .probe          = i801_probe,
1752         .remove         = i801_remove,
1753         .shutdown       = i801_shutdown,
1754         .driver         = {
1755                 .pm     = &i801_pm_ops,
1756         },
1757 };
1758
1759 static int __init i2c_i801_init(void)
1760 {
1761         if (dmi_name_in_vendors("FUJITSU"))
1762                 input_apanel_init();
1763         return pci_register_driver(&i801_driver);
1764 }
1765
1766 static void __exit i2c_i801_exit(void)
1767 {
1768         pci_unregister_driver(&i801_driver);
1769 }
1770
1771 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1772 MODULE_DESCRIPTION("I801 SMBus driver");
1773 MODULE_LICENSE("GPL");
1774
1775 module_init(i2c_i801_init);
1776 module_exit(i2c_i801_exit);