drivers/i2c/busses/i2c-emev2.c

   1 /*
   2  * I2C driver for the Renesas EMEV2 SoC
   3  *
   4  * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
   5  * Copyright 2013 Codethink Ltd.
   6  * Copyright 2010-2015 Renesas Electronics Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2
  10  * as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/completion.h>
  15 #include <linux/device.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched.h>
  25
  26 /* I2C Registers */
  27 #define I2C_OFS_IICACT0         0x00    /* start */
  28 #define I2C_OFS_IIC0            0x04    /* shift */
  29 #define I2C_OFS_IICC0           0x08    /* control */
  30 #define I2C_OFS_SVA0            0x0c    /* slave address */
  31 #define I2C_OFS_IICCL0          0x10    /* clock select */
  32 #define I2C_OFS_IICX0           0x14    /* extension */
  33 #define I2C_OFS_IICS0           0x18    /* status */
  34 #define I2C_OFS_IICSE0          0x1c    /* status For emulation */
  35 #define I2C_OFS_IICF0           0x20    /* IIC flag */
  36
  37 /* I2C IICACT0 Masks */
  38 #define I2C_BIT_IICE0           0x0001
  39
  40 /* I2C IICC0 Masks */
  41 #define I2C_BIT_LREL0           0x0040
  42 #define I2C_BIT_WREL0           0x0020
  43 #define I2C_BIT_SPIE0           0x0010
  44 #define I2C_BIT_WTIM0           0x0008
  45 #define I2C_BIT_ACKE0           0x0004
  46 #define I2C_BIT_STT0            0x0002
  47 #define I2C_BIT_SPT0            0x0001
  48
  49 /* I2C IICCL0 Masks */
  50 #define I2C_BIT_SMC0            0x0008
  51 #define I2C_BIT_DFC0            0x0004
  52
  53 /* I2C IICSE0 Masks */
  54 #define I2C_BIT_MSTS0           0x0080
  55 #define I2C_BIT_ALD0            0x0040
  56 #define I2C_BIT_EXC0            0x0020
  57 #define I2C_BIT_COI0            0x0010
  58 #define I2C_BIT_TRC0            0x0008
  59 #define I2C_BIT_ACKD0           0x0004
  60 #define I2C_BIT_STD0            0x0002
  61 #define I2C_BIT_SPD0            0x0001
  62
  63 /* I2C IICF0 Masks */
  64 #define I2C_BIT_STCF            0x0080
  65 #define I2C_BIT_IICBSY          0x0040
  66 #define I2C_BIT_STCEN           0x0002
  67 #define I2C_BIT_IICRSV          0x0001
  68
  69 struct em_i2c_device {
  70         void __iomem *base;
  71         struct i2c_adapter adap;
  72         struct completion msg_done;
  73         struct clk *sclk;
  74         struct i2c_client *slave;
  75         int irq;
  76 };
  77
  78 static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
  79 {
  80         writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
  81 }
  82
  83 static int em_i2c_wait_for_event(struct em_i2c_device *priv)
  84 {
  85         unsigned long time_left;
  86         int status;
  87
  88         reinit_completion(&priv->msg_done);
  89
  90         time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
  91
  92         if (!time_left)
  93                 return -ETIMEDOUT;
  94
  95         status = readb(priv->base + I2C_OFS_IICSE0);
  96         return status & I2C_BIT_ALD0 ? -EAGAIN : status;
  97 }
  98
  99 static void em_i2c_stop(struct em_i2c_device *priv)
 100 {
 101         /* Send Stop condition */
 102         em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
 103
 104         /* Wait for stop condition */
 105         em_i2c_wait_for_event(priv);
 106 }
 107
 108 static void em_i2c_reset(struct i2c_adapter *adap)
 109 {
 110         struct em_i2c_device *priv = i2c_get_adapdata(adap);
 111         int retr;
 112
 113         /* If I2C active */
 114         if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
 115                 /* Disable I2C operation */
 116                 writeb(0, priv->base + I2C_OFS_IICACT0);
 117
 118                 retr = 1000;
 119                 while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
 120                         retr--;
 121                 WARN_ON(retr == 0);
 122         }
 123
 124         /* Transfer mode set */
 125         writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
 126
 127         /* Can Issue start without detecting a stop, Reservation disabled. */
 128         writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
 129
 130         /* I2C enable, 9 bit interrupt mode */
 131         writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
 132
 133         /* Enable I2C operation */
 134         writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
 135
 136         retr = 1000;
 137         while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
 138                 retr--;
 139         WARN_ON(retr == 0);
 140 }
 141
 142 static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
 143                                 int stop)
 144 {
 145         struct em_i2c_device *priv = i2c_get_adapdata(adap);
 146         int count, status, read = !!(msg->flags & I2C_M_RD);
 147
 148         /* Send start condition */
 149         em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
 150         em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
 151
 152         /* Send slave address and R/W type */
 153         writeb((msg->addr << 1) | read, priv->base + I2C_OFS_IIC0);
 154
 155         /* Wait for transaction */
 156         status = em_i2c_wait_for_event(priv);
 157         if (status < 0)
 158                 goto out_reset;
 159
 160         /* Received NACK (result of setting slave address and R/W) */
 161         if (!(status & I2C_BIT_ACKD0)) {
 162                 em_i2c_stop(priv);
 163                 goto out;
 164         }
 165
 166         /* Extra setup for read transactions */
 167         if (read) {
 168                 /* 8 bit interrupt mode */
 169                 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
 170                 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
 171
 172                 /* Wait for transaction */
 173                 status = em_i2c_wait_for_event(priv);
 174                 if (status < 0)
 175                         goto out_reset;
 176         }
 177
 178         /* Send / receive data */
 179         for (count = 0; count < msg->len; count++) {
 180                 if (read) { /* Read transaction */
 181                         msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
 182                         em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
 183
 184                 } else { /* Write transaction */
 185                         /* Received NACK */
 186                         if (!(status & I2C_BIT_ACKD0)) {
 187                                 em_i2c_stop(priv);
 188                                 goto out;
 189                         }
 190
 191                         /* Write data */
 192                         writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
 193                 }
 194
 195                 /* Wait for R/W transaction */
 196                 status = em_i2c_wait_for_event(priv);
 197                 if (status < 0)
 198                         goto out_reset;
 199         }
 200
 201         if (stop)
 202                 em_i2c_stop(priv);
 203
 204         return count;
 205
 206 out_reset:
 207         em_i2c_reset(adap);
 208 out:
 209         return status < 0 ? status : -ENXIO;
 210 }
 211
 212 static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 213         int num)
 214 {
 215         struct em_i2c_device *priv = i2c_get_adapdata(adap);
 216         int ret, i;
 217
 218         if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
 219                 return -EAGAIN;
 220
 221         for (i = 0; i < num; i++) {
 222                 ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
 223                 if (ret < 0)
 224                         return ret;
 225         }
 226
 227         /* I2C transfer completed */
 228         return num;
 229 }
 230
 231 static bool em_i2c_slave_irq(struct em_i2c_device *priv)
 232 {
 233         u8 status, value;
 234         enum i2c_slave_event event;
 235         int ret;
 236
 237         if (!priv->slave)
 238                 return false;
 239
 240         status = readb(priv->base + I2C_OFS_IICSE0);
 241
 242         /* Extension code, do not participate */
 243         if (status & I2C_BIT_EXC0) {
 244                 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
 245                 return true;
 246         }
 247
 248         /* Stop detected, we don't know if it's for slave or master */
 249         if (status & I2C_BIT_SPD0) {
 250                 /* Notify slave device */
 251                 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
 252                 /* Pretend we did not handle the interrupt */
 253                 return false;
 254         }
 255
 256         /* Only handle interrupts addressed to us */
 257         if (!(status & I2C_BIT_COI0))
 258                 return false;
 259
 260         /* Enable stop interrupts */
 261         em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0);
 262
 263         /* Transmission or Reception */
 264         if (status & I2C_BIT_TRC0) {
 265                 if (status & I2C_BIT_ACKD0) {
 266                         /* 9 bit interrupt mode */
 267                         em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0);
 268
 269                         /* Send data */
 270                         event = status & I2C_BIT_STD0 ?
 271                                 I2C_SLAVE_READ_REQUESTED :
 272                                 I2C_SLAVE_READ_PROCESSED;
 273                         i2c_slave_event(priv->slave, event, &value);
 274                         writeb(value, priv->base + I2C_OFS_IIC0);
 275                 } else {
 276                         /* NACK, stop transmitting */
 277                         em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
 278                 }
 279         } else {
 280                 /* 8 bit interrupt mode */
 281                 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0,
 282                                 I2C_OFS_IICC0);
 283                 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0,
 284                                 I2C_OFS_IICC0);
 285
 286                 if (status & I2C_BIT_STD0) {
 287                         i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED,
 288                                         &value);
 289                 } else {
 290                         /* Recv data */
 291                         value = readb(priv->base + I2C_OFS_IIC0);
 292                         ret = i2c_slave_event(priv->slave,
 293                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 294                         if (ret < 0)
 295                                 em_clear_set_bit(priv, I2C_BIT_ACKE0, 0,
 296                                                 I2C_OFS_IICC0);
 297                 }
 298         }
 299
 300         return true;
 301 }
 302
 303 static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
 304 {
 305         struct em_i2c_device *priv = dev_id;
 306
 307         if (em_i2c_slave_irq(priv))
 308                 return IRQ_HANDLED;
 309
 310         complete(&priv->msg_done);
 311
 312         return IRQ_HANDLED;
 313 }
 314
 315 static u32 em_i2c_func(struct i2c_adapter *adap)
 316 {
 317         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
 318 }
 319
 320 static int em_i2c_reg_slave(struct i2c_client *slave)
 321 {
 322         struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
 323
 324         if (priv->slave)
 325                 return -EBUSY;
 326
 327         if (slave->flags & I2C_CLIENT_TEN)
 328                 return -EAFNOSUPPORT;
 329
 330         priv->slave = slave;
 331
 332         /* Set slave address */
 333         writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0);
 334
 335         return 0;
 336 }
 337
 338 static int em_i2c_unreg_slave(struct i2c_client *slave)
 339 {
 340         struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
 341
 342         WARN_ON(!priv->slave);
 343
 344         writeb(0, priv->base + I2C_OFS_SVA0);
 345
 346         /*
 347          * Wait for interrupt to finish. New slave irqs cannot happen because we
 348          * cleared the slave address and, thus, only extension codes will be
 349          * detected which do not use the slave ptr.
 350          */
 351         synchronize_irq(priv->irq);
 352         priv->slave = NULL;
 353
 354         return 0;
 355 }
 356
 357 static struct i2c_algorithm em_i2c_algo = {
 358         .master_xfer = em_i2c_xfer,
 359         .functionality = em_i2c_func,
 360         .reg_slave      = em_i2c_reg_slave,
 361         .unreg_slave    = em_i2c_unreg_slave,
 362 };
 363
 364 static int em_i2c_probe(struct platform_device *pdev)
 365 {
 366         struct em_i2c_device *priv;
 367         struct resource *r;
 368         int ret;
 369
 370         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 371         if (!priv)
 372                 return -ENOMEM;
 373
 374         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 375         priv->base = devm_ioremap_resource(&pdev->dev, r);
 376         if (IS_ERR(priv->base))
 377                 return PTR_ERR(priv->base);
 378
 379         strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
 380
 381         priv->sclk = devm_clk_get(&pdev->dev, "sclk");
 382         if (IS_ERR(priv->sclk))
 383                 return PTR_ERR(priv->sclk);
 384
 385         clk_prepare_enable(priv->sclk);
 386
 387         priv->adap.timeout = msecs_to_jiffies(100);
 388         priv->adap.retries = 5;
 389         priv->adap.dev.parent = &pdev->dev;
 390         priv->adap.algo = &em_i2c_algo;
 391         priv->adap.owner = THIS_MODULE;
 392         priv->adap.dev.of_node = pdev->dev.of_node;
 393
 394         init_completion(&priv->msg_done);
 395
 396         platform_set_drvdata(pdev, priv);
 397         i2c_set_adapdata(&priv->adap, priv);
 398
 399         em_i2c_reset(&priv->adap);
 400
 401         ret = platform_get_irq(pdev, 0);
 402         if (ret < 0)
 403                 goto err_clk;
 404         priv->irq = ret;
 405         ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0,
 406                                 "em_i2c", priv);
 407         if (ret)
 408                 goto err_clk;
 409
 410         ret = i2c_add_adapter(&priv->adap);
 411
 412         if (ret)
 413                 goto err_clk;
 414
 415         dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr,
 416                  priv->irq);
 417
 418         return 0;
 419
 420 err_clk:
 421         clk_disable_unprepare(priv->sclk);
 422         return ret;
 423 }
 424
 425 static int em_i2c_remove(struct platform_device *dev)
 426 {
 427         struct em_i2c_device *priv = platform_get_drvdata(dev);
 428
 429         i2c_del_adapter(&priv->adap);
 430         clk_disable_unprepare(priv->sclk);
 431
 432         return 0;
 433 }
 434
 435 static const struct of_device_id em_i2c_ids[] = {
 436         { .compatible = "renesas,iic-emev2", },
 437         { }
 438 };
 439
 440 static struct platform_driver em_i2c_driver = {
 441         .probe = em_i2c_probe,
 442         .remove = em_i2c_remove,
 443         .driver = {
 444                 .name = "em-i2c",
 445                 .of_match_table = em_i2c_ids,
 446         }
 447 };
 448 module_platform_driver(em_i2c_driver);
 449
 450 MODULE_DESCRIPTION("EMEV2 I2C bus driver");
 451 MODULE_AUTHOR("Ian Molton and Wolfram Sang <wsa@sang-engineering.com>");
 452 MODULE_LICENSE("GPL v2");
 453 MODULE_DEVICE_TABLE(of, em_i2c_ids);