1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/export.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/swab.h>
26 #include <linux/types.h>
27 #include <linux/units.h>
29 #include "i2c-designware-core.h"
31 static char *abort_sources[] = {
32 [ABRT_7B_ADDR_NOACK] =
33 "slave address not acknowledged (7bit mode)",
34 [ABRT_10ADDR1_NOACK] =
35 "first address byte not acknowledged (10bit mode)",
36 [ABRT_10ADDR2_NOACK] =
37 "second address byte not acknowledged (10bit mode)",
39 "data not acknowledged",
41 "no acknowledgement for a general call",
43 "read after general call",
45 "start byte acknowledged",
46 [ABRT_SBYTE_NORSTRT] =
47 "trying to send start byte when restart is disabled",
48 [ABRT_10B_RD_NORSTRT] =
49 "trying to read when restart is disabled (10bit mode)",
51 "trying to use disabled adapter",
54 [ABRT_SLAVE_FLUSH_TXFIFO] =
55 "read command so flush old data in the TX FIFO",
56 [ABRT_SLAVE_ARBLOST] =
57 "slave lost the bus while transmitting data to a remote master",
58 [ABRT_SLAVE_RD_INTX] =
59 "incorrect slave-transmitter mode configuration",
62 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
64 struct dw_i2c_dev *dev = context;
66 *val = readl(dev->base + reg);
71 static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
73 struct dw_i2c_dev *dev = context;
75 writel(val, dev->base + reg);
80 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
82 struct dw_i2c_dev *dev = context;
84 *val = swab32(readl(dev->base + reg));
89 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
91 struct dw_i2c_dev *dev = context;
93 writel(swab32(val), dev->base + reg);
98 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
100 struct dw_i2c_dev *dev = context;
102 *val = readw(dev->base + reg) |
103 (readw(dev->base + reg + 2) << 16);
108 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
110 struct dw_i2c_dev *dev = context;
112 writew(val, dev->base + reg);
113 writew(val >> 16, dev->base + reg + 2);
119 * i2c_dw_init_regmap() - Initialize registers map
120 * @dev: device private data
122 * Autodetects needed register access mode and creates the regmap with
123 * corresponding read/write callbacks. This must be called before doing any
124 * other register access.
126 int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
128 struct regmap_config map_cfg = {
132 .disable_locking = true,
133 .reg_read = dw_reg_read,
134 .reg_write = dw_reg_write,
135 .max_register = DW_IC_COMP_TYPE,
141 * Skip detecting the registers map configuration if the regmap has
142 * already been provided by a higher code.
147 ret = i2c_dw_acquire_lock(dev);
151 reg = readl(dev->base + DW_IC_COMP_TYPE);
152 i2c_dw_release_lock(dev);
154 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
155 map_cfg.reg_read = dw_reg_read_swab;
156 map_cfg.reg_write = dw_reg_write_swab;
157 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
158 map_cfg.reg_read = dw_reg_read_word;
159 map_cfg.reg_write = dw_reg_write_word;
160 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
162 "Unknown Synopsys component type: 0x%08x\n", reg);
167 * Note we'll check the return value of the regmap IO accessors only
168 * at the probe stage. The rest of the code won't do this because
169 * basically we have MMIO-based regmap so non of the read/write methods
172 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
173 if (IS_ERR(dev->map)) {
174 dev_err(dev->dev, "Failed to init the registers map\n");
175 return PTR_ERR(dev->map);
181 static const u32 supported_speeds[] = {
182 I2C_MAX_HIGH_SPEED_MODE_FREQ,
183 I2C_MAX_FAST_MODE_PLUS_FREQ,
184 I2C_MAX_FAST_MODE_FREQ,
185 I2C_MAX_STANDARD_MODE_FREQ,
188 int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
190 struct i2c_timings *t = &dev->timings;
194 * Only standard mode at 100kHz, fast mode at 400kHz,
195 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
197 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
198 if (t->bus_freq_hz == supported_speeds[i])
203 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
208 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
212 #include <linux/dmi.h>
215 * The HCNT/LCNT information coming from ACPI should be the most accurate
216 * for given platform. However, some systems get it wrong. On such systems
217 * we get better results by calculating those based on the input clock.
219 static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
221 .ident = "Dell Inspiron 7348",
223 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
224 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
230 static void i2c_dw_acpi_params(struct device *device, char method[],
231 u16 *hcnt, u16 *lcnt, u32 *sda_hold)
233 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
234 acpi_handle handle = ACPI_HANDLE(device);
235 union acpi_object *obj;
237 if (dmi_check_system(i2c_dw_no_acpi_params))
240 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
243 obj = (union acpi_object *)buf.pointer;
244 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
245 const union acpi_object *objs = obj->package.elements;
247 *hcnt = (u16)objs[0].integer.value;
248 *lcnt = (u16)objs[1].integer.value;
249 *sda_hold = (u32)objs[2].integer.value;
255 int i2c_dw_acpi_configure(struct device *device)
257 struct dw_i2c_dev *dev = dev_get_drvdata(device);
258 struct i2c_timings *t = &dev->timings;
259 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
262 * Try to get SDA hold time and *CNT values from an ACPI method for
263 * selected speed modes.
265 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
266 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
267 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
268 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
270 switch (t->bus_freq_hz) {
271 case I2C_MAX_STANDARD_MODE_FREQ:
272 dev->sda_hold_time = ss_ht;
274 case I2C_MAX_FAST_MODE_PLUS_FREQ:
275 dev->sda_hold_time = fp_ht;
277 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
278 dev->sda_hold_time = hs_ht;
280 case I2C_MAX_FAST_MODE_FREQ:
282 dev->sda_hold_time = fs_ht;
288 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
290 static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
295 acpi_speed = i2c_acpi_find_bus_speed(device);
297 * Some DSTDs use a non standard speed, round down to the lowest
300 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
301 if (acpi_speed >= supported_speeds[i])
302 return supported_speeds[i];
308 #else /* CONFIG_ACPI */
310 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
312 #endif /* CONFIG_ACPI */
314 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
316 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
317 struct i2c_timings *t = &dev->timings;
320 * Find bus speed from the "clock-frequency" device property, ACPI
321 * or by using fast mode if neither is set.
323 if (acpi_speed && t->bus_freq_hz)
324 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
325 else if (acpi_speed || t->bus_freq_hz)
326 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
328 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
330 EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
332 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
335 * DesignWare I2C core doesn't seem to have solid strategy to meet
336 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
337 * will result in violation of the tHD;STA spec.
341 * Conditional expression:
343 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
345 * This is based on the DW manuals, and represents an ideal
346 * configuration. The resulting I2C bus speed will be
347 * faster than any of the others.
349 * If your hardware is free from tHD;STA issue, try this one.
351 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) -
355 * Conditional expression:
357 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
359 * This is just experimental rule; the tHD;STA period turned
360 * out to be proportinal to (_HCNT + 3). With this setting,
361 * we could meet both tHIGH and tHD;STA timing specs.
363 * If unsure, you'd better to take this alternative.
365 * The reason why we need to take into account "tf" here,
366 * is the same as described in i2c_dw_scl_lcnt().
368 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) -
372 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
375 * Conditional expression:
377 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
379 * DW I2C core starts counting the SCL CNTs for the LOW period
380 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
381 * In order to meet the tLOW timing spec, we need to take into
382 * account the fall time of SCL signal (tf). Default tf value
383 * should be 0.3 us, for safety.
385 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) -
389 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
394 ret = i2c_dw_acquire_lock(dev);
398 /* Configure SDA Hold Time if required */
399 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
401 goto err_release_lock;
403 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
404 if (!dev->sda_hold_time) {
405 /* Keep previous hold time setting if no one set it */
406 ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
407 &dev->sda_hold_time);
409 goto err_release_lock;
413 * Workaround for avoiding TX arbitration lost in case I2C
414 * slave pulls SDA down "too quickly" after falling edge of
415 * SCL by enabling non-zero SDA RX hold. Specification says it
416 * extends incoming SDA low to high transition while SCL is
417 * high but it appears to help also above issue.
419 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
420 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
422 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
423 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
424 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
425 } else if (dev->set_sda_hold_time) {
426 dev->set_sda_hold_time(dev);
427 } else if (dev->sda_hold_time) {
429 "Hardware too old to adjust SDA hold time.\n");
430 dev->sda_hold_time = 0;
434 i2c_dw_release_lock(dev);
439 void __i2c_dw_disable(struct dw_i2c_dev *dev)
445 __i2c_dw_disable_nowait(dev);
447 * The enable status register may be unimplemented, but
448 * in that case this test reads zero and exits the loop.
450 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
451 if ((status & 1) == 0)
455 * Wait 10 times the signaling period of the highest I2C
456 * transfer supported by the driver (for 400KHz this is
457 * 25us) as described in the DesignWare I2C databook.
459 usleep_range(25, 250);
462 dev_warn(dev->dev, "timeout in disabling adapter\n");
465 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
468 * Clock is not necessary if we got LCNT/HCNT values directly from
471 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
473 return dev->get_clk_rate_khz(dev);
476 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
481 /* Optional interface clock */
482 ret = clk_prepare_enable(dev->pclk);
486 ret = clk_prepare_enable(dev->clk);
488 clk_disable_unprepare(dev->pclk);
493 clk_disable_unprepare(dev->clk);
494 clk_disable_unprepare(dev->pclk);
498 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
500 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
504 if (!dev->acquire_lock)
507 ret = dev->acquire_lock();
511 dev_err(dev->dev, "couldn't acquire bus ownership\n");
516 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
518 if (dev->release_lock)
523 * Waiting for bus not busy
525 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
530 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
531 !(status & DW_IC_STATUS_ACTIVITY),
534 dev_warn(dev->dev, "timeout waiting for bus ready\n");
536 i2c_recover_bus(&dev->adapter);
538 regmap_read(dev->map, DW_IC_STATUS, &status);
539 if (!(status & DW_IC_STATUS_ACTIVITY))
546 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
548 unsigned long abort_source = dev->abort_source;
551 if (abort_source & DW_IC_TX_ABRT_NOACK) {
552 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
554 "%s: %s\n", __func__, abort_sources[i]);
558 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
559 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
561 if (abort_source & DW_IC_TX_ARB_LOST)
563 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
564 return -EINVAL; /* wrong msgs[] data */
569 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
571 u32 param, tx_fifo_depth, rx_fifo_depth;
575 * Try to detect the FIFO depth if not set by interface driver,
576 * the depth could be from 2 to 256 from HW spec.
578 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
582 tx_fifo_depth = ((param >> 16) & 0xff) + 1;
583 rx_fifo_depth = ((param >> 8) & 0xff) + 1;
584 if (!dev->tx_fifo_depth) {
585 dev->tx_fifo_depth = tx_fifo_depth;
586 dev->rx_fifo_depth = rx_fifo_depth;
587 } else if (tx_fifo_depth >= 2) {
588 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
590 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
597 u32 i2c_dw_func(struct i2c_adapter *adap)
599 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
601 return dev->functionality;
604 void i2c_dw_disable(struct dw_i2c_dev *dev)
608 /* Disable controller */
609 __i2c_dw_disable(dev);
611 /* Disable all interrupts */
612 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
613 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
616 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
618 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
621 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
622 MODULE_LICENSE("GPL");