2 * TI DAVINCI I2C adapter driver.
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
7 * Updated by Vinod & Sudhakar Feb 2005
9 * ----------------------------------------------------------------------------
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 * ----------------------------------------------------------------------------
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/clk.h>
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/err.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/cpufreq.h>
36 #include <linux/gpio.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_data/i2c-davinci.h>
40 /* ----- global defines ----------------------------------------------- */
42 #define DAVINCI_I2C_TIMEOUT (1*HZ)
43 #define DAVINCI_I2C_MAX_TRIES 2
44 #define DAVINCI_I2C_OWN_ADDRESS 0x08
45 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \
50 #define DAVINCI_I2C_OAR_REG 0x00
51 #define DAVINCI_I2C_IMR_REG 0x04
52 #define DAVINCI_I2C_STR_REG 0x08
53 #define DAVINCI_I2C_CLKL_REG 0x0c
54 #define DAVINCI_I2C_CLKH_REG 0x10
55 #define DAVINCI_I2C_CNT_REG 0x14
56 #define DAVINCI_I2C_DRR_REG 0x18
57 #define DAVINCI_I2C_SAR_REG 0x1c
58 #define DAVINCI_I2C_DXR_REG 0x20
59 #define DAVINCI_I2C_MDR_REG 0x24
60 #define DAVINCI_I2C_IVR_REG 0x28
61 #define DAVINCI_I2C_EMDR_REG 0x2c
62 #define DAVINCI_I2C_PSC_REG 0x30
63 #define DAVINCI_I2C_FUNC_REG 0x48
64 #define DAVINCI_I2C_DIR_REG 0x4c
65 #define DAVINCI_I2C_DIN_REG 0x50
66 #define DAVINCI_I2C_DOUT_REG 0x54
67 #define DAVINCI_I2C_DSET_REG 0x58
68 #define DAVINCI_I2C_DCLR_REG 0x5c
70 #define DAVINCI_I2C_IVR_AAS 0x07
71 #define DAVINCI_I2C_IVR_SCD 0x06
72 #define DAVINCI_I2C_IVR_XRDY 0x05
73 #define DAVINCI_I2C_IVR_RDR 0x04
74 #define DAVINCI_I2C_IVR_ARDY 0x03
75 #define DAVINCI_I2C_IVR_NACK 0x02
76 #define DAVINCI_I2C_IVR_AL 0x01
78 #define DAVINCI_I2C_STR_BB BIT(12)
79 #define DAVINCI_I2C_STR_RSFULL BIT(11)
80 #define DAVINCI_I2C_STR_SCD BIT(5)
81 #define DAVINCI_I2C_STR_ARDY BIT(2)
82 #define DAVINCI_I2C_STR_NACK BIT(1)
83 #define DAVINCI_I2C_STR_AL BIT(0)
85 #define DAVINCI_I2C_MDR_NACK BIT(15)
86 #define DAVINCI_I2C_MDR_STT BIT(13)
87 #define DAVINCI_I2C_MDR_STP BIT(11)
88 #define DAVINCI_I2C_MDR_MST BIT(10)
89 #define DAVINCI_I2C_MDR_TRX BIT(9)
90 #define DAVINCI_I2C_MDR_XA BIT(8)
91 #define DAVINCI_I2C_MDR_RM BIT(7)
92 #define DAVINCI_I2C_MDR_IRS BIT(5)
94 #define DAVINCI_I2C_IMR_AAS BIT(6)
95 #define DAVINCI_I2C_IMR_SCD BIT(5)
96 #define DAVINCI_I2C_IMR_XRDY BIT(4)
97 #define DAVINCI_I2C_IMR_RRDY BIT(3)
98 #define DAVINCI_I2C_IMR_ARDY BIT(2)
99 #define DAVINCI_I2C_IMR_NACK BIT(1)
100 #define DAVINCI_I2C_IMR_AL BIT(0)
102 /* set SDA and SCL as GPIO */
103 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
105 /* set SCL as output when used as GPIO*/
106 #define DAVINCI_I2C_DIR_PDIR0 BIT(0)
107 /* set SDA as output when used as GPIO*/
108 #define DAVINCI_I2C_DIR_PDIR1 BIT(1)
110 /* read SCL GPIO level */
111 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
112 /* read SDA GPIO level */
113 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
115 /*set the SCL GPIO high */
116 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
117 /*set the SDA GPIO high */
118 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
120 /* set the SCL GPIO low */
121 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
122 /* set the SDA GPIO low */
123 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
125 struct davinci_i2c_dev {
128 struct completion cmd_complete;
136 struct i2c_adapter adapter;
137 #ifdef CONFIG_CPU_FREQ
138 struct completion xfr_complete;
139 struct notifier_block freq_transition;
141 struct davinci_i2c_platform_data *pdata;
144 /* default platform data to use if not supplied in the platform_device */
145 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
150 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
153 writew_relaxed(val, i2c_dev->base + reg);
156 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
158 return readw_relaxed(i2c_dev->base + reg);
161 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
166 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
167 if (!val) /* put I2C into reset */
168 w &= ~DAVINCI_I2C_MDR_IRS;
169 else /* take I2C out of reset */
170 w |= DAVINCI_I2C_MDR_IRS;
172 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
175 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
177 struct davinci_i2c_platform_data *pdata = dev->pdata;
183 u32 input_clock = clk_get_rate(dev->clk);
184 struct device_node *of_node = dev->dev->of_node;
186 /* NOTE: I2C Clock divider programming info
187 * As per I2C specs the following formulas provide prescaler
188 * and low/high divider values
189 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
192 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
195 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
197 * where if PSC == 0, d = 7,
202 * d is always 6 on Keystone I2C controller
206 * Both Davinci and current Keystone User Guides recommend a value
207 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
208 * always produce enough margin between SDA and SCL transitions.
209 * Measurements show that the higher the module clock is, the
210 * bigger is the margin, providing more reliable communication.
211 * So we better target for 12MHz.
213 psc = (input_clock / 12000000) - 1;
214 if ((input_clock / (psc + 1)) > 12000000)
215 psc++; /* better to run under spec than over */
216 d = (psc >= 2) ? 5 : 7 - psc;
218 if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
221 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
222 /* Avoid driving the bus too fast because of rounding errors above */
223 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
226 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
227 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
228 * to LOW ratio as 1 to 2 is more safe.
230 if (pdata->bus_freq > 100)
231 clkl = (clk << 1) / 3;
235 * It's not always possible to have 1 to 2 ratio when d=7, so fall back
236 * to minimal possible clkh in this case.
239 * CLKH is not allowed to be 0, in this case I2C clock is not generated
242 if (clk > clkl + d) {
243 clkh = clk - clkl - d;
247 clkl = clk - (d << 1);
250 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
251 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
252 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
254 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
258 * This function configures I2C and brings I2C out of reset.
259 * This function is called during I2C init function. This function
260 * also gets called if I2C encounters any errors.
262 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
264 struct davinci_i2c_platform_data *pdata = dev->pdata;
266 /* put I2C into reset */
267 davinci_i2c_reset_ctrl(dev, 0);
269 /* compute clock dividers */
270 i2c_davinci_calc_clk_dividers(dev);
272 /* Respond at reserved "SMBus Host" slave address" (and zero);
273 * we seem to have no option to not respond...
275 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
277 dev_dbg(dev->dev, "PSC = %d\n",
278 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
279 dev_dbg(dev->dev, "CLKL = %d\n",
280 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
281 dev_dbg(dev->dev, "CLKH = %d\n",
282 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
283 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
284 pdata->bus_freq, pdata->bus_delay);
287 /* Take the I2C module out of reset: */
288 davinci_i2c_reset_ctrl(dev, 1);
290 /* Enable interrupts */
291 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
297 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
298 * which is provided by I2C Bus recovery infrastructure.
300 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
302 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
304 /* Disable interrupts */
305 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
307 /* put I2C into reset */
308 davinci_i2c_reset_ctrl(dev, 0);
311 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
313 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
315 i2c_davinci_init(dev);
318 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
319 .recover_bus = i2c_generic_gpio_recovery,
320 .prepare_recovery = davinci_i2c_prepare_recovery,
321 .unprepare_recovery = davinci_i2c_unprepare_recovery,
324 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
326 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
329 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
330 DAVINCI_I2C_DSET_PDSET0);
332 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
333 DAVINCI_I2C_DCLR_PDCLR0);
336 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
338 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
341 /* read the state of SCL */
342 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
343 return val & DAVINCI_I2C_DIN_PDIN0;
346 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
348 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
351 /* read the state of SDA */
352 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
353 return val & DAVINCI_I2C_DIN_PDIN1;
356 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
358 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
360 davinci_i2c_prepare_recovery(adap);
362 /* SCL output, SDA input */
363 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
365 /* change to GPIO mode */
366 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
367 DAVINCI_I2C_FUNC_PFUNC0);
370 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
372 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
374 /* change back to I2C mode */
375 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
377 davinci_i2c_unprepare_recovery(adap);
380 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
381 .recover_bus = i2c_generic_scl_recovery,
382 .set_scl = davinci_i2c_set_scl,
383 .get_scl = davinci_i2c_get_scl,
384 .get_sda = davinci_i2c_get_sda,
385 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
386 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
390 * Waiting for bus not busy
392 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
394 unsigned long timeout = jiffies + dev->adapter.timeout;
397 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
399 schedule_timeout_uninterruptible(1);
400 } while (time_before_eq(jiffies, timeout));
402 dev_warn(dev->dev, "timeout waiting for bus ready\n");
403 i2c_recover_bus(&dev->adapter);
406 * if bus is still "busy" here, it's most probably a HW problem like
409 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
416 * Low level master read/write transaction. This function is called
417 * from i2c_davinci_xfer.
420 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
422 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
423 struct davinci_i2c_platform_data *pdata = dev->pdata;
426 unsigned long time_left;
428 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
429 dev_warn(dev->dev, "transfer to own address aborted\n");
430 return -EADDRNOTAVAIL;
433 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
434 if (pdata->bus_delay)
435 udelay(pdata->bus_delay);
437 /* set the slave address */
438 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
441 dev->buf_len = msg->len;
444 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
446 reinit_completion(&dev->cmd_complete);
449 /* Take I2C out of reset and configure it as master */
450 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
452 /* if the slave address is ten bit address, enable XA bit */
453 if (msg->flags & I2C_M_TEN)
454 flag |= DAVINCI_I2C_MDR_XA;
455 if (!(msg->flags & I2C_M_RD))
456 flag |= DAVINCI_I2C_MDR_TRX;
458 flag |= DAVINCI_I2C_MDR_RM;
460 /* Enable receive or transmit interrupts */
461 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
462 if (msg->flags & I2C_M_RD)
463 w |= DAVINCI_I2C_IMR_RRDY;
465 w |= DAVINCI_I2C_IMR_XRDY;
466 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
471 * Write mode register first as needed for correct behaviour
472 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
473 * occurring before we have loaded DXR
475 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
478 * First byte should be set here, not after interrupt,
479 * because transmit-data-ready interrupt can come before
480 * NACK-interrupt during sending of previous message and
481 * ICDXR may have wrong data
482 * It also saves us one interrupt, slightly faster
484 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
485 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
489 /* Set STT to begin transmit now DXR is loaded */
490 flag |= DAVINCI_I2C_MDR_STT;
491 if (stop && msg->len != 0)
492 flag |= DAVINCI_I2C_MDR_STP;
493 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
495 time_left = wait_for_completion_timeout(&dev->cmd_complete,
496 dev->adapter.timeout);
498 dev_err(dev->dev, "controller timed out\n");
499 i2c_recover_bus(adap);
504 /* This should be 0 if all bytes were transferred
505 * or dev->cmd_err denotes an error.
507 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
516 if (likely(!dev->cmd_err))
519 /* We have an error */
520 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
521 i2c_davinci_init(dev);
525 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
526 if (msg->flags & I2C_M_IGNORE_NAK)
528 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
529 w |= DAVINCI_I2C_MDR_STP;
530 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
537 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
540 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
542 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
546 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
548 ret = i2c_davinci_wait_bus_not_busy(dev);
550 dev_warn(dev->dev, "timeout waiting for bus ready\n");
554 for (i = 0; i < num; i++) {
555 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
556 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
562 #ifdef CONFIG_CPU_FREQ
563 complete(&dev->xfr_complete);
569 static u32 i2c_davinci_func(struct i2c_adapter *adap)
571 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
574 static void terminate_read(struct davinci_i2c_dev *dev)
576 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
577 w |= DAVINCI_I2C_MDR_NACK;
578 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
580 /* Throw away data */
581 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
583 dev_err(dev->dev, "RDR IRQ while no data requested\n");
585 static void terminate_write(struct davinci_i2c_dev *dev)
587 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
588 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
589 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
592 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
596 * Interrupt service routine. This gets called whenever an I2C interrupt
599 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
601 struct davinci_i2c_dev *dev = dev_id;
606 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
607 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
608 if (count++ == 100) {
609 dev_warn(dev->dev, "Too much work in one IRQ\n");
614 case DAVINCI_I2C_IVR_AL:
615 /* Arbitration lost, must retry */
616 dev->cmd_err |= DAVINCI_I2C_STR_AL;
618 complete(&dev->cmd_complete);
621 case DAVINCI_I2C_IVR_NACK:
622 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
624 complete(&dev->cmd_complete);
627 case DAVINCI_I2C_IVR_ARDY:
628 davinci_i2c_write_reg(dev,
629 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
630 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
631 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
632 w = davinci_i2c_read_reg(dev,
633 DAVINCI_I2C_MDR_REG);
634 w |= DAVINCI_I2C_MDR_STP;
635 davinci_i2c_write_reg(dev,
636 DAVINCI_I2C_MDR_REG, w);
638 complete(&dev->cmd_complete);
641 case DAVINCI_I2C_IVR_RDR:
644 davinci_i2c_read_reg(dev,
645 DAVINCI_I2C_DRR_REG);
650 davinci_i2c_write_reg(dev,
652 DAVINCI_I2C_IMR_RRDY);
654 /* signal can terminate transfer */
659 case DAVINCI_I2C_IVR_XRDY:
661 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
667 w = davinci_i2c_read_reg(dev,
668 DAVINCI_I2C_IMR_REG);
669 w &= ~DAVINCI_I2C_IMR_XRDY;
670 davinci_i2c_write_reg(dev,
674 /* signal can terminate transfer */
675 terminate_write(dev);
679 case DAVINCI_I2C_IVR_SCD:
680 davinci_i2c_write_reg(dev,
681 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
682 complete(&dev->cmd_complete);
685 case DAVINCI_I2C_IVR_AAS:
686 dev_dbg(dev->dev, "Address as slave interrupt\n");
690 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
695 return count ? IRQ_HANDLED : IRQ_NONE;
698 #ifdef CONFIG_CPU_FREQ
699 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
700 unsigned long val, void *data)
702 struct davinci_i2c_dev *dev;
704 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
705 if (val == CPUFREQ_PRECHANGE) {
706 wait_for_completion(&dev->xfr_complete);
707 davinci_i2c_reset_ctrl(dev, 0);
708 } else if (val == CPUFREQ_POSTCHANGE) {
709 i2c_davinci_calc_clk_dividers(dev);
710 davinci_i2c_reset_ctrl(dev, 1);
716 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
718 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
720 return cpufreq_register_notifier(&dev->freq_transition,
721 CPUFREQ_TRANSITION_NOTIFIER);
724 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
726 cpufreq_unregister_notifier(&dev->freq_transition,
727 CPUFREQ_TRANSITION_NOTIFIER);
730 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
735 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
740 static struct i2c_algorithm i2c_davinci_algo = {
741 .master_xfer = i2c_davinci_xfer,
742 .functionality = i2c_davinci_func,
745 static const struct of_device_id davinci_i2c_of_match[] = {
746 {.compatible = "ti,davinci-i2c", },
747 {.compatible = "ti,keystone-i2c", },
750 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
752 static int davinci_i2c_probe(struct platform_device *pdev)
754 struct davinci_i2c_dev *dev;
755 struct i2c_adapter *adap;
756 struct resource *mem;
759 irq = platform_get_irq(pdev, 0);
763 if (irq != -EPROBE_DEFER)
765 "can't get irq resource ret=%d\n", irq);
769 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
772 dev_err(&pdev->dev, "Memory allocation failed\n");
776 init_completion(&dev->cmd_complete);
777 #ifdef CONFIG_CPU_FREQ
778 init_completion(&dev->xfr_complete);
780 dev->dev = &pdev->dev;
782 dev->pdata = dev_get_platdata(&pdev->dev);
783 platform_set_drvdata(pdev, dev);
785 if (!dev->pdata && pdev->dev.of_node) {
788 dev->pdata = devm_kzalloc(&pdev->dev,
789 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
793 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
794 sizeof(struct davinci_i2c_platform_data));
795 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
797 dev->pdata->bus_freq = prop / 1000;
799 dev->pdata->has_pfunc =
800 of_property_read_bool(pdev->dev.of_node,
802 } else if (!dev->pdata) {
803 dev->pdata = &davinci_i2c_platform_data_default;
806 dev->clk = devm_clk_get(&pdev->dev, NULL);
807 if (IS_ERR(dev->clk))
809 clk_prepare_enable(dev->clk);
811 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
812 dev->base = devm_ioremap_resource(&pdev->dev, mem);
813 if (IS_ERR(dev->base)) {
814 r = PTR_ERR(dev->base);
815 goto err_unuse_clocks;
818 i2c_davinci_init(dev);
820 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
823 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
824 goto err_unuse_clocks;
827 r = i2c_davinci_cpufreq_register(dev);
829 dev_err(&pdev->dev, "failed to register cpufreq\n");
830 goto err_unuse_clocks;
833 adap = &dev->adapter;
834 i2c_set_adapdata(adap, dev);
835 adap->owner = THIS_MODULE;
836 adap->class = I2C_CLASS_DEPRECATED;
837 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
838 adap->algo = &i2c_davinci_algo;
839 adap->dev.parent = &pdev->dev;
840 adap->timeout = DAVINCI_I2C_TIMEOUT;
841 adap->dev.of_node = pdev->dev.of_node;
843 if (dev->pdata->has_pfunc)
844 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
845 else if (dev->pdata->scl_pin) {
846 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
847 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
848 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
852 r = i2c_add_numbered_adapter(adap);
854 goto err_unuse_clocks;
859 clk_disable_unprepare(dev->clk);
864 static int davinci_i2c_remove(struct platform_device *pdev)
866 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
868 i2c_davinci_cpufreq_deregister(dev);
870 i2c_del_adapter(&dev->adapter);
872 clk_disable_unprepare(dev->clk);
875 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
881 static int davinci_i2c_suspend(struct device *dev)
883 struct platform_device *pdev = to_platform_device(dev);
884 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
886 /* put I2C into reset */
887 davinci_i2c_reset_ctrl(i2c_dev, 0);
888 clk_disable_unprepare(i2c_dev->clk);
893 static int davinci_i2c_resume(struct device *dev)
895 struct platform_device *pdev = to_platform_device(dev);
896 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
898 clk_prepare_enable(i2c_dev->clk);
899 /* take I2C out of reset */
900 davinci_i2c_reset_ctrl(i2c_dev, 1);
905 static const struct dev_pm_ops davinci_i2c_pm = {
906 .suspend = davinci_i2c_suspend,
907 .resume = davinci_i2c_resume,
910 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
912 #define davinci_i2c_pm_ops NULL
915 /* work with hotplug and coldplug */
916 MODULE_ALIAS("platform:i2c_davinci");
918 static struct platform_driver davinci_i2c_driver = {
919 .probe = davinci_i2c_probe,
920 .remove = davinci_i2c_remove,
922 .name = "i2c_davinci",
923 .pm = davinci_i2c_pm_ops,
924 .of_match_table = davinci_i2c_of_match,
928 /* I2C may be needed to bring up other drivers */
929 static int __init davinci_i2c_init_driver(void)
931 return platform_driver_register(&davinci_i2c_driver);
933 subsys_initcall(davinci_i2c_init_driver);
935 static void __exit davinci_i2c_exit_driver(void)
937 platform_driver_unregister(&davinci_i2c_driver);
939 module_exit(davinci_i2c_exit_driver);
941 MODULE_AUTHOR("Texas Instruments India");
942 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
943 MODULE_LICENSE("GPL");