2 * Freescale CPM1/CPM2 I2C interface.
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
5 * moved into proper i2c interface;
6 * Brad Parker (brad@heeltoe.com)
8 * Parts from dbox2_i2c.c (cvs.tuxbox.org)
9 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
11 * (C) 2007 Montavista Software, Inc.
12 * Vitaly Bordug <vitb@kernel.crashing.org>
14 * Converted to of_platform_device. Renamed to i2c-cpm.c.
15 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/errno.h>
34 #include <linux/stddef.h>
35 #include <linux/i2c.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/of_address.h>
39 #include <linux/of_device.h>
40 #include <linux/of_irq.h>
41 #include <linux/of_platform.h>
42 #include <sysdev/fsl_soc.h>
45 /* Try to define this if you have an older CPU (earlier than rev D4) */
46 /* However, better use a GPIO based bitbang driver in this case :/ */
47 #undef I2C_CHIP_ERRATA
49 #define CPM_MAX_READ 513
52 #define I2C_EB (0x10) /* Big endian mode */
53 #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */
55 #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0))
57 /* I2C parameter RAM. */
59 ushort rbase; /* Rx Buffer descriptor base address */
60 ushort tbase; /* Tx Buffer descriptor base address */
61 u_char rfcr; /* Rx function code */
62 u_char tfcr; /* Tx function code */
63 ushort mrblr; /* Max receive buffer length */
64 uint rstate; /* Internal */
65 uint rdp; /* Internal */
66 ushort rbptr; /* Rx Buffer descriptor pointer */
67 ushort rbc; /* Internal */
68 uint rxtmp; /* Internal */
69 uint tstate; /* Internal */
70 uint tdp; /* Internal */
71 ushort tbptr; /* Tx Buffer descriptor pointer */
72 ushort tbc; /* Internal */
73 uint txtmp; /* Internal */
74 char res1[4]; /* Reserved */
75 ushort rpbase; /* Relocation pointer */
76 char res2[2]; /* Reserved */
77 /* The following elements are only for CPM2 */
78 char res3[4]; /* Reserved */
79 uint sdmatmp; /* Internal */
82 #define I2COM_START 0x80
83 #define I2COM_MASTER 0x01
84 #define I2CER_TXE 0x10
85 #define I2CER_BUSY 0x04
86 #define I2CER_TXB 0x02
87 #define I2CER_RXB 0x01
107 struct platform_device *ofdev;
108 struct i2c_adapter adap;
110 int version; /* CPM1=1, CPM2=2 */
114 struct i2c_reg __iomem *i2c_reg;
115 struct i2c_ram __iomem *i2c_ram;
117 wait_queue_head_t i2c_wait;
118 cbd_t __iomem *tbase;
119 cbd_t __iomem *rbase;
120 u_char *txbuf[CPM_MAXBD];
121 u_char *rxbuf[CPM_MAXBD];
122 dma_addr_t txdma[CPM_MAXBD];
123 dma_addr_t rxdma[CPM_MAXBD];
126 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
129 struct i2c_reg __iomem *i2c_reg;
130 struct i2c_adapter *adap = dev_id;
133 cpm = i2c_get_adapdata(dev_id);
134 i2c_reg = cpm->i2c_reg;
136 /* Clear interrupt. */
137 i = in_8(&i2c_reg->i2cer);
138 out_8(&i2c_reg->i2cer, i);
140 dev_dbg(&adap->dev, "Interrupt: %x\n", i);
142 wake_up(&cpm->i2c_wait);
144 return i ? IRQ_HANDLED : IRQ_NONE;
147 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
149 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
151 /* Set up the I2C parameters in the parameter ram. */
152 out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
153 out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
155 if (cpm->version == 1) {
156 out_8(&i2c_ram->tfcr, I2C_EB);
157 out_8(&i2c_ram->rfcr, I2C_EB);
159 out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
160 out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
163 out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
165 out_be32(&i2c_ram->rstate, 0);
166 out_be32(&i2c_ram->rdp, 0);
167 out_be16(&i2c_ram->rbptr, 0);
168 out_be16(&i2c_ram->rbc, 0);
169 out_be32(&i2c_ram->rxtmp, 0);
170 out_be32(&i2c_ram->tstate, 0);
171 out_be32(&i2c_ram->tdp, 0);
172 out_be16(&i2c_ram->tbptr, 0);
173 out_be16(&i2c_ram->tbc, 0);
174 out_be32(&i2c_ram->txtmp, 0);
177 static void cpm_i2c_force_close(struct i2c_adapter *adap)
179 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
180 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
182 dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
184 cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
186 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */
187 out_8(&i2c_reg->i2cer, 0xff);
190 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
191 struct i2c_msg *pmsg, int num, int tx, int rx)
198 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
200 tbdf = cpm->tbase + tx;
201 rbdf = cpm->rbase + rx;
203 addr = i2c_8bit_addr_from_msg(pmsg);
208 /* Align read buffer */
209 rb = (u_char *) (((ulong) rb + 1) & ~1);
211 tb[0] = addr; /* Device address byte w/rw flag */
213 out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
214 out_be16(&tbdf->cbd_sc, 0);
216 if (!(pmsg->flags & I2C_M_NOSTART))
217 setbits16(&tbdf->cbd_sc, BD_I2C_START);
220 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
222 if (pmsg->flags & I2C_M_RD) {
224 * To read, we need an empty buffer of the proper length.
225 * All that is used is the first byte for address, the remainder
226 * is just used for timing (and doesn't really have to exist).
229 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
231 out_be16(&rbdf->cbd_datlen, 0);
232 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
234 if (rx + 1 == CPM_MAXBD)
235 setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
238 setbits16(&tbdf->cbd_sc, BD_SC_READY);
240 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
242 memcpy(tb+1, pmsg->buf, pmsg->len);
245 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
249 static int cpm_i2c_check_message(struct i2c_adapter *adap,
250 struct i2c_msg *pmsg, int tx, int rx)
256 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
258 tbdf = cpm->tbase + tx;
259 rbdf = cpm->rbase + rx;
264 /* Align read buffer */
265 rb = (u_char *) (((uint) rb + 1) & ~1);
268 if (pmsg->flags & I2C_M_RD) {
269 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
270 in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
272 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
273 dev_dbg(&adap->dev, "I2C read; No ack\n");
276 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
278 "I2C read; complete but rbuf empty\n");
281 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
282 dev_err(&adap->dev, "I2C read; Overrun\n");
285 memcpy(pmsg->buf, rb, pmsg->len);
287 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
288 in_be16(&tbdf->cbd_sc));
290 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
291 dev_dbg(&adap->dev, "I2C write; No ack\n");
294 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
295 dev_err(&adap->dev, "I2C write; Underrun\n");
298 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
299 dev_err(&adap->dev, "I2C write; Collision\n");
306 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
308 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
309 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
310 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
311 struct i2c_msg *pmsg;
318 /* Reset to use first buffer */
319 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
320 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
329 * If there was a collision in the last i2c transaction,
330 * Set I2COM_MASTER as it was cleared during collision.
332 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
333 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
338 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
340 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
341 if (pmsg->flags & I2C_M_RD)
345 /* Start transfer now */
346 /* Enable RX/TX/Error interupts */
347 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
348 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */
349 /* Chip bug, set enable here */
350 setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */
351 /* Begin transmission */
352 setbits8(&i2c_reg->i2com, I2COM_START);
358 /* Check for outstanding messages */
359 dev_dbg(&adap->dev, "test ready.\n");
361 if (pmsg->flags & I2C_M_RD)
362 ret = wait_event_timeout(cpm->i2c_wait,
363 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
364 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
367 ret = wait_event_timeout(cpm->i2c_wait,
368 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
372 dev_err(&adap->dev, "I2C transfer: timeout\n");
376 dev_dbg(&adap->dev, "ready.\n");
377 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
379 if (pmsg->flags & I2C_M_RD)
385 #ifdef I2C_CHIP_ERRATA
387 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
388 * Disabling I2C too early may cause too short stop condition
391 clrbits8(&i2c_reg->i2mod, I2MOD_EN);
396 cpm_i2c_force_close(adap);
397 #ifdef I2C_CHIP_ERRATA
399 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
401 clrbits8(&i2c_reg->i2mod, I2MOD_EN);
406 static u32 cpm_i2c_func(struct i2c_adapter *adap)
408 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
411 /* -----exported algorithm data: ------------------------------------- */
413 static const struct i2c_algorithm cpm_i2c_algo = {
414 .master_xfer = cpm_i2c_xfer,
415 .functionality = cpm_i2c_func,
418 /* CPM_MAX_READ is also limiting writes according to the code! */
419 static const struct i2c_adapter_quirks cpm_i2c_quirks = {
420 .max_num_msgs = CPM_MAXBD,
421 .max_read_len = CPM_MAX_READ,
422 .max_write_len = CPM_MAX_READ,
425 static const struct i2c_adapter cpm_ops = {
426 .owner = THIS_MODULE,
428 .algo = &cpm_i2c_algo,
429 .quirks = &cpm_i2c_quirks,
432 static int cpm_i2c_setup(struct cpm_i2c *cpm)
434 struct platform_device *ofdev = cpm->ofdev;
437 void __iomem *i2c_base;
442 dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
444 init_waitqueue_head(&cpm->i2c_wait);
446 cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
450 /* Install interrupt handler. */
451 ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
456 /* I2C parameter RAM */
457 i2c_base = of_iomap(ofdev->dev.of_node, 1);
458 if (i2c_base == NULL) {
463 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
465 /* Check for and use a microcode relocation patch. */
466 cpm->i2c_ram = i2c_base;
467 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
470 * Maybe should use cpm_muram_alloc instead of hardcoding
471 * this in micropatch.c
474 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
480 } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
481 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
482 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
483 out_be16(i2c_base, cpm->i2c_addr);
494 /* I2C control/status registers */
495 cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
496 if (cpm->i2c_reg == NULL) {
501 data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
502 if (!data || len != 4) {
506 cpm->cp_command = *data;
508 data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
509 if (data && len == 4)
510 cpm->adap.class = *data;
512 data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
513 if (data && len == 4)
516 cpm->freq = 60000; /* use 60kHz i2c clock by default */
519 * Allocate space for CPM_MAXBD transmit and receive buffer
520 * descriptors in the DP ram.
522 cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
528 cpm->tbase = cpm_muram_addr(cpm->dp_addr);
529 cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
531 /* Allocate TX and RX buffers */
536 for (i = 0; i < CPM_MAXBD; i++) {
537 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
539 &cpm->rxdma[i], GFP_KERNEL);
540 if (!cpm->rxbuf[i]) {
544 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
546 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
547 if (!cpm->txbuf[i]) {
551 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
554 /* Initialize Tx/Rx parameters. */
556 cpm_reset_i2c_params(cpm);
558 dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
559 cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
560 dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
561 (u8 __iomem *)cpm->tbase - DPRAM_BASE,
562 (u8 __iomem *)cpm->rbase - DPRAM_BASE);
564 cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
567 * Select an invalid address. Just make sure we don't use loopback mode
569 out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
572 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
573 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
574 * the actual i2c bus frequency.
576 brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
577 out_8(&cpm->i2c_reg->i2brg, brg);
579 out_8(&cpm->i2c_reg->i2mod, 0x00);
580 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */
582 /* Disable interrupts. */
583 out_8(&cpm->i2c_reg->i2cmr, 0);
584 out_8(&cpm->i2c_reg->i2cer, 0xff);
589 for (i = 0; i < CPM_MAXBD; i++) {
591 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
592 cpm->rxbuf[i], cpm->rxdma[i]);
594 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
595 cpm->txbuf[i], cpm->txdma[i]);
597 cpm_muram_free(cpm->dp_addr);
599 iounmap(cpm->i2c_reg);
601 if ((cpm->version == 1) && (!cpm->i2c_addr))
602 iounmap(cpm->i2c_ram);
603 if (cpm->version == 2)
604 cpm_muram_free(cpm->i2c_addr);
606 free_irq(cpm->irq, &cpm->adap);
610 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
615 clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
617 /* Disable interrupts */
618 out_8(&cpm->i2c_reg->i2cmr, 0);
619 out_8(&cpm->i2c_reg->i2cer, 0xff);
621 free_irq(cpm->irq, &cpm->adap);
623 /* Free all memory */
624 for (i = 0; i < CPM_MAXBD; i++) {
625 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
626 cpm->rxbuf[i], cpm->rxdma[i]);
627 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
628 cpm->txbuf[i], cpm->txdma[i]);
631 cpm_muram_free(cpm->dp_addr);
632 iounmap(cpm->i2c_reg);
634 if ((cpm->version == 1) && (!cpm->i2c_addr))
635 iounmap(cpm->i2c_ram);
636 if (cpm->version == 2)
637 cpm_muram_free(cpm->i2c_addr);
640 static int cpm_i2c_probe(struct platform_device *ofdev)
646 cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
652 platform_set_drvdata(ofdev, cpm);
655 i2c_set_adapdata(&cpm->adap, cpm);
656 cpm->adap.dev.parent = &ofdev->dev;
657 cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
659 result = cpm_i2c_setup(cpm);
661 dev_err(&ofdev->dev, "Unable to init hardware\n");
665 /* register new adapter to i2c module... */
667 data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
668 cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
669 result = i2c_add_numbered_adapter(&cpm->adap);
674 dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
679 cpm_i2c_shutdown(cpm);
686 static int cpm_i2c_remove(struct platform_device *ofdev)
688 struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
690 i2c_del_adapter(&cpm->adap);
692 cpm_i2c_shutdown(cpm);
699 static const struct of_device_id cpm_i2c_match[] = {
701 .compatible = "fsl,cpm1-i2c",
704 .compatible = "fsl,cpm2-i2c",
709 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
711 static struct platform_driver cpm_i2c_driver = {
712 .probe = cpm_i2c_probe,
713 .remove = cpm_i2c_remove,
715 .name = "fsl-i2c-cpm",
716 .of_match_table = cpm_i2c_match,
720 module_platform_driver(cpm_i2c_driver);
722 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
723 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
724 MODULE_LICENSE("GPL");