drivers/i2c/busses/i2c-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * I2C bus driver for the Cadence I2C controller.
   4  *
   5  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/i2c.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/reset.h>
  20
  21 /* Register offsets for the I2C device. */
  22 #define CDNS_I2C_CR_OFFSET              0x00 /* Control Register, RW */
  23 #define CDNS_I2C_SR_OFFSET              0x04 /* Status Register, RO */
  24 #define CDNS_I2C_ADDR_OFFSET            0x08 /* I2C Address Register, RW */
  25 #define CDNS_I2C_DATA_OFFSET            0x0C /* I2C Data Register, RW */
  26 #define CDNS_I2C_ISR_OFFSET             0x10 /* IRQ Status Register, RW */
  27 #define CDNS_I2C_XFER_SIZE_OFFSET       0x14 /* Transfer Size Register, RW */
  28 #define CDNS_I2C_TIME_OUT_OFFSET        0x1C /* Time Out Register, RW */
  29 #define CDNS_I2C_IMR_OFFSET             0x20 /* IRQ Mask Register, RO */
  30 #define CDNS_I2C_IER_OFFSET             0x24 /* IRQ Enable Register, WO */
  31 #define CDNS_I2C_IDR_OFFSET             0x28 /* IRQ Disable Register, WO */
  32
  33 /* Control Register Bit mask definitions */
  34 #define CDNS_I2C_CR_HOLD                BIT(4) /* Hold Bus bit */
  35 #define CDNS_I2C_CR_ACK_EN              BIT(3)
  36 #define CDNS_I2C_CR_NEA                 BIT(2)
  37 #define CDNS_I2C_CR_MS                  BIT(1)
  38 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
  39 #define CDNS_I2C_CR_RW                  BIT(0)
  40 /* 1 = Auto init FIFO to zeroes */
  41 #define CDNS_I2C_CR_CLR_FIFO            BIT(6)
  42 #define CDNS_I2C_CR_DIVA_SHIFT          14
  43 #define CDNS_I2C_CR_DIVA_MASK           (3 << CDNS_I2C_CR_DIVA_SHIFT)
  44 #define CDNS_I2C_CR_DIVB_SHIFT          8
  45 #define CDNS_I2C_CR_DIVB_MASK           (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
  46
  47 #define CDNS_I2C_CR_MASTER_EN_MASK      (CDNS_I2C_CR_NEA | \
  48                                          CDNS_I2C_CR_ACK_EN | \
  49                                          CDNS_I2C_CR_MS)
  50
  51 #define CDNS_I2C_CR_SLAVE_EN_MASK       ~CDNS_I2C_CR_MASTER_EN_MASK
  52
  53 /* Status Register Bit mask definitions */
  54 #define CDNS_I2C_SR_BA          BIT(8)
  55 #define CDNS_I2C_SR_TXDV        BIT(6)
  56 #define CDNS_I2C_SR_RXDV        BIT(5)
  57 #define CDNS_I2C_SR_RXRW        BIT(3)
  58
  59 /*
  60  * I2C Address Register Bit mask definitions
  61  * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
  62  * bits. A write access to this register always initiates a transfer if the I2C
  63  * is in master mode.
  64  */
  65 #define CDNS_I2C_ADDR_MASK      0x000003FF /* I2C Address Mask */
  66
  67 /*
  68  * I2C Interrupt Registers Bit mask definitions
  69  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  70  * bit definitions.
  71  */
  72 #define CDNS_I2C_IXR_ARB_LOST           BIT(9)
  73 #define CDNS_I2C_IXR_RX_UNF             BIT(7)
  74 #define CDNS_I2C_IXR_TX_OVF             BIT(6)
  75 #define CDNS_I2C_IXR_RX_OVF             BIT(5)
  76 #define CDNS_I2C_IXR_SLV_RDY            BIT(4)
  77 #define CDNS_I2C_IXR_TO                 BIT(3)
  78 #define CDNS_I2C_IXR_NACK               BIT(2)
  79 #define CDNS_I2C_IXR_DATA               BIT(1)
  80 #define CDNS_I2C_IXR_COMP               BIT(0)
  81
  82 #define CDNS_I2C_IXR_ALL_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  83                                          CDNS_I2C_IXR_RX_UNF | \
  84                                          CDNS_I2C_IXR_TX_OVF | \
  85                                          CDNS_I2C_IXR_RX_OVF | \
  86                                          CDNS_I2C_IXR_SLV_RDY | \
  87                                          CDNS_I2C_IXR_TO | \
  88                                          CDNS_I2C_IXR_NACK | \
  89                                          CDNS_I2C_IXR_DATA | \
  90                                          CDNS_I2C_IXR_COMP)
  91
  92 #define CDNS_I2C_IXR_ERR_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  93                                          CDNS_I2C_IXR_RX_UNF | \
  94                                          CDNS_I2C_IXR_TX_OVF | \
  95                                          CDNS_I2C_IXR_RX_OVF | \
  96                                          CDNS_I2C_IXR_NACK)
  97
  98 #define CDNS_I2C_ENABLED_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  99                                          CDNS_I2C_IXR_RX_UNF | \
 100                                          CDNS_I2C_IXR_TX_OVF | \
 101                                          CDNS_I2C_IXR_RX_OVF | \
 102                                          CDNS_I2C_IXR_NACK | \
 103                                          CDNS_I2C_IXR_DATA | \
 104                                          CDNS_I2C_IXR_COMP)
 105
 106 #define CDNS_I2C_IXR_SLAVE_INTR_MASK    (CDNS_I2C_IXR_RX_UNF | \
 107                                          CDNS_I2C_IXR_TX_OVF | \
 108                                          CDNS_I2C_IXR_RX_OVF | \
 109                                          CDNS_I2C_IXR_TO | \
 110                                          CDNS_I2C_IXR_NACK | \
 111                                          CDNS_I2C_IXR_DATA | \
 112                                          CDNS_I2C_IXR_COMP)
 113
 114 #define CDNS_I2C_TIMEOUT                msecs_to_jiffies(1000)
 115 /* timeout for pm runtime autosuspend */
 116 #define CNDS_I2C_PM_TIMEOUT             1000    /* ms */
 117
 118 #define CDNS_I2C_FIFO_DEPTH_DEFAULT     16
 119 #define CDNS_I2C_MAX_TRANSFER_SIZE      255
 120 /* Transfer size in multiples of data interrupt depth */
 121 #define CDNS_I2C_TRANSFER_SIZE(max)     ((max) - 3)
 122
 123 #define DRIVER_NAME             "cdns-i2c"
 124
 125 #define CDNS_I2C_DIVA_MAX       4
 126 #define CDNS_I2C_DIVB_MAX       64
 127
 128 #define CDNS_I2C_TIMEOUT_MAX    0xFF
 129
 130 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
 131 #define CDNS_I2C_POLL_US        100000
 132 #define CDNS_I2C_TIMEOUT_US     500000
 133
 134 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
 135 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
 136
 137 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 138 /**
 139  * enum cdns_i2c_mode - I2C Controller current operating mode
 140  *
 141  * @CDNS_I2C_MODE_SLAVE:       I2C controller operating in slave mode
 142  * @CDNS_I2C_MODE_MASTER:      I2C Controller operating in master mode
 143  */
 144 enum cdns_i2c_mode {
 145         CDNS_I2C_MODE_SLAVE,
 146         CDNS_I2C_MODE_MASTER,
 147 };
 148
 149 /**
 150  * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
 151  *
 152  * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
 153  * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
 154  * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
 155  */
 156 enum cdns_i2c_slave_state {
 157         CDNS_I2C_SLAVE_STATE_IDLE,
 158         CDNS_I2C_SLAVE_STATE_SEND,
 159         CDNS_I2C_SLAVE_STATE_RECV,
 160 };
 161 #endif
 162
 163 /**
 164  * struct cdns_i2c - I2C device private data structure
 165  *
 166  * @dev:                Pointer to device structure
 167  * @membase:            Base address of the I2C device
 168  * @adap:               I2C adapter instance
 169  * @p_msg:              Message pointer
 170  * @err_status:         Error status in Interrupt Status Register
 171  * @xfer_done:          Transfer complete status
 172  * @p_send_buf:         Pointer to transmit buffer
 173  * @p_recv_buf:         Pointer to receive buffer
 174  * @send_count:         Number of bytes still expected to send
 175  * @recv_count:         Number of bytes still expected to receive
 176  * @curr_recv_count:    Number of bytes to be received in current transfer
 177  * @input_clk:          Input clock to I2C controller
 178  * @i2c_clk:            Maximum I2C clock speed
 179  * @bus_hold_flag:      Flag used in repeated start for clearing HOLD bit
 180  * @clk:                Pointer to struct clk
 181  * @clk_rate_change_nb: Notifier block for clock rate changes
 182  * @reset:              Reset control for the device
 183  * @quirks:             flag for broken hold bit usage in r1p10
 184  * @ctrl_reg:           Cached value of the control register.
 185  * @rinfo:              I2C GPIO recovery information
 186  * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
 187  * @slave:              Registered slave instance.
 188  * @dev_mode:           I2C operating role(master/slave).
 189  * @slave_state:        I2C Slave state(idle/read/write).
 190  * @fifo_depth:         The depth of the transfer FIFO
 191  * @transfer_size:      The maximum number of bytes in one transfer
 192  */
 193 struct cdns_i2c {
 194         struct device           *dev;
 195         void __iomem *membase;
 196         struct i2c_adapter adap;
 197         struct i2c_msg *p_msg;
 198         int err_status;
 199         struct completion xfer_done;
 200         unsigned char *p_send_buf;
 201         unsigned char *p_recv_buf;
 202         unsigned int send_count;
 203         unsigned int recv_count;
 204         unsigned int curr_recv_count;
 205         unsigned long input_clk;
 206         unsigned int i2c_clk;
 207         unsigned int bus_hold_flag;
 208         struct clk *clk;
 209         struct notifier_block clk_rate_change_nb;
 210         struct reset_control *reset;
 211         u32 quirks;
 212         u32 ctrl_reg;
 213         struct i2c_bus_recovery_info rinfo;
 214 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 215         u16 ctrl_reg_diva_divb;
 216         struct i2c_client *slave;
 217         enum cdns_i2c_mode dev_mode;
 218         enum cdns_i2c_slave_state slave_state;
 219 #endif
 220         u32 fifo_depth;
 221         unsigned int transfer_size;
 222 };
 223
 224 struct cdns_platform_data {
 225         u32 quirks;
 226 };
 227
 228 #define to_cdns_i2c(_nb)        container_of(_nb, struct cdns_i2c, \
 229                                              clk_rate_change_nb)
 230
 231 /**
 232  * cdns_i2c_clear_bus_hold - Clear bus hold bit
 233  * @id: Pointer to driver data struct
 234  *
 235  * Helper to clear the controller's bus hold bit.
 236  */
 237 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
 238 {
 239         u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 240         if (reg & CDNS_I2C_CR_HOLD)
 241                 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
 242 }
 243
 244 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
 245 {
 246         return (hold_wrkaround &&
 247                 (id->curr_recv_count == id->fifo_depth + 1));
 248 }
 249
 250 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 251 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
 252 {
 253         /* Disable all interrupts */
 254         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 255
 256         /* Clear FIFO and transfer size */
 257         cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
 258
 259         /* Update device mode and state */
 260         id->dev_mode = mode;
 261         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 262
 263         switch (mode) {
 264         case CDNS_I2C_MODE_MASTER:
 265                 /* Enable i2c master */
 266                 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
 267                                   CDNS_I2C_CR_MASTER_EN_MASK,
 268                                   CDNS_I2C_CR_OFFSET);
 269                 /*
 270                  * This delay is needed to give the IP some time to switch to
 271                  * the master mode. With lower values(like 110 us) i2cdetect
 272                  * will not detect any slave and without this delay, the IP will
 273                  * trigger a timeout interrupt.
 274                  */
 275                 usleep_range(115, 125);
 276                 break;
 277         case CDNS_I2C_MODE_SLAVE:
 278                 /* Enable i2c slave */
 279                 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
 280                                   CDNS_I2C_CR_SLAVE_EN_MASK,
 281                                   CDNS_I2C_CR_OFFSET);
 282
 283                 /* Setting slave address */
 284                 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
 285                                   CDNS_I2C_ADDR_OFFSET);
 286
 287                 /* Enable slave send/receive interrupts */
 288                 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
 289                                   CDNS_I2C_IER_OFFSET);
 290                 break;
 291         }
 292 }
 293
 294 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
 295 {
 296         u8 bytes;
 297         unsigned char data;
 298
 299         /* Prepare backend for data reception */
 300         if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
 301                 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
 302                 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
 303         }
 304
 305         /* Fetch number of bytes to receive */
 306         bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 307
 308         /* Read data and send to backend */
 309         while (bytes--) {
 310                 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 311                 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
 312         }
 313 }
 314
 315 static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
 316 {
 317         u8 data;
 318
 319         /* Prepare backend for data transmission */
 320         if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
 321                 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
 322                 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
 323         } else {
 324                 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
 325         }
 326
 327         /* Send data over bus */
 328         cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
 329 }
 330
 331 /**
 332  * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
 333  * @ptr:       Pointer to I2C device private data
 334  *
 335  * This function handles the data interrupt and transfer complete interrupt of
 336  * the I2C device in slave role.
 337  *
 338  * Return: IRQ_HANDLED always
 339  */
 340 static irqreturn_t cdns_i2c_slave_isr(void *ptr)
 341 {
 342         struct cdns_i2c *id = ptr;
 343         unsigned int isr_status, i2c_status;
 344
 345         /* Fetch the interrupt status */
 346         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 347         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 348
 349         /* Ignore masked interrupts */
 350         isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
 351
 352         /* Fetch transfer mode (send/receive) */
 353         i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 354
 355         /* Handle data send/receive */
 356         if (i2c_status & CDNS_I2C_SR_RXRW) {
 357                 /* Send data to master */
 358                 if (isr_status & CDNS_I2C_IXR_DATA)
 359                         cdns_i2c_slave_send_data(id);
 360
 361                 if (isr_status & CDNS_I2C_IXR_COMP) {
 362                         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 363                         i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
 364                 }
 365         } else {
 366                 /* Receive data from master */
 367                 if (isr_status & CDNS_I2C_IXR_DATA)
 368                         cdns_i2c_slave_rcv_data(id);
 369
 370                 if (isr_status & CDNS_I2C_IXR_COMP) {
 371                         cdns_i2c_slave_rcv_data(id);
 372                         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 373                         i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
 374                 }
 375         }
 376
 377         /* Master indicated xfer stop or fifo underflow/overflow */
 378         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
 379                           CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
 380                 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 381                 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
 382                 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
 383         }
 384
 385         return IRQ_HANDLED;
 386 }
 387 #endif
 388
 389 /**
 390  * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
 391  * @ptr:       Pointer to I2C device private data
 392  *
 393  * This function handles the data interrupt, transfer complete interrupt and
 394  * the error interrupts of the I2C device in master role.
 395  *
 396  * Return: IRQ_HANDLED always
 397  */
 398 static irqreturn_t cdns_i2c_master_isr(void *ptr)
 399 {
 400         unsigned int isr_status, avail_bytes;
 401         unsigned int bytes_to_send;
 402         bool updatetx;
 403         struct cdns_i2c *id = ptr;
 404         /* Signal completion only after everything is updated */
 405         int done_flag = 0;
 406         irqreturn_t status = IRQ_NONE;
 407
 408         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 409         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 410         id->err_status = 0;
 411
 412         /* Handling nack and arbitration lost interrupt */
 413         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
 414                 done_flag = 1;
 415                 status = IRQ_HANDLED;
 416         }
 417
 418         /*
 419          * Check if transfer size register needs to be updated again for a
 420          * large data receive operation.
 421          */
 422         updatetx = id->recv_count > id->curr_recv_count;
 423
 424         /* When receiving, handle data interrupt and completion interrupt */
 425         if (id->p_recv_buf &&
 426             ((isr_status & CDNS_I2C_IXR_COMP) ||
 427              (isr_status & CDNS_I2C_IXR_DATA))) {
 428                 /* Read data if receive data valid is set */
 429                 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
 430                        CDNS_I2C_SR_RXDV) {
 431                         if (id->recv_count > 0) {
 432                                 *(id->p_recv_buf)++ =
 433                                         cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 434                                 id->recv_count--;
 435                                 id->curr_recv_count--;
 436
 437                                 /*
 438                                  * Clear hold bit that was set for FIFO control
 439                                  * if RX data left is less than or equal to
 440                                  * FIFO DEPTH unless repeated start is selected
 441                                  */
 442                                 if (id->recv_count <= id->fifo_depth &&
 443                                     !id->bus_hold_flag)
 444                                         cdns_i2c_clear_bus_hold(id);
 445
 446                         } else {
 447                                 dev_err(id->adap.dev.parent,
 448                                         "xfer_size reg rollover. xfer aborted!\n");
 449                                 id->err_status |= CDNS_I2C_IXR_TO;
 450                                 break;
 451                         }
 452
 453                         if (cdns_is_holdquirk(id, updatetx))
 454                                 break;
 455                 }
 456
 457                 /*
 458                  * The controller sends NACK to the slave when transfer size
 459                  * register reaches zero without considering the HOLD bit.
 460                  * This workaround is implemented for large data transfers to
 461                  * maintain transfer size non-zero while performing a large
 462                  * receive operation.
 463                  */
 464                 if (cdns_is_holdquirk(id, updatetx)) {
 465                         /* wait while fifo is full */
 466                         while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
 467                                (id->curr_recv_count - id->fifo_depth))
 468                                 ;
 469
 470                         /*
 471                          * Check number of bytes to be received against maximum
 472                          * transfer size and update register accordingly.
 473                          */
 474                         if (((int)(id->recv_count) - id->fifo_depth) >
 475                             id->transfer_size) {
 476                                 cdns_i2c_writereg(id->transfer_size,
 477                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 478                                 id->curr_recv_count = id->transfer_size +
 479                                                       id->fifo_depth;
 480                         } else {
 481                                 cdns_i2c_writereg(id->recv_count -
 482                                                   id->fifo_depth,
 483                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 484                                 id->curr_recv_count = id->recv_count;
 485                         }
 486                 }
 487
 488                 /* Clear hold (if not repeated start) and signal completion */
 489                 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
 490                         if (!id->bus_hold_flag)
 491                                 cdns_i2c_clear_bus_hold(id);
 492                         done_flag = 1;
 493                 }
 494
 495                 status = IRQ_HANDLED;
 496         }
 497
 498         /* When sending, handle transfer complete interrupt */
 499         if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
 500                 /*
 501                  * If there is more data to be sent, calculate the
 502                  * space available in FIFO and fill with that many bytes.
 503                  */
 504                 if (id->send_count) {
 505                         avail_bytes = id->fifo_depth -
 506                             cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 507                         if (id->send_count > avail_bytes)
 508                                 bytes_to_send = avail_bytes;
 509                         else
 510                                 bytes_to_send = id->send_count;
 511
 512                         while (bytes_to_send--) {
 513                                 cdns_i2c_writereg(
 514                                         (*(id->p_send_buf)++),
 515                                          CDNS_I2C_DATA_OFFSET);
 516                                 id->send_count--;
 517                         }
 518                 } else {
 519                         /*
 520                          * Signal the completion of transaction and
 521                          * clear the hold bus bit if there are no
 522                          * further messages to be processed.
 523                          */
 524                         done_flag = 1;
 525                 }
 526                 if (!id->send_count && !id->bus_hold_flag)
 527                         cdns_i2c_clear_bus_hold(id);
 528
 529                 status = IRQ_HANDLED;
 530         }
 531
 532         /* Update the status for errors */
 533         id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
 534         if (id->err_status)
 535                 status = IRQ_HANDLED;
 536
 537         if (done_flag)
 538                 complete(&id->xfer_done);
 539
 540         return status;
 541 }
 542
 543 /**
 544  * cdns_i2c_isr - Interrupt handler for the I2C device
 545  * @irq:        irq number for the I2C device
 546  * @ptr:        void pointer to cdns_i2c structure
 547  *
 548  * This function passes the control to slave/master based on current role of
 549  * i2c controller.
 550  *
 551  * Return: IRQ_HANDLED always
 552  */
 553 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
 554 {
 555 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 556         struct cdns_i2c *id = ptr;
 557
 558         if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
 559                 return cdns_i2c_slave_isr(ptr);
 560 #endif
 561         return cdns_i2c_master_isr(ptr);
 562 }
 563
 564 /**
 565  * cdns_i2c_mrecv - Prepare and start a master receive operation
 566  * @id:         pointer to the i2c device structure
 567  */
 568 static void cdns_i2c_mrecv(struct cdns_i2c *id)
 569 {
 570         unsigned int ctrl_reg;
 571         unsigned int isr_status;
 572         unsigned long flags;
 573         bool hold_clear = false;
 574         bool irq_save = false;
 575
 576         u32 addr;
 577
 578         id->p_recv_buf = id->p_msg->buf;
 579         id->recv_count = id->p_msg->len;
 580
 581         /* Put the controller in master receive mode and clear the FIFO */
 582         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 583         ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
 584
 585         /*
 586          * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
 587          * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
 588          * PEC is enabled, otherwise 1.
 589          */
 590         if (id->p_msg->flags & I2C_M_RECV_LEN)
 591                 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
 592
 593         id->curr_recv_count = id->recv_count;
 594
 595         /*
 596          * Check for the message size against FIFO depth and set the
 597          * 'hold bus' bit if it is greater than FIFO depth.
 598          */
 599         if (id->recv_count > id->fifo_depth)
 600                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 601
 602         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 603
 604         /* Clear the interrupts in interrupt status register */
 605         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 606         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 607
 608         /*
 609          * The no. of bytes to receive is checked against the limit of
 610          * max transfer size. Set transfer size register with no of bytes
 611          * receive if it is less than transfer size and transfer size if
 612          * it is more. Enable the interrupts.
 613          */
 614         if (id->recv_count > id->transfer_size) {
 615                 cdns_i2c_writereg(id->transfer_size,
 616                                   CDNS_I2C_XFER_SIZE_OFFSET);
 617                 id->curr_recv_count = id->transfer_size;
 618         } else {
 619                 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
 620         }
 621
 622         /* Determine hold_clear based on number of bytes to receive and hold flag */
 623         if (!id->bus_hold_flag && id->recv_count <= id->fifo_depth) {
 624                 if (ctrl_reg & CDNS_I2C_CR_HOLD) {
 625                         hold_clear = true;
 626                         if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT)
 627                                 irq_save = true;
 628                 }
 629         }
 630
 631         addr = id->p_msg->addr;
 632         addr &= CDNS_I2C_ADDR_MASK;
 633
 634         if (hold_clear) {
 635                 ctrl_reg &= ~CDNS_I2C_CR_HOLD;
 636                 /*
 637                  * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
 638                  * register reaches '0'. This is an IP bug which causes transfer size
 639                  * register overflow to 0xFF. To satisfy this timing requirement,
 640                  * disable the interrupts on current processor core between register
 641                  * writes to slave address register and control register.
 642                  */
 643                 if (irq_save)
 644                         local_irq_save(flags);
 645
 646                 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
 647                 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 648                 /* Read it back to avoid bufferring and make sure write happens */
 649                 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 650
 651                 if (irq_save)
 652                         local_irq_restore(flags);
 653         } else {
 654                 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
 655         }
 656
 657         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 658 }
 659
 660 /**
 661  * cdns_i2c_msend - Prepare and start a master send operation
 662  * @id:         pointer to the i2c device
 663  */
 664 static void cdns_i2c_msend(struct cdns_i2c *id)
 665 {
 666         unsigned int avail_bytes;
 667         unsigned int bytes_to_send;
 668         unsigned int ctrl_reg;
 669         unsigned int isr_status;
 670
 671         id->p_recv_buf = NULL;
 672         id->p_send_buf = id->p_msg->buf;
 673         id->send_count = id->p_msg->len;
 674
 675         /* Set the controller in Master transmit mode and clear the FIFO. */
 676         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 677         ctrl_reg &= ~CDNS_I2C_CR_RW;
 678         ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
 679
 680         /*
 681          * Check for the message size against FIFO depth and set the
 682          * 'hold bus' bit if it is greater than FIFO depth.
 683          */
 684         if (id->send_count > id->fifo_depth)
 685                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 686         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 687
 688         /* Clear the interrupts in interrupt status register. */
 689         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 690         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 691
 692         /*
 693          * Calculate the space available in FIFO. Check the message length
 694          * against the space available, and fill the FIFO accordingly.
 695          * Enable the interrupts.
 696          */
 697         avail_bytes = id->fifo_depth -
 698                                 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 699
 700         if (id->send_count > avail_bytes)
 701                 bytes_to_send = avail_bytes;
 702         else
 703                 bytes_to_send = id->send_count;
 704
 705         while (bytes_to_send--) {
 706                 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
 707                 id->send_count--;
 708         }
 709
 710         /*
 711          * Clear the bus hold flag if there is no more data
 712          * and if it is the last message.
 713          */
 714         if (!id->bus_hold_flag && !id->send_count)
 715                 cdns_i2c_clear_bus_hold(id);
 716         /* Set the slave address in address register - triggers operation. */
 717         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 718                                                 CDNS_I2C_ADDR_OFFSET);
 719
 720         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 721 }
 722
 723 /**
 724  * cdns_i2c_master_reset - Reset the interface
 725  * @adap:       pointer to the i2c adapter driver instance
 726  *
 727  * This function cleanup the fifos, clear the hold bit and status
 728  * and disable the interrupts.
 729  */
 730 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
 731 {
 732         struct cdns_i2c *id = adap->algo_data;
 733         u32 regval;
 734
 735         /* Disable the interrupts */
 736         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 737         /* Clear the hold bit and fifos */
 738         regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 739         regval &= ~CDNS_I2C_CR_HOLD;
 740         regval |= CDNS_I2C_CR_CLR_FIFO;
 741         cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
 742         /* Update the transfercount register to zero */
 743         cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
 744         /* Clear the interrupt status register */
 745         regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 746         cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
 747         /* Clear the status register */
 748         regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 749         cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
 750 }
 751
 752 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
 753                 struct i2c_adapter *adap)
 754 {
 755         unsigned long time_left, msg_timeout;
 756         u32 reg;
 757
 758         id->p_msg = msg;
 759         id->err_status = 0;
 760         reinit_completion(&id->xfer_done);
 761
 762         /* Check for the TEN Bit mode on each msg */
 763         reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 764         if (msg->flags & I2C_M_TEN) {
 765                 if (reg & CDNS_I2C_CR_NEA)
 766                         cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
 767                                         CDNS_I2C_CR_OFFSET);
 768         } else {
 769                 if (!(reg & CDNS_I2C_CR_NEA))
 770                         cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
 771                                         CDNS_I2C_CR_OFFSET);
 772         }
 773
 774         /* Check for the R/W flag on each msg */
 775         if (msg->flags & I2C_M_RD)
 776                 cdns_i2c_mrecv(id);
 777         else
 778                 cdns_i2c_msend(id);
 779
 780         /* Minimal time to execute this message */
 781         msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
 782         /* Plus some wiggle room */
 783         msg_timeout += msecs_to_jiffies(500);
 784
 785         if (msg_timeout < adap->timeout)
 786                 msg_timeout = adap->timeout;
 787
 788         /* Wait for the signal of completion */
 789         time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
 790         if (time_left == 0) {
 791                 cdns_i2c_master_reset(adap);
 792                 dev_err(id->adap.dev.parent,
 793                                 "timeout waiting on completion\n");
 794                 return -ETIMEDOUT;
 795         }
 796
 797         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
 798                           CDNS_I2C_IDR_OFFSET);
 799
 800         /* If it is bus arbitration error, try again */
 801         if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
 802                 return -EAGAIN;
 803
 804         if (msg->flags & I2C_M_RECV_LEN)
 805                 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * cdns_i2c_master_xfer - The main i2c transfer function
 812  * @adap:       pointer to the i2c adapter driver instance
 813  * @msgs:       pointer to the i2c message structure
 814  * @num:        the number of messages to transfer
 815  *
 816  * Initiates the send/recv activity based on the transfer message received.
 817  *
 818  * Return: number of msgs processed on success, negative error otherwise
 819  */
 820 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 821                                 int num)
 822 {
 823         int ret, count;
 824         u32 reg;
 825         struct cdns_i2c *id = adap->algo_data;
 826         bool hold_quirk;
 827 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 828         bool change_role = false;
 829 #endif
 830
 831         ret = pm_runtime_resume_and_get(id->dev);
 832         if (ret < 0)
 833                 return ret;
 834
 835 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 836         /* Check i2c operating mode and switch if possible */
 837         if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
 838                 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) {
 839                         ret = -EAGAIN;
 840                         goto out;
 841                 }
 842
 843                 /* Set mode to master */
 844                 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
 845
 846                 /* Mark flag to change role once xfer is completed */
 847                 change_role = true;
 848         }
 849 #endif
 850
 851         /* Check if the bus is free */
 852
 853         ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET,
 854                                          reg,
 855                                          !(reg & CDNS_I2C_SR_BA),
 856                                          CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US);
 857         if (ret) {
 858                 ret = -EAGAIN;
 859                 if (id->adap.bus_recovery_info)
 860                         i2c_recover_bus(adap);
 861                 goto out;
 862         }
 863
 864         hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 865         /*
 866          * Set the flag to one when multiple messages are to be
 867          * processed with a repeated start.
 868          */
 869         if (num > 1) {
 870                 /*
 871                  * This controller does not give completion interrupt after a
 872                  * master receive message if HOLD bit is set (repeated start),
 873                  * resulting in SW timeout. Hence, if a receive message is
 874                  * followed by any other message, an error is returned
 875                  * indicating that this sequence is not supported.
 876                  */
 877                 for (count = 0; (count < num - 1 && hold_quirk); count++) {
 878                         if (msgs[count].flags & I2C_M_RD) {
 879                                 dev_warn(adap->dev.parent,
 880                                          "Can't do repeated start after a receive message\n");
 881                                 ret = -EOPNOTSUPP;
 882                                 goto out;
 883                         }
 884                 }
 885                 id->bus_hold_flag = 1;
 886                 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 887                 reg |= CDNS_I2C_CR_HOLD;
 888                 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
 889         } else {
 890                 id->bus_hold_flag = 0;
 891         }
 892
 893         /* Process the msg one by one */
 894         for (count = 0; count < num; count++, msgs++) {
 895                 if (count == (num - 1))
 896                         id->bus_hold_flag = 0;
 897
 898                 ret = cdns_i2c_process_msg(id, msgs, adap);
 899                 if (ret)
 900                         goto out;
 901
 902                 /* Report the other error interrupts to application */
 903                 if (id->err_status) {
 904                         cdns_i2c_master_reset(adap);
 905
 906                         if (id->err_status & CDNS_I2C_IXR_NACK) {
 907                                 ret = -ENXIO;
 908                                 goto out;
 909                         }
 910                         ret = -EIO;
 911                         goto out;
 912                 }
 913         }
 914
 915         ret = num;
 916
 917 out:
 918
 919 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 920         /* Switch i2c mode to slave */
 921         if (change_role)
 922                 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
 923 #endif
 924
 925         pm_runtime_mark_last_busy(id->dev);
 926         pm_runtime_put_autosuspend(id->dev);
 927         return ret;
 928 }
 929
 930 /**
 931  * cdns_i2c_func - Returns the supported features of the I2C driver
 932  * @adap:       pointer to the i2c adapter structure
 933  *
 934  * Return: 32 bit value, each bit corresponding to a feature
 935  */
 936 static u32 cdns_i2c_func(struct i2c_adapter *adap)
 937 {
 938         u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 939                         (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 940                         I2C_FUNC_SMBUS_BLOCK_DATA;
 941
 942 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 943         func |= I2C_FUNC_SLAVE;
 944 #endif
 945
 946         return func;
 947 }
 948
 949 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 950 static int cdns_reg_slave(struct i2c_client *slave)
 951 {
 952         int ret;
 953         struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
 954                                                                         adap);
 955
 956         if (id->slave)
 957                 return -EBUSY;
 958
 959         if (slave->flags & I2C_CLIENT_TEN)
 960                 return -EAFNOSUPPORT;
 961
 962         ret = pm_runtime_resume_and_get(id->dev);
 963         if (ret < 0)
 964                 return ret;
 965
 966         /* Store slave information */
 967         id->slave = slave;
 968
 969         /* Enable I2C slave */
 970         cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
 971
 972         return 0;
 973 }
 974
 975 static int cdns_unreg_slave(struct i2c_client *slave)
 976 {
 977         struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
 978                                                                         adap);
 979
 980         pm_runtime_put(id->dev);
 981
 982         /* Remove slave information */
 983         id->slave = NULL;
 984
 985         /* Enable I2C master */
 986         cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
 987
 988         return 0;
 989 }
 990 #endif
 991
 992 static const struct i2c_algorithm cdns_i2c_algo = {
 993         .master_xfer    = cdns_i2c_master_xfer,
 994         .functionality  = cdns_i2c_func,
 995 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 996         .reg_slave      = cdns_reg_slave,
 997         .unreg_slave    = cdns_unreg_slave,
 998 #endif
 999 };
1000
1001 /**
1002  * cdns_i2c_calc_divs - Calculate clock dividers
1003  * @f:          I2C clock frequency
1004  * @input_clk:  Input clock frequency
1005  * @a:          First divider (return value)
1006  * @b:          Second divider (return value)
1007  *
1008  * f is used as input and output variable. As input it is used as target I2C
1009  * frequency. On function exit f holds the actually resulting I2C frequency.
1010  *
1011  * Return: 0 on success, negative errno otherwise.
1012  */
1013 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
1014                 unsigned int *a, unsigned int *b)
1015 {
1016         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
1017         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
1018         unsigned int last_error, current_error;
1019
1020         /* calculate (divisor_a+1) x (divisor_b+1) */
1021         temp = input_clk / (22 * fscl);
1022
1023         /*
1024          * If the calculated value is negative or 0, the fscl input is out of
1025          * range. Return error.
1026          */
1027         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
1028                 return -EINVAL;
1029
1030         last_error = -1;
1031         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
1032                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
1033
1034                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
1035                         continue;
1036                 div_b--;
1037
1038                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
1039
1040                 if (actual_fscl > fscl)
1041                         continue;
1042
1043                 current_error = fscl - actual_fscl;
1044
1045                 if (last_error > current_error) {
1046                         calc_div_a = div_a;
1047                         calc_div_b = div_b;
1048                         best_fscl = actual_fscl;
1049                         last_error = current_error;
1050                 }
1051         }
1052
1053         *a = calc_div_a;
1054         *b = calc_div_b;
1055         *f = best_fscl;
1056
1057         return 0;
1058 }
1059
1060 /**
1061  * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1062  * @clk_in:     I2C clock input frequency in Hz
1063  * @id:         Pointer to the I2C device structure
1064  *
1065  * The device must be idle rather than busy transferring data before setting
1066  * these device options.
1067  * The data rate is set by values in the control register.
1068  * The formula for determining the correct register values is
1069  *      Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1070  * See the hardware data sheet for a full explanation of setting the serial
1071  * clock rate. The clock can not be faster than the input clock divide by 22.
1072  * The two most common clock rates are 100KHz and 400KHz.
1073  *
1074  * Return: 0 on success, negative error otherwise
1075  */
1076 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1077 {
1078         unsigned int div_a, div_b;
1079         unsigned int ctrl_reg;
1080         int ret = 0;
1081         unsigned long fscl = id->i2c_clk;
1082
1083         ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1084         if (ret)
1085                 return ret;
1086
1087         ctrl_reg = id->ctrl_reg;
1088         ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1089         ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1090                         (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1091         id->ctrl_reg = ctrl_reg;
1092         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1093 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1094         id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1095                                  CDNS_I2C_CR_DIVB_MASK);
1096 #endif
1097         return 0;
1098 }
1099
1100 /**
1101  * cdns_i2c_clk_notifier_cb - Clock rate change callback
1102  * @nb:         Pointer to notifier block
1103  * @event:      Notification reason
1104  * @data:       Pointer to notification data object
1105  *
1106  * This function is called when the cdns_i2c input clock frequency changes.
1107  * The callback checks whether a valid bus frequency can be generated after the
1108  * change. If so, the change is acknowledged, otherwise the change is aborted.
1109  * New dividers are written to the HW in the pre- or post change notification
1110  * depending on the scaling direction.
1111  *
1112  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1113  *              to acknowledge the change, NOTIFY_DONE if the notification is
1114  *              considered irrelevant.
1115  */
1116 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1117                 event, void *data)
1118 {
1119         struct clk_notifier_data *ndata = data;
1120         struct cdns_i2c *id = to_cdns_i2c(nb);
1121
1122         if (pm_runtime_suspended(id->dev))
1123                 return NOTIFY_OK;
1124
1125         switch (event) {
1126         case PRE_RATE_CHANGE:
1127         {
1128                 unsigned long input_clk = ndata->new_rate;
1129                 unsigned long fscl = id->i2c_clk;
1130                 unsigned int div_a, div_b;
1131                 int ret;
1132
1133                 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1134                 if (ret) {
1135                         dev_warn(id->adap.dev.parent,
1136                                         "clock rate change rejected\n");
1137                         return NOTIFY_STOP;
1138                 }
1139
1140                 /* scale up */
1141                 if (ndata->new_rate > ndata->old_rate)
1142                         cdns_i2c_setclk(ndata->new_rate, id);
1143
1144                 return NOTIFY_OK;
1145         }
1146         case POST_RATE_CHANGE:
1147                 id->input_clk = ndata->new_rate;
1148                 /* scale down */
1149                 if (ndata->new_rate < ndata->old_rate)
1150                         cdns_i2c_setclk(ndata->new_rate, id);
1151                 return NOTIFY_OK;
1152         case ABORT_RATE_CHANGE:
1153                 /* scale up */
1154                 if (ndata->new_rate > ndata->old_rate)
1155                         cdns_i2c_setclk(ndata->old_rate, id);
1156                 return NOTIFY_OK;
1157         default:
1158                 return NOTIFY_DONE;
1159         }
1160 }
1161
1162 /**
1163  * cdns_i2c_runtime_suspend -  Runtime suspend method for the driver
1164  * @dev:        Address of the platform_device structure
1165  *
1166  * Put the driver into low power mode.
1167  *
1168  * Return: 0 always
1169  */
1170 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1171 {
1172         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1173
1174         clk_disable(xi2c->clk);
1175
1176         return 0;
1177 }
1178
1179 static int __maybe_unused cdns_i2c_suspend(struct device *dev)
1180 {
1181         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1182
1183         i2c_mark_adapter_suspended(&xi2c->adap);
1184
1185         if (!pm_runtime_status_suspended(dev))
1186                 return cdns_i2c_runtime_suspend(dev);
1187
1188         return 0;
1189 }
1190
1191 /**
1192  * cdns_i2c_init -  Controller initialisation
1193  * @id:         Device private data structure
1194  *
1195  * Initialise the i2c controller.
1196  *
1197  */
1198 static void cdns_i2c_init(struct cdns_i2c *id)
1199 {
1200         cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
1201         /*
1202          * Cadence I2C controller has a bug wherein it generates
1203          * invalid read transaction after HW timeout in master receiver mode.
1204          * HW timeout is not used by this driver and the interrupt is disabled.
1205          * But the feature itself cannot be disabled. Hence maximum value
1206          * is written to this register to reduce the chances of error.
1207          */
1208         cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1209 }
1210
1211 /**
1212  * cdns_i2c_runtime_resume - Runtime resume
1213  * @dev:        Address of the platform_device structure
1214  *
1215  * Runtime resume callback.
1216  *
1217  * Return: 0 on success and error value on error
1218  */
1219 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1220 {
1221         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1222         int ret;
1223
1224         ret = clk_enable(xi2c->clk);
1225         if (ret) {
1226                 dev_err(dev, "Cannot enable clock.\n");
1227                 return ret;
1228         }
1229         cdns_i2c_init(xi2c);
1230
1231         return 0;
1232 }
1233
1234 static int __maybe_unused cdns_i2c_resume(struct device *dev)
1235 {
1236         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1237         int err;
1238
1239         err = cdns_i2c_runtime_resume(dev);
1240         if (err)
1241                 return err;
1242
1243         if (pm_runtime_status_suspended(dev)) {
1244                 err = cdns_i2c_runtime_suspend(dev);
1245                 if (err)
1246                         return err;
1247         }
1248
1249         i2c_mark_adapter_resumed(&xi2c->adap);
1250
1251         return 0;
1252 }
1253
1254 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1255         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_i2c_suspend, cdns_i2c_resume)
1256         SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1257                            cdns_i2c_runtime_resume, NULL)
1258 };
1259
1260 static const struct cdns_platform_data r1p10_i2c_def = {
1261         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1262 };
1263
1264 static const struct of_device_id cdns_i2c_of_match[] = {
1265         { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1266         { .compatible = "cdns,i2c-r1p14",},
1267         { /* end of table */ }
1268 };
1269 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1270
1271 /**
1272  * cdns_i2c_detect_transfer_size - Detect the maximum transfer size supported
1273  * @id: Device private data structure
1274  *
1275  * Detect the maximum transfer size that is supported by this instance of the
1276  * Cadence I2C controller.
1277  */
1278 static void cdns_i2c_detect_transfer_size(struct cdns_i2c *id)
1279 {
1280         u32 val;
1281
1282         /*
1283          * Writing to the transfer size register is only possible if these two bits
1284          * are set in the control register.
1285          */
1286         cdns_i2c_writereg(CDNS_I2C_CR_MS | CDNS_I2C_CR_RW, CDNS_I2C_CR_OFFSET);
1287
1288         /*
1289          * The number of writable bits of the transfer size register can be between
1290          * 4 and 8. This is a controlled through a synthesis parameter of the IP
1291          * core and can vary from instance to instance. The unused MSBs always read
1292          * back as 0. Writing 0xff and then reading the value back will report the
1293          * maximum supported transfer size.
1294          */
1295         cdns_i2c_writereg(CDNS_I2C_MAX_TRANSFER_SIZE, CDNS_I2C_XFER_SIZE_OFFSET);
1296         val = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
1297         id->transfer_size = CDNS_I2C_TRANSFER_SIZE(val);
1298         cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
1299         cdns_i2c_writereg(0, CDNS_I2C_CR_OFFSET);
1300 }
1301
1302 /**
1303  * cdns_i2c_probe - Platform registration call
1304  * @pdev:       Handle to the platform device structure
1305  *
1306  * This function does all the memory allocation and registration for the i2c
1307  * device. User can modify the address mode to 10 bit address mode using the
1308  * ioctl call with option I2C_TENBIT.
1309  *
1310  * Return: 0 on success, negative error otherwise
1311  */
1312 static int cdns_i2c_probe(struct platform_device *pdev)
1313 {
1314         struct resource *r_mem;
1315         struct cdns_i2c *id;
1316         int ret, irq;
1317         const struct of_device_id *match;
1318
1319         id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1320         if (!id)
1321                 return -ENOMEM;
1322
1323         id->dev = &pdev->dev;
1324         platform_set_drvdata(pdev, id);
1325
1326         match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1327         if (match && match->data) {
1328                 const struct cdns_platform_data *data = match->data;
1329                 id->quirks = data->quirks;
1330         }
1331
1332         id->rinfo.pinctrl = devm_pinctrl_get(&pdev->dev);
1333         if (IS_ERR(id->rinfo.pinctrl)) {
1334                 int err = PTR_ERR(id->rinfo.pinctrl);
1335
1336                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1337                 if (err != -ENODEV)
1338                         return err;
1339         } else {
1340                 id->adap.bus_recovery_info = &id->rinfo;
1341         }
1342
1343         id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1344         if (IS_ERR(id->membase))
1345                 return PTR_ERR(id->membase);
1346
1347         irq = platform_get_irq(pdev, 0);
1348         if (irq < 0)
1349                 return irq;
1350
1351         id->adap.owner = THIS_MODULE;
1352         id->adap.dev.of_node = pdev->dev.of_node;
1353         id->adap.algo = &cdns_i2c_algo;
1354         id->adap.timeout = CDNS_I2C_TIMEOUT;
1355         id->adap.retries = 3;           /* Default retry value. */
1356         id->adap.algo_data = id;
1357         id->adap.dev.parent = &pdev->dev;
1358         init_completion(&id->xfer_done);
1359         snprintf(id->adap.name, sizeof(id->adap.name),
1360                  "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1361
1362         id->clk = devm_clk_get(&pdev->dev, NULL);
1363         if (IS_ERR(id->clk))
1364                 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk),
1365                                      "input clock not found.\n");
1366
1367         id->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
1368         if (IS_ERR(id->reset))
1369                 return dev_err_probe(&pdev->dev, PTR_ERR(id->reset),
1370                                      "Failed to request reset.\n");
1371
1372         ret = clk_prepare_enable(id->clk);
1373         if (ret)
1374                 dev_err(&pdev->dev, "Unable to enable clock.\n");
1375
1376         ret = reset_control_deassert(id->reset);
1377         if (ret) {
1378                 dev_err_probe(&pdev->dev, ret,
1379                               "Failed to de-assert reset.\n");
1380                 goto err_clk_dis;
1381         }
1382
1383         pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1384         pm_runtime_use_autosuspend(id->dev);
1385         pm_runtime_set_active(id->dev);
1386         pm_runtime_enable(id->dev);
1387
1388         id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1389         if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1390                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1391         id->input_clk = clk_get_rate(id->clk);
1392
1393         ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1394                         &id->i2c_clk);
1395         if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1396                 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1397
1398 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1399         /* Set initial mode to master */
1400         id->dev_mode = CDNS_I2C_MODE_MASTER;
1401         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1402 #endif
1403         id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS;
1404
1405         id->fifo_depth = CDNS_I2C_FIFO_DEPTH_DEFAULT;
1406         of_property_read_u32(pdev->dev.of_node, "fifo-depth", &id->fifo_depth);
1407
1408         cdns_i2c_detect_transfer_size(id);
1409
1410         ret = cdns_i2c_setclk(id->input_clk, id);
1411         if (ret) {
1412                 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1413                 ret = -EINVAL;
1414                 goto err_clk_notifier_unregister;
1415         }
1416
1417         ret = devm_request_irq(&pdev->dev, irq, cdns_i2c_isr, 0,
1418                                  DRIVER_NAME, id);
1419         if (ret) {
1420                 dev_err(&pdev->dev, "cannot get irq %d\n", irq);
1421                 goto err_clk_notifier_unregister;
1422         }
1423         cdns_i2c_init(id);
1424
1425         ret = i2c_add_adapter(&id->adap);
1426         if (ret < 0)
1427                 goto err_clk_notifier_unregister;
1428
1429         dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1430                  id->i2c_clk / 1000, (unsigned long)r_mem->start, irq);
1431
1432         return 0;
1433
1434 err_clk_notifier_unregister:
1435         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1436         reset_control_assert(id->reset);
1437 err_clk_dis:
1438         clk_disable_unprepare(id->clk);
1439         pm_runtime_disable(&pdev->dev);
1440         pm_runtime_set_suspended(&pdev->dev);
1441         return ret;
1442 }
1443
1444 /**
1445  * cdns_i2c_remove - Unregister the device after releasing the resources
1446  * @pdev:       Handle to the platform device structure
1447  *
1448  * This function frees all the resources allocated to the device.
1449  *
1450  * Return: 0 always
1451  */
1452 static void cdns_i2c_remove(struct platform_device *pdev)
1453 {
1454         struct cdns_i2c *id = platform_get_drvdata(pdev);
1455
1456         pm_runtime_disable(&pdev->dev);
1457         pm_runtime_set_suspended(&pdev->dev);
1458         pm_runtime_dont_use_autosuspend(&pdev->dev);
1459
1460         i2c_del_adapter(&id->adap);
1461         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1462         reset_control_assert(id->reset);
1463         clk_disable_unprepare(id->clk);
1464 }
1465
1466 static struct platform_driver cdns_i2c_drv = {
1467         .driver = {
1468                 .name  = DRIVER_NAME,
1469                 .of_match_table = cdns_i2c_of_match,
1470                 .pm = &cdns_i2c_dev_pm_ops,
1471         },
1472         .probe  = cdns_i2c_probe,
1473         .remove_new = cdns_i2c_remove,
1474 };
1475
1476 module_platform_driver(cdns_i2c_drv);
1477
1478 MODULE_AUTHOR("Xilinx Inc.");
1479 MODULE_DESCRIPTION("Cadence I2C bus driver");
1480 MODULE_LICENSE("GPL");