drivers/i2c/busses/i2c-brcmstb.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/device.h>
  17 #include <linux/i2c.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sched.h>
  24 #include <linux/slab.h>
  25 #include <linux/version.h>
  26
  27 #define N_DATA_REGS                                     8
  28
  29 /*
  30  * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
  31  * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
  32  * data register whereas STB SoCs use 4 byte per data register transfer,
  33  * account for this difference in total count per transaction and mask to
  34  * use.
  35  */
  36 #define BSC_CNT_REG1_MASK(nb)   (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
  37 #define BSC_CNT_REG1_SHIFT      0
  38
  39 /* BSC CTL register field definitions */
  40 #define BSC_CTL_REG_DTF_MASK                            0x00000003
  41 #define BSC_CTL_REG_SCL_SEL_MASK                        0x00000030
  42 #define BSC_CTL_REG_SCL_SEL_SHIFT                       4
  43 #define BSC_CTL_REG_INT_EN_MASK                         0x00000040
  44 #define BSC_CTL_REG_INT_EN_SHIFT                        6
  45 #define BSC_CTL_REG_DIV_CLK_MASK                        0x00000080
  46
  47 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
  48 #define BSC_IIC_EN_RESTART_MASK                         0x00000040
  49 #define BSC_IIC_EN_NOSTART_MASK                         0x00000020
  50 #define BSC_IIC_EN_NOSTOP_MASK                          0x00000010
  51 #define BSC_IIC_EN_NOACK_MASK                           0x00000004
  52 #define BSC_IIC_EN_INTRP_MASK                           0x00000002
  53 #define BSC_IIC_EN_ENABLE_MASK                          0x00000001
  54
  55 /* BSC_CTLHI control register field definitions */
  56 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK        0x00000080
  57 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK                 0x00000040
  58 #define BSC_CTLHI_REG_IGNORE_ACK_MASK                   0x00000002
  59 #define BSC_CTLHI_REG_WAIT_DIS_MASK                     0x00000001
  60
  61 #define I2C_TIMEOUT                                     100 /* msecs */
  62
  63 /* Condition mask used for non combined transfer */
  64 #define COND_RESTART            BSC_IIC_EN_RESTART_MASK
  65 #define COND_NOSTART            BSC_IIC_EN_NOSTART_MASK
  66 #define COND_NOSTOP             BSC_IIC_EN_NOSTOP_MASK
  67 #define COND_START_STOP         (COND_RESTART | COND_NOSTART | COND_NOSTOP)
  68
  69 /* BSC data transfer direction */
  70 #define DTF_WR_MASK             0x00000000
  71 #define DTF_RD_MASK             0x00000001
  72 /* BSC data transfer direction combined format */
  73 #define DTF_RD_WR_MASK          0x00000002
  74 #define DTF_WR_RD_MASK          0x00000003
  75
  76 #define INT_ENABLE              true
  77 #define INT_DISABLE             false
  78
  79 /* BSC block register map structure to cache fields to be written */
  80 struct bsc_regs {
  81         u32     chip_address;           /* slave address */
  82         u32     data_in[N_DATA_REGS];   /* tx data buffer*/
  83         u32     cnt_reg;                /* rx/tx data length */
  84         u32     ctl_reg;                /* control register */
  85         u32     iic_enable;             /* xfer enable and status */
  86         u32     data_out[N_DATA_REGS];  /* rx data buffer */
  87         u32     ctlhi_reg;              /* more control fields */
  88         u32     scl_param;              /* reserved */
  89 };
  90
  91 struct bsc_clk_param {
  92         u32 hz;
  93         u32 scl_mask;
  94         u32 div_mask;
  95 };
  96
  97 enum bsc_xfer_cmd {
  98         CMD_WR,
  99         CMD_RD,
 100         CMD_WR_NOACK,
 101         CMD_RD_NOACK,
 102 };
 103
 104 static char const *cmd_string[] = {
 105         [CMD_WR] = "WR",
 106         [CMD_RD] = "RD",
 107         [CMD_WR_NOACK] = "WR NOACK",
 108         [CMD_RD_NOACK] = "RD NOACK",
 109 };
 110
 111 enum bus_speeds {
 112         SPD_375K,
 113         SPD_390K,
 114         SPD_187K,
 115         SPD_200K,
 116         SPD_93K,
 117         SPD_97K,
 118         SPD_46K,
 119         SPD_50K
 120 };
 121
 122 static const struct bsc_clk_param bsc_clk[] = {
 123         [SPD_375K] = {
 124                 .hz = 375000,
 125                 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
 126                 .div_mask = 0
 127         },
 128         [SPD_390K] = {
 129                 .hz = 390000,
 130                 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
 131                 .div_mask = 0
 132         },
 133         [SPD_187K] = {
 134                 .hz = 187500,
 135                 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
 136                 .div_mask = 0
 137         },
 138         [SPD_200K] = {
 139                 .hz = 200000,
 140                 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
 141                 .div_mask = 0
 142         },
 143         [SPD_93K]  = {
 144                 .hz = 93750,
 145                 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
 146                 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
 147         },
 148         [SPD_97K]  = {
 149                 .hz = 97500,
 150                 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
 151                 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
 152         },
 153         [SPD_46K]  = {
 154                 .hz = 46875,
 155                 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
 156                 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
 157         },
 158         [SPD_50K]  = {
 159                 .hz = 50000,
 160                 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
 161                 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
 162         }
 163 };
 164
 165 struct brcmstb_i2c_dev {
 166         struct device *device;
 167         void __iomem *base;
 168         int irq;
 169         struct bsc_regs *bsc_regmap;
 170         struct i2c_adapter adapter;
 171         struct completion done;
 172         u32 clk_freq_hz;
 173         int data_regsz;
 174 };
 175
 176 /* register accessors for both be and le cpu arch */
 177 #ifdef CONFIG_CPU_BIG_ENDIAN
 178 #define __bsc_readl(_reg) ioread32be(_reg)
 179 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
 180 #else
 181 #define __bsc_readl(_reg) ioread32(_reg)
 182 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
 183 #endif
 184
 185 #define bsc_readl(_dev, _reg)                                           \
 186         __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
 187
 188 #define bsc_writel(_dev, _val, _reg)                                    \
 189         __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
 190
 191 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
 192 {
 193         return (N_DATA_REGS * dev->data_regsz);
 194 }
 195
 196 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
 197 {
 198         return dev->data_regsz;
 199 }
 200
 201 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
 202                                            bool int_en)
 203 {
 204
 205         if (int_en)
 206                 /* Enable BSC  CTL interrupt line */
 207                 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
 208         else
 209                 /* Disable BSC CTL interrupt line */
 210                 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
 211
 212         barrier();
 213         bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
 214 }
 215
 216 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
 217 {
 218         struct brcmstb_i2c_dev *dev = devid;
 219         u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
 220         u32 status_iic_intrp = bsc_readl(dev, iic_enable);
 221
 222         dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
 223                 status_bsc_ctl, status_iic_intrp);
 224
 225         if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
 226                 return IRQ_NONE;
 227
 228         brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
 229         complete(&dev->done);
 230
 231         dev_dbg(dev->device, "isr handled");
 232         return IRQ_HANDLED;
 233 }
 234
 235 /* Wait for device to be ready */
 236 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
 237 {
 238         unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
 239
 240         while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
 241                 if (time_after(jiffies, timeout))
 242                         return -ETIMEDOUT;
 243                 cpu_relax();
 244         }
 245         return 0;
 246 }
 247
 248 /* i2c xfer completion function, handles both irq and polling mode */
 249 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
 250 {
 251         int ret = 0;
 252         unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
 253
 254         if (dev->irq >= 0) {
 255                 if (!wait_for_completion_timeout(&dev->done, timeout))
 256                         ret = -ETIMEDOUT;
 257         } else {
 258                 /* we are in polling mode */
 259                 u32 bsc_intrp;
 260                 unsigned long time_left = jiffies + timeout;
 261
 262                 do {
 263                         bsc_intrp = bsc_readl(dev, iic_enable) &
 264                                 BSC_IIC_EN_INTRP_MASK;
 265                         if (time_after(jiffies, time_left)) {
 266                                 ret = -ETIMEDOUT;
 267                                 break;
 268                         }
 269                         cpu_relax();
 270                 } while (!bsc_intrp);
 271         }
 272
 273         if (dev->irq < 0 || ret == -ETIMEDOUT)
 274                 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
 275
 276         return ret;
 277 }
 278
 279 /* Set xfer START/STOP conditions for subsequent transfer */
 280 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
 281                                        u32 cond_flag)
 282 {
 283         u32 regval = dev->bsc_regmap->iic_enable;
 284
 285         dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
 286 }
 287
 288 /* Send I2C request check completion */
 289 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
 290                                 enum bsc_xfer_cmd cmd)
 291 {
 292         int rc = 0;
 293         struct bsc_regs *pi2creg = dev->bsc_regmap;
 294
 295         /* Make sure the hardware is ready */
 296         rc = brcmstb_i2c_wait_if_busy(dev);
 297         if (rc < 0)
 298                 return rc;
 299
 300         /* only if we are in interrupt mode */
 301         if (dev->irq >= 0)
 302                 reinit_completion(&dev->done);
 303
 304         /* enable BSC CTL interrupt line */
 305         brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
 306
 307         /* initiate transfer by setting iic_enable */
 308         pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
 309         bsc_writel(dev, pi2creg->iic_enable, iic_enable);
 310
 311         /* Wait for transaction to finish or timeout */
 312         rc = brcmstb_i2c_wait_for_completion(dev);
 313         if (rc) {
 314                 dev_dbg(dev->device, "intr timeout for cmd %s\n",
 315                         cmd_string[cmd]);
 316                 goto cmd_out;
 317         }
 318
 319         if ((cmd == CMD_RD || cmd == CMD_WR) &&
 320             bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
 321                 rc = -EREMOTEIO;
 322                 dev_dbg(dev->device, "controller received NOACK intr for %s\n",
 323                         cmd_string[cmd]);
 324         }
 325
 326 cmd_out:
 327         bsc_writel(dev, 0, cnt_reg);
 328         bsc_writel(dev, 0, iic_enable);
 329
 330         return rc;
 331 }
 332
 333 /* Actual data transfer through the BSC master */
 334 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
 335                                      u8 *buf, unsigned int len,
 336                                      struct i2c_msg *pmsg)
 337 {
 338         int cnt, byte, i, rc;
 339         enum bsc_xfer_cmd cmd;
 340         u32 ctl_reg;
 341         struct bsc_regs *pi2creg = dev->bsc_regmap;
 342         int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
 343         int data_regsz = brcmstb_i2c_get_data_regsz(dev);
 344
 345         /* see if the transaction needs to check NACK conditions */
 346         if (no_ack) {
 347                 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
 348                         : CMD_WR_NOACK;
 349                 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
 350         } else {
 351                 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
 352                 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
 353         }
 354         bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
 355
 356         /* set data transfer direction */
 357         ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
 358         if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
 359                 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
 360         else
 361                 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
 362
 363         /* set the read/write length */
 364         bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
 365                    (len << BSC_CNT_REG1_SHIFT), cnt_reg);
 366
 367         /* Write data into data_in register */
 368
 369         if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
 370                 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
 371                         u32 word = 0;
 372
 373                         for (byte = 0; byte < data_regsz; byte++) {
 374                                 word >>= BITS_PER_BYTE;
 375                                 if ((cnt + byte) < len)
 376                                         word |= buf[cnt + byte] <<
 377                                         (BITS_PER_BYTE * (data_regsz - 1));
 378                         }
 379                         bsc_writel(dev, word, data_in[i]);
 380                 }
 381         }
 382
 383         /* Initiate xfer, the function will return on completion */
 384         rc = brcmstb_send_i2c_cmd(dev, cmd);
 385
 386         if (rc != 0) {
 387                 dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
 388                 return rc;
 389         }
 390
 391         /* Read data from data_out register */
 392         if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
 393                 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
 394                         u32 data = bsc_readl(dev, data_out[i]);
 395
 396                         for (byte = 0; byte < data_regsz &&
 397                                      (byte + cnt) < len; byte++) {
 398                                 buf[cnt + byte] = data & 0xff;
 399                                 data >>= BITS_PER_BYTE;
 400                         }
 401                 }
 402         }
 403
 404         return 0;
 405 }
 406
 407 /* Write a single byte of data to the i2c bus */
 408 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
 409                                        u8 *buf, unsigned int nak_expected)
 410 {
 411         enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
 412
 413         bsc_writel(dev, 1, cnt_reg);
 414         bsc_writel(dev, *buf, data_in);
 415
 416         return brcmstb_send_i2c_cmd(dev, cmd);
 417 }
 418
 419 /* Send i2c address */
 420 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
 421                                struct i2c_msg *msg)
 422 {
 423         unsigned char addr;
 424
 425         if (msg->flags & I2C_M_TEN) {
 426                 /* First byte is 11110XX0 where XX is upper 2 bits */
 427                 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
 428                 bsc_writel(dev, addr, chip_address);
 429
 430                 /* Second byte is the remaining 8 bits */
 431                 addr = msg->addr & 0xFF;
 432                 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
 433                         return -EREMOTEIO;
 434
 435                 if (msg->flags & I2C_M_RD) {
 436                         /* For read, send restart without stop condition */
 437                         brcmstb_set_i2c_start_stop(dev, COND_RESTART
 438                                                    | COND_NOSTOP);
 439                         /* Then re-send the first byte with the read bit set */
 440                         addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
 441                         if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
 442                                 return -EREMOTEIO;
 443
 444                 }
 445         } else {
 446                 addr = i2c_8bit_addr_from_msg(msg);
 447
 448                 bsc_writel(dev, addr, chip_address);
 449         }
 450
 451         return 0;
 452 }
 453
 454 /* Master transfer function */
 455 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
 456                             struct i2c_msg msgs[], int num)
 457 {
 458         struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
 459         struct i2c_msg *pmsg;
 460         int rc = 0;
 461         int i;
 462         int bytes_to_xfer;
 463         u8 *tmp_buf;
 464         int len = 0;
 465         int xfersz = brcmstb_i2c_get_xfersz(dev);
 466         u32 cond, cond_per_msg;
 467
 468         /* Loop through all messages */
 469         for (i = 0; i < num; i++) {
 470                 pmsg = &msgs[i];
 471                 len = pmsg->len;
 472                 tmp_buf = pmsg->buf;
 473
 474                 dev_dbg(dev->device,
 475                         "msg# %d/%d flg %x buf %x len %d\n", i,
 476                         num - 1, pmsg->flags,
 477                         pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
 478
 479                 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
 480                         cond = ~COND_START_STOP;
 481                 else
 482                         cond = COND_RESTART | COND_NOSTOP;
 483
 484                 brcmstb_set_i2c_start_stop(dev, cond);
 485
 486                 /* Send slave address */
 487                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 488                         rc = brcmstb_i2c_do_addr(dev, pmsg);
 489                         if (rc < 0) {
 490                                 dev_dbg(dev->device,
 491                                         "NACK for addr %2.2x msg#%d rc = %d\n",
 492                                         pmsg->addr, i, rc);
 493                                 goto out;
 494                         }
 495                 }
 496
 497                 cond_per_msg = cond;
 498
 499                 /* Perform data transfer */
 500                 while (len) {
 501                         bytes_to_xfer = min(len, xfersz);
 502
 503                         if (len <= xfersz) {
 504                                 if (i == (num - 1))
 505                                         cond_per_msg = cond_per_msg &
 506                                                 ~(COND_RESTART | COND_NOSTOP);
 507                                 else
 508                                         cond_per_msg = cond;
 509                         } else {
 510                                 cond_per_msg = (cond_per_msg & ~COND_RESTART) |
 511                                         COND_NOSTOP;
 512                         }
 513
 514                         brcmstb_set_i2c_start_stop(dev, cond_per_msg);
 515
 516                         rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
 517                                                        bytes_to_xfer, pmsg);
 518                         if (rc < 0)
 519                                 goto out;
 520
 521                         len -=  bytes_to_xfer;
 522                         tmp_buf += bytes_to_xfer;
 523
 524                         cond_per_msg = COND_NOSTART | COND_NOSTOP;
 525                 }
 526         }
 527
 528         rc = num;
 529 out:
 530         return rc;
 531
 532 }
 533
 534 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
 535 {
 536         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
 537                 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
 538 }
 539
 540 static const struct i2c_algorithm brcmstb_i2c_algo = {
 541         .master_xfer = brcmstb_i2c_xfer,
 542         .functionality = brcmstb_i2c_functionality,
 543 };
 544
 545 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
 546 {
 547         int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
 548         u32 clk_freq_hz = dev->clk_freq_hz;
 549
 550         for (i = 0; i < num_speeds; i++) {
 551                 if (bsc_clk[i].hz == clk_freq_hz) {
 552                         dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
 553                                                 | BSC_CTL_REG_DIV_CLK_MASK);
 554                         dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
 555                                                      bsc_clk[i].div_mask);
 556                         bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
 557                         break;
 558                 }
 559         }
 560
 561         /* in case we did not get find a valid speed */
 562         if (i == num_speeds) {
 563                 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
 564                         BSC_CTL_REG_SCL_SEL_SHIFT;
 565                 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
 566                         bsc_clk[i].hz);
 567         }
 568 }
 569
 570 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
 571 {
 572         if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
 573                 /* set 4 byte data in/out xfers  */
 574                 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
 575         else
 576                 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
 577
 578         bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
 579         /* set bus speed */
 580         brcmstb_i2c_set_bus_speed(dev);
 581 }
 582
 583 #define AUTOI2C_CTRL0           0x26c
 584 #define AUTOI2C_CTRL0_RELEASE_BSC       BIT(1)
 585
 586 static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev)
 587 {
 588         struct platform_device *pdev = to_platform_device(dev->device);
 589         struct resource *iomem;
 590         void __iomem *autoi2c;
 591
 592         /* Map hardware registers */
 593         iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "auto-i2c");
 594         autoi2c = devm_ioremap_resource(&pdev->dev, iomem);
 595         if (IS_ERR(autoi2c))
 596                 return PTR_ERR(autoi2c);
 597
 598         writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0);
 599         devm_iounmap(&pdev->dev, autoi2c);
 600
 601         /* We need to reset the controller after the release */
 602         dev->bsc_regmap->iic_enable = 0;
 603         bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable);
 604
 605         return 0;
 606 }
 607
 608 static int brcmstb_i2c_probe(struct platform_device *pdev)
 609 {
 610         int rc = 0;
 611         struct brcmstb_i2c_dev *dev;
 612         struct i2c_adapter *adap;
 613         struct resource *iomem;
 614         const char *int_name;
 615
 616         /* Allocate memory for private data structure */
 617         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 618         if (!dev)
 619                 return -ENOMEM;
 620
 621         dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
 622         if (!dev->bsc_regmap)
 623                 return -ENOMEM;
 624
 625         platform_set_drvdata(pdev, dev);
 626         dev->device = &pdev->dev;
 627         init_completion(&dev->done);
 628
 629         /* Map hardware registers */
 630         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 631         dev->base = devm_ioremap_resource(dev->device, iomem);
 632         if (IS_ERR(dev->base)) {
 633                 rc = -ENOMEM;
 634                 goto probe_errorout;
 635         }
 636
 637         if (of_device_is_compatible(dev->device->of_node,
 638                                     "brcm,bcm2711-hdmi-i2c")) {
 639                 rc = bcm2711_release_bsc(dev);
 640                 if (rc)
 641                         goto probe_errorout;
 642         }
 643
 644         rc = of_property_read_string(dev->device->of_node, "interrupt-names",
 645                                      &int_name);
 646         if (rc < 0)
 647                 int_name = NULL;
 648
 649         /* Get the interrupt number */
 650         dev->irq = platform_get_irq_optional(pdev, 0);
 651
 652         /* disable the bsc interrupt line */
 653         brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
 654
 655         /* register the ISR handler */
 656         if (dev->irq >= 0) {
 657                 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
 658                                       IRQF_SHARED,
 659                                       int_name ? int_name : pdev->name,
 660                                       dev);
 661
 662                 if (rc) {
 663                         dev_dbg(dev->device, "falling back to polling mode");
 664                         dev->irq = -1;
 665                 }
 666         }
 667
 668         if (of_property_read_u32(dev->device->of_node,
 669                                  "clock-frequency", &dev->clk_freq_hz)) {
 670                 dev_warn(dev->device, "setting clock-frequency@%dHz\n",
 671                          bsc_clk[0].hz);
 672                 dev->clk_freq_hz = bsc_clk[0].hz;
 673         }
 674
 675         /* set the data in/out register size for compatible SoCs */
 676         if (of_device_is_compatible(dev->device->of_node,
 677                                     "brcm,brcmper-i2c"))
 678                 dev->data_regsz = sizeof(u8);
 679         else
 680                 dev->data_regsz = sizeof(u32);
 681
 682         brcmstb_i2c_set_bsc_reg_defaults(dev);
 683
 684         /* Add the i2c adapter */
 685         adap = &dev->adapter;
 686         i2c_set_adapdata(adap, dev);
 687         adap->owner = THIS_MODULE;
 688         strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name));
 689         if (int_name)
 690                 strlcat(adap->name, int_name, sizeof(adap->name));
 691         adap->algo = &brcmstb_i2c_algo;
 692         adap->dev.parent = &pdev->dev;
 693         adap->dev.of_node = pdev->dev.of_node;
 694         rc = i2c_add_adapter(adap);
 695         if (rc)
 696                 goto probe_errorout;
 697
 698         dev_info(dev->device, "%s@%dhz registered in %s mode\n",
 699                  int_name ? int_name : " ", dev->clk_freq_hz,
 700                  (dev->irq >= 0) ? "interrupt" : "polling");
 701
 702         return 0;
 703
 704 probe_errorout:
 705         return rc;
 706 }
 707
 708 static int brcmstb_i2c_remove(struct platform_device *pdev)
 709 {
 710         struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
 711
 712         i2c_del_adapter(&dev->adapter);
 713         return 0;
 714 }
 715
 716 #ifdef CONFIG_PM_SLEEP
 717 static int brcmstb_i2c_suspend(struct device *dev)
 718 {
 719         struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 720
 721         i2c_mark_adapter_suspended(&i2c_dev->adapter);
 722         return 0;
 723 }
 724
 725 static int brcmstb_i2c_resume(struct device *dev)
 726 {
 727         struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 728
 729         brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
 730         i2c_mark_adapter_resumed(&i2c_dev->adapter);
 731
 732         return 0;
 733 }
 734 #endif
 735
 736 static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
 737                          brcmstb_i2c_resume);
 738
 739 static const struct of_device_id brcmstb_i2c_of_match[] = {
 740         {.compatible = "brcm,brcmstb-i2c"},
 741         {.compatible = "brcm,brcmper-i2c"},
 742         {.compatible = "brcm,bcm2711-hdmi-i2c"},
 743         {},
 744 };
 745 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
 746
 747 static struct platform_driver brcmstb_i2c_driver = {
 748         .driver = {
 749                    .name = "brcmstb-i2c",
 750                    .of_match_table = brcmstb_i2c_of_match,
 751                    .pm = &brcmstb_i2c_pm,
 752                    },
 753         .probe = brcmstb_i2c_probe,
 754         .remove = brcmstb_i2c_remove,
 755 };
 756 module_platform_driver(brcmstb_i2c_driver);
 757
 758 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
 759 MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
 760 MODULE_LICENSE("GPL v2");