1 // SPDX-License-Identifier: GPL-2.0
3 * BCM2835 master mode driver
7 #include <linux/clkdev.h>
8 #include <linux/clk-provider.h>
9 #include <linux/completion.h>
10 #include <linux/err.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #define BCM2835_I2C_C 0x0
20 #define BCM2835_I2C_S 0x4
21 #define BCM2835_I2C_DLEN 0x8
22 #define BCM2835_I2C_A 0xc
23 #define BCM2835_I2C_FIFO 0x10
24 #define BCM2835_I2C_DIV 0x14
25 #define BCM2835_I2C_DEL 0x18
27 * 16-bit field for the number of SCL cycles to wait after rising SCL
28 * before deciding the slave is not responding. 0 disables the
31 #define BCM2835_I2C_CLKT 0x1c
33 #define BCM2835_I2C_C_READ BIT(0)
34 #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */
35 #define BCM2835_I2C_C_ST BIT(7)
36 #define BCM2835_I2C_C_INTD BIT(8)
37 #define BCM2835_I2C_C_INTT BIT(9)
38 #define BCM2835_I2C_C_INTR BIT(10)
39 #define BCM2835_I2C_C_I2CEN BIT(15)
41 #define BCM2835_I2C_S_TA BIT(0)
42 #define BCM2835_I2C_S_DONE BIT(1)
43 #define BCM2835_I2C_S_TXW BIT(2)
44 #define BCM2835_I2C_S_RXR BIT(3)
45 #define BCM2835_I2C_S_TXD BIT(4)
46 #define BCM2835_I2C_S_RXD BIT(5)
47 #define BCM2835_I2C_S_TXE BIT(6)
48 #define BCM2835_I2C_S_RXF BIT(7)
49 #define BCM2835_I2C_S_ERR BIT(8)
50 #define BCM2835_I2C_S_CLKT BIT(9)
51 #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
53 #define BCM2835_I2C_FEDL_SHIFT 16
54 #define BCM2835_I2C_REDL_SHIFT 0
56 #define BCM2835_I2C_CDIV_MIN 0x0002
57 #define BCM2835_I2C_CDIV_MAX 0xFFFE
59 struct bcm2835_i2c_dev {
63 struct i2c_adapter adapter;
64 struct completion completion;
65 struct i2c_msg *curr_msg;
70 size_t msg_buf_remaining;
73 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
76 writel(val, i2c_dev->regs + reg);
79 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
81 return readl(i2c_dev->regs + reg);
84 #define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
85 struct clk_bcm2835_i2c {
87 struct bcm2835_i2c_dev *i2c_dev;
90 static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
91 unsigned long parent_rate)
93 u32 divider = DIV_ROUND_UP(parent_rate, rate);
96 * Per the datasheet, the register is always interpreted as an even
97 * number, by rounding down. In other words, the LSB is ignored. So,
98 * if the LSB is set, increment the divider to avoid any issue.
102 if ((divider < BCM2835_I2C_CDIV_MIN) ||
103 (divider > BCM2835_I2C_CDIV_MAX))
109 static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
110 unsigned long parent_rate)
112 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
116 if (divider == -EINVAL)
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
122 * Number of core clocks to wait after falling edge before
123 * outputting the next data bit. Note that both FEDL and REDL
124 * can't be greater than CDIV/2.
126 fedl = max(divider / 16, 1u);
129 * Number of core clocks to wait after rising edge before
130 * sampling the next incoming data bit.
132 redl = max(divider / 4, 1u);
134 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
135 (fedl << BCM2835_I2C_FEDL_SHIFT) |
136 (redl << BCM2835_I2C_REDL_SHIFT));
140 static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
141 unsigned long *parent_rate)
143 u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
145 return DIV_ROUND_UP(*parent_rate, divider);
148 static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
149 unsigned long parent_rate)
151 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
152 u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
154 return DIV_ROUND_UP(parent_rate, divider);
157 static const struct clk_ops clk_bcm2835_i2c_ops = {
158 .set_rate = clk_bcm2835_i2c_set_rate,
159 .round_rate = clk_bcm2835_i2c_round_rate,
160 .recalc_rate = clk_bcm2835_i2c_recalc_rate,
163 static struct clk *bcm2835_i2c_register_div(struct device *dev,
165 struct bcm2835_i2c_dev *i2c_dev)
167 struct clk_init_data init;
168 struct clk_bcm2835_i2c *priv;
170 const char *mclk_name;
172 snprintf(name, sizeof(name), "%s_div", dev_name(dev));
174 mclk_name = __clk_get_name(mclk);
176 init.ops = &clk_bcm2835_i2c_ops;
178 init.parent_names = (const char* []) { mclk_name };
179 init.num_parents = 1;
182 priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
184 return ERR_PTR(-ENOMEM);
186 priv->hw.init = &init;
187 priv->i2c_dev = i2c_dev;
189 clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
190 return devm_clk_register(dev, &priv->hw);
193 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
197 while (i2c_dev->msg_buf_remaining) {
198 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
199 if (!(val & BCM2835_I2C_S_TXD))
201 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
204 i2c_dev->msg_buf_remaining--;
208 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
212 while (i2c_dev->msg_buf_remaining) {
213 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
214 if (!(val & BCM2835_I2C_S_RXD))
216 *i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
219 i2c_dev->msg_buf_remaining--;
224 * Repeated Start Condition (Sr)
225 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
226 * talks about reading from a slave with 10 bit address. This is achieved by
227 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
229 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
230 * firmware actually does it using polling and says that it's a workaround for
231 * a problem in the state machine.
232 * It turns out that it is possible to use the TXW interrupt to know when the
233 * transfer is active, provided the FIFO has not been prefilled.
236 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
238 u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
239 struct i2c_msg *msg = i2c_dev->curr_msg;
240 bool last_msg = (i2c_dev->num_msgs == 1);
242 if (!i2c_dev->num_msgs)
246 i2c_dev->msg_buf = msg->buf;
247 i2c_dev->msg_buf_remaining = msg->len;
249 if (msg->flags & I2C_M_RD)
250 c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
252 c |= BCM2835_I2C_C_INTT;
255 c |= BCM2835_I2C_C_INTD;
257 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
258 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
259 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
262 static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
264 i2c_dev->curr_msg = NULL;
265 i2c_dev->num_msgs = 0;
267 i2c_dev->msg_buf = NULL;
268 i2c_dev->msg_buf_remaining = 0;
272 * Note about I2C_C_CLEAR on error:
273 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
274 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
275 * the state machine to send a NACK and a STOP. Since we're setting CLEAR
276 * without I2CEN, that NACK will be hanging around queued up for next time
277 * we start the engine.
280 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
282 struct bcm2835_i2c_dev *i2c_dev = data;
285 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
287 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
289 i2c_dev->msg_err = err;
293 if (val & BCM2835_I2C_S_DONE) {
294 if (!i2c_dev->curr_msg) {
295 dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
296 } else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
297 bcm2835_drain_rxfifo(i2c_dev);
298 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
301 if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
302 i2c_dev->msg_err = BCM2835_I2C_S_LEN;
304 i2c_dev->msg_err = 0;
308 if (val & BCM2835_I2C_S_TXW) {
309 if (!i2c_dev->msg_buf_remaining) {
310 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
314 bcm2835_fill_txfifo(i2c_dev);
316 if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
318 bcm2835_i2c_start_transfer(i2c_dev);
324 if (val & BCM2835_I2C_S_RXR) {
325 if (!i2c_dev->msg_buf_remaining) {
326 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
330 bcm2835_drain_rxfifo(i2c_dev);
337 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
338 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
339 BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
340 complete(&i2c_dev->completion);
345 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
348 struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
349 unsigned long time_left;
352 for (i = 0; i < (num - 1); i++)
353 if (msgs[i].flags & I2C_M_RD) {
354 dev_warn_once(i2c_dev->dev,
355 "only one read message supported, has to be last\n");
359 i2c_dev->curr_msg = msgs;
360 i2c_dev->num_msgs = num;
361 reinit_completion(&i2c_dev->completion);
363 bcm2835_i2c_start_transfer(i2c_dev);
365 time_left = wait_for_completion_timeout(&i2c_dev->completion,
368 bcm2835_i2c_finish_transfer(i2c_dev);
371 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
372 BCM2835_I2C_C_CLEAR);
373 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
377 if (!i2c_dev->msg_err)
380 dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
382 if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
388 static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
390 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
393 static const struct i2c_algorithm bcm2835_i2c_algo = {
394 .master_xfer = bcm2835_i2c_xfer,
395 .functionality = bcm2835_i2c_func,
399 * The BCM2835 was reported to have problems with clock stretching:
400 * https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
401 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
403 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
404 .flags = I2C_AQ_NO_CLK_STRETCH,
407 static int bcm2835_i2c_probe(struct platform_device *pdev)
409 struct bcm2835_i2c_dev *i2c_dev;
410 struct resource *mem, *irq;
412 struct i2c_adapter *adap;
416 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
419 platform_set_drvdata(pdev, i2c_dev);
420 i2c_dev->dev = &pdev->dev;
421 init_completion(&i2c_dev->completion);
423 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
424 i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
425 if (IS_ERR(i2c_dev->regs))
426 return PTR_ERR(i2c_dev->regs);
428 mclk = devm_clk_get(&pdev->dev, NULL);
430 return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
431 "Could not get clock\n");
433 i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
435 if (IS_ERR(i2c_dev->bus_clk)) {
436 dev_err(&pdev->dev, "Could not register clock\n");
437 return PTR_ERR(i2c_dev->bus_clk);
440 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
444 "Could not read clock-frequency property\n");
445 bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
448 ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
450 dev_err(&pdev->dev, "Could not set clock frequency\n");
454 ret = clk_prepare_enable(i2c_dev->bus_clk);
456 dev_err(&pdev->dev, "Couldn't prepare clock");
460 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
462 dev_err(&pdev->dev, "No IRQ resource\n");
465 i2c_dev->irq = irq->start;
467 ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
468 dev_name(&pdev->dev), i2c_dev);
470 dev_err(&pdev->dev, "Could not request IRQ\n");
474 adap = &i2c_dev->adapter;
475 i2c_set_adapdata(adap, i2c_dev);
476 adap->owner = THIS_MODULE;
477 adap->class = I2C_CLASS_DEPRECATED;
478 snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
479 of_node_full_name(pdev->dev.of_node));
480 adap->algo = &bcm2835_i2c_algo;
481 adap->dev.parent = &pdev->dev;
482 adap->dev.of_node = pdev->dev.of_node;
483 adap->quirks = of_device_get_match_data(&pdev->dev);
486 * Disable the hardware clock stretching timeout. SMBUS
487 * specifies a limit for how long the device can stretch the
488 * clock, but core I2C doesn't.
490 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
491 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
493 ret = i2c_add_adapter(adap);
495 free_irq(i2c_dev->irq, i2c_dev);
500 static int bcm2835_i2c_remove(struct platform_device *pdev)
502 struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
504 clk_rate_exclusive_put(i2c_dev->bus_clk);
505 clk_disable_unprepare(i2c_dev->bus_clk);
507 free_irq(i2c_dev->irq, i2c_dev);
508 i2c_del_adapter(&i2c_dev->adapter);
513 static const struct of_device_id bcm2835_i2c_of_match[] = {
514 { .compatible = "brcm,bcm2711-i2c" },
515 { .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
518 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
520 static struct platform_driver bcm2835_i2c_driver = {
521 .probe = bcm2835_i2c_probe,
522 .remove = bcm2835_i2c_remove,
524 .name = "i2c-bcm2835",
525 .of_match_table = bcm2835_i2c_of_match,
528 module_platform_driver(bcm2835_i2c_driver);
530 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
531 MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
532 MODULE_LICENSE("GPL v2");
533 MODULE_ALIAS("platform:i2c-bcm2835");