drivers/i2c/busses/i2c-bcm-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define IDM_CTRL_DIRECT_OFFSET       0x00
  25 #define CFG_OFFSET                   0x00
  26 #define CFG_RESET_SHIFT              31
  27 #define CFG_EN_SHIFT                 30
  28 #define CFG_SLAVE_ADDR_0_SHIFT       28
  29 #define CFG_M_RETRY_CNT_SHIFT        16
  30 #define CFG_M_RETRY_CNT_MASK         0x0f
  31
  32 #define TIM_CFG_OFFSET               0x04
  33 #define TIM_CFG_MODE_400_SHIFT       31
  34 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  35 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  38
  39 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  41 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  42 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  44 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  45 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  47 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  48 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  50 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  51 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  52
  53 #define M_FIFO_CTRL_OFFSET           0x0c
  54 #define M_FIFO_RX_FLUSH_SHIFT        31
  55 #define M_FIFO_TX_FLUSH_SHIFT        30
  56 #define M_FIFO_RX_CNT_SHIFT          16
  57 #define M_FIFO_RX_CNT_MASK           0x7f
  58 #define M_FIFO_RX_THLD_SHIFT         8
  59 #define M_FIFO_RX_THLD_MASK          0x3f
  60
  61 #define S_FIFO_CTRL_OFFSET           0x10
  62 #define S_FIFO_RX_FLUSH_SHIFT        31
  63 #define S_FIFO_TX_FLUSH_SHIFT        30
  64 #define S_FIFO_RX_CNT_SHIFT          16
  65 #define S_FIFO_RX_CNT_MASK           0x7f
  66 #define S_FIFO_RX_THLD_SHIFT         8
  67 #define S_FIFO_RX_THLD_MASK          0x3f
  68
  69 #define M_CMD_OFFSET                 0x30
  70 #define M_CMD_START_BUSY_SHIFT       31
  71 #define M_CMD_STATUS_SHIFT           25
  72 #define M_CMD_STATUS_MASK            0x07
  73 #define M_CMD_STATUS_SUCCESS         0x0
  74 #define M_CMD_STATUS_LOST_ARB        0x1
  75 #define M_CMD_STATUS_NACK_ADDR       0x2
  76 #define M_CMD_STATUS_NACK_DATA       0x3
  77 #define M_CMD_STATUS_TIMEOUT         0x4
  78 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  79 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  80 #define M_CMD_PROTOCOL_SHIFT         9
  81 #define M_CMD_PROTOCOL_MASK          0xf
  82 #define M_CMD_PROTOCOL_QUICK         0x0
  83 #define M_CMD_PROTOCOL_BLK_WR        0x7
  84 #define M_CMD_PROTOCOL_BLK_RD        0x8
  85 #define M_CMD_PROTOCOL_PROCESS       0xa
  86 #define M_CMD_PEC_SHIFT              8
  87 #define M_CMD_RD_CNT_SHIFT           0
  88 #define M_CMD_RD_CNT_MASK            0xff
  89
  90 #define S_CMD_OFFSET                 0x34
  91 #define S_CMD_START_BUSY_SHIFT       31
  92 #define S_CMD_STATUS_SHIFT           23
  93 #define S_CMD_STATUS_MASK            0x07
  94 #define S_CMD_STATUS_SUCCESS         0x0
  95 #define S_CMD_STATUS_TIMEOUT         0x5
  96
  97 #define IE_OFFSET                    0x38
  98 #define IE_M_RX_FIFO_FULL_SHIFT      31
  99 #define IE_M_RX_THLD_SHIFT           30
 100 #define IE_M_START_BUSY_SHIFT        28
 101 #define IE_M_TX_UNDERRUN_SHIFT       27
 102 #define IE_S_RX_FIFO_FULL_SHIFT      26
 103 #define IE_S_RX_THLD_SHIFT           25
 104 #define IE_S_RX_EVENT_SHIFT          24
 105 #define IE_S_START_BUSY_SHIFT        23
 106 #define IE_S_TX_UNDERRUN_SHIFT       22
 107 #define IE_S_RD_EVENT_SHIFT          21
 108
 109 #define IS_OFFSET                    0x3c
 110 #define IS_M_RX_FIFO_FULL_SHIFT      31
 111 #define IS_M_RX_THLD_SHIFT           30
 112 #define IS_M_START_BUSY_SHIFT        28
 113 #define IS_M_TX_UNDERRUN_SHIFT       27
 114 #define IS_S_RX_FIFO_FULL_SHIFT      26
 115 #define IS_S_RX_THLD_SHIFT           25
 116 #define IS_S_RX_EVENT_SHIFT          24
 117 #define IS_S_START_BUSY_SHIFT        23
 118 #define IS_S_TX_UNDERRUN_SHIFT       22
 119 #define IS_S_RD_EVENT_SHIFT          21
 120
 121 #define M_TX_OFFSET                  0x40
 122 #define M_TX_WR_STATUS_SHIFT         31
 123 #define M_TX_DATA_SHIFT              0
 124 #define M_TX_DATA_MASK               0xff
 125
 126 #define M_RX_OFFSET                  0x44
 127 #define M_RX_STATUS_SHIFT            30
 128 #define M_RX_STATUS_MASK             0x03
 129 #define M_RX_PEC_ERR_SHIFT           29
 130 #define M_RX_DATA_SHIFT              0
 131 #define M_RX_DATA_MASK               0xff
 132
 133 #define S_TX_OFFSET                  0x48
 134 #define S_TX_WR_STATUS_SHIFT         31
 135 #define S_TX_DATA_SHIFT              0
 136 #define S_TX_DATA_MASK               0xff
 137
 138 #define S_RX_OFFSET                  0x4c
 139 #define S_RX_STATUS_SHIFT            30
 140 #define S_RX_STATUS_MASK             0x03
 141 #define S_RX_PEC_ERR_SHIFT           29
 142 #define S_RX_DATA_SHIFT              0
 143 #define S_RX_DATA_MASK               0xff
 144
 145 #define I2C_TIMEOUT_MSEC             50000
 146 #define M_TX_RX_FIFO_SIZE            64
 147 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 148
 149 #define M_RX_MAX_READ_LEN            255
 150 #define M_RX_FIFO_THLD_VALUE         50
 151
 152 #define IE_M_ALL_INTERRUPT_SHIFT     27
 153 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 154
 155 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 156 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 157 #define SLAVE_MAX_SIZE_TRANSACTION   64
 158 #define SLAVE_CLOCK_STRETCH_TIME     25
 159
 160 #define IE_S_ALL_INTERRUPT_SHIFT     21
 161 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 162 /*
 163  * It takes ~18us to reading 10bytes of data, hence to keep tasklet
 164  * running for less time, max slave read per tasklet is set to 10 bytes.
 165  */
 166 #define MAX_SLAVE_RX_PER_INT         10
 167
 168 enum i2c_slave_read_status {
 169         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 170         I2C_SLAVE_RX_START,
 171         I2C_SLAVE_RX_DATA,
 172         I2C_SLAVE_RX_END,
 173 };
 174
 175 enum bus_speed_index {
 176         I2C_SPD_100K = 0,
 177         I2C_SPD_400K,
 178 };
 179
 180 enum bcm_iproc_i2c_type {
 181         IPROC_I2C,
 182         IPROC_I2C_NIC
 183 };
 184
 185 struct bcm_iproc_i2c_dev {
 186         struct device *device;
 187         enum bcm_iproc_i2c_type type;
 188         int irq;
 189
 190         void __iomem *base;
 191         void __iomem *idm_base;
 192
 193         u32 ape_addr_mask;
 194
 195         /* lock for indirect access through IDM */
 196         spinlock_t idm_lock;
 197
 198         struct i2c_adapter adapter;
 199         unsigned int bus_speed;
 200
 201         struct completion done;
 202         int xfer_is_done;
 203
 204         struct i2c_msg *msg;
 205
 206         struct i2c_client *slave;
 207
 208         /* bytes that have been transferred */
 209         unsigned int tx_bytes;
 210         /* bytes that have been read */
 211         unsigned int rx_bytes;
 212         unsigned int thld_bytes;
 213
 214         bool slave_rx_only;
 215         bool rx_start_rcvd;
 216         bool slave_read_complete;
 217         u32 tx_underrun;
 218         u32 slave_int_mask;
 219         struct tasklet_struct slave_rx_tasklet;
 220 };
 221
 222 /* tasklet to process slave rx data */
 223 static void slave_rx_tasklet_fn(unsigned long);
 224
 225 /*
 226  * Can be expanded in the future if more interrupt status bits are utilized
 227  */
 228 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 229                 | BIT(IS_M_RX_THLD_SHIFT))
 230
 231 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 232                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 233                 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
 234                 | BIT(IS_S_RX_THLD_SHIFT))
 235
 236 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 237 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 238 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 239                                          bool enable);
 240
 241 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 242                                    u32 offset)
 243 {
 244         u32 val;
 245         unsigned long flags;
 246
 247         if (iproc_i2c->idm_base) {
 248                 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
 249                 writel(iproc_i2c->ape_addr_mask,
 250                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 251                 val = readl(iproc_i2c->base + offset);
 252                 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);
 253         } else {
 254                 val = readl(iproc_i2c->base + offset);
 255         }
 256
 257         return val;
 258 }
 259
 260 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 261                                     u32 offset, u32 val)
 262 {
 263         unsigned long flags;
 264
 265         if (iproc_i2c->idm_base) {
 266                 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
 267                 writel(iproc_i2c->ape_addr_mask,
 268                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 269                 writel(val, iproc_i2c->base + offset);
 270                 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);
 271         } else {
 272                 writel(val, iproc_i2c->base + offset);
 273         }
 274 }
 275
 276 static void bcm_iproc_i2c_slave_init(
 277         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 278 {
 279         u32 val;
 280
 281         iproc_i2c->tx_underrun = 0;
 282         if (need_reset) {
 283                 /* put controller in reset */
 284                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 285                 val |= BIT(CFG_RESET_SHIFT);
 286                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 287
 288                 /* wait 100 usec per spec */
 289                 udelay(100);
 290
 291                 /* bring controller out of reset */
 292                 val &= ~(BIT(CFG_RESET_SHIFT));
 293                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 294         }
 295
 296         /* flush TX/RX FIFOs */
 297         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 298         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 299
 300         /* Maximum slave stretch time */
 301         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 302         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 303         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 304         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 305
 306         /* Configure the slave address */
 307         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 308         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 309         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 310         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 311         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 312
 313         /* clear all pending slave interrupts */
 314         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 315
 316         /* Enable interrupt register to indicate a valid byte in receive fifo */
 317         val = BIT(IE_S_RX_EVENT_SHIFT);
 318         /* Enable interrupt register to indicate a Master read transaction */
 319         val |= BIT(IE_S_RD_EVENT_SHIFT);
 320         /* Enable interrupt register for the Slave BUSY command */
 321         val |= BIT(IE_S_START_BUSY_SHIFT);
 322         iproc_i2c->slave_int_mask = val;
 323         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 324 }
 325
 326 static void bcm_iproc_i2c_check_slave_status(
 327         struct bcm_iproc_i2c_dev *iproc_i2c)
 328 {
 329         u32 val;
 330
 331         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 332         /* status is valid only when START_BUSY is cleared after it was set */
 333         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 334                 return;
 335
 336         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 337         if (val == S_CMD_STATUS_TIMEOUT) {
 338                 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
 339
 340                 /* re-initialize i2c for recovery */
 341                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 342                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 343                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 344         }
 345 }
 346
 347 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 348 {
 349         u8 rx_data, rx_status;
 350         u32 rx_bytes = 0;
 351         u32 val;
 352
 353         while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
 354                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 355                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 356                 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 357
 358                 if (rx_status == I2C_SLAVE_RX_START) {
 359                         /* Start of SMBUS Master write */
 360                         i2c_slave_event(iproc_i2c->slave,
 361                                         I2C_SLAVE_WRITE_REQUESTED, &rx_data);
 362                         iproc_i2c->rx_start_rcvd = true;
 363                         iproc_i2c->slave_read_complete = false;
 364                 } else if (rx_status == I2C_SLAVE_RX_DATA &&
 365                            iproc_i2c->rx_start_rcvd) {
 366                         /* Middle of SMBUS Master write */
 367                         i2c_slave_event(iproc_i2c->slave,
 368                                         I2C_SLAVE_WRITE_RECEIVED, &rx_data);
 369                 } else if (rx_status == I2C_SLAVE_RX_END &&
 370                            iproc_i2c->rx_start_rcvd) {
 371                         /* End of SMBUS Master write */
 372                         if (iproc_i2c->slave_rx_only)
 373                                 i2c_slave_event(iproc_i2c->slave,
 374                                                 I2C_SLAVE_WRITE_RECEIVED,
 375                                                 &rx_data);
 376
 377                         i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
 378                                         &rx_data);
 379                 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
 380                         iproc_i2c->rx_start_rcvd = false;
 381                         iproc_i2c->slave_read_complete = true;
 382                         break;
 383                 }
 384
 385                 rx_bytes++;
 386         }
 387 }
 388
 389 static void slave_rx_tasklet_fn(unsigned long data)
 390 {
 391         struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
 392         u32 int_clr;
 393
 394         bcm_iproc_i2c_slave_read(iproc_i2c);
 395
 396         /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
 397         int_clr = BIT(IS_S_RX_EVENT_SHIFT);
 398
 399         if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
 400                 /*
 401                  * In case of single byte master-read request,
 402                  * IS_S_TX_UNDERRUN_SHIFT event is generated before
 403                  * IS_S_START_BUSY_SHIFT event. Hence start slave data send
 404                  * from first IS_S_TX_UNDERRUN_SHIFT event.
 405                  *
 406                  * This means don't send any data from slave when
 407                  * IS_S_RD_EVENT_SHIFT event is generated else it will increment
 408                  * eeprom or other backend slave driver read pointer twice.
 409                  */
 410                 iproc_i2c->tx_underrun = 0;
 411                 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 412
 413                 /* clear IS_S_RD_EVENT_SHIFT interrupt */
 414                 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
 415         }
 416
 417         /* clear slave interrupt */
 418         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
 419         /* enable slave interrupts */
 420         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
 421 }
 422
 423 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 424                                     u32 status)
 425 {
 426         u32 val;
 427         u8 value;
 428
 429         /*
 430          * Slave events in case of master-write, master-write-read and,
 431          * master-read
 432          *
 433          * Master-write     : only IS_S_RX_EVENT_SHIFT event
 434          * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
 435          *                    events
 436          * Master-read      : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
 437          *                    events or only IS_S_RD_EVENT_SHIFT
 438          */
 439         if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
 440             status & BIT(IS_S_RD_EVENT_SHIFT)) {
 441                 /* disable slave interrupts */
 442                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 443                 val &= ~iproc_i2c->slave_int_mask;
 444                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 445
 446                 if (status & BIT(IS_S_RD_EVENT_SHIFT))
 447                         /* Master-write-read request */
 448                         iproc_i2c->slave_rx_only = false;
 449                 else
 450                         /* Master-write request only */
 451                         iproc_i2c->slave_rx_only = true;
 452
 453                 /* schedule tasklet to read data later */
 454                 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
 455
 456                 /* clear only IS_S_RX_EVENT_SHIFT interrupt */
 457                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 458                                  BIT(IS_S_RX_EVENT_SHIFT));
 459         }
 460
 461         if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 462                 iproc_i2c->tx_underrun++;
 463                 if (iproc_i2c->tx_underrun == 1)
 464                         /* Start of SMBUS for Master Read */
 465                         i2c_slave_event(iproc_i2c->slave,
 466                                         I2C_SLAVE_READ_REQUESTED,
 467                                         &value);
 468                 else
 469                         /* Master read other than start */
 470                         i2c_slave_event(iproc_i2c->slave,
 471                                         I2C_SLAVE_READ_PROCESSED,
 472                                         &value);
 473
 474                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 475                 /* start transfer */
 476                 val = BIT(S_CMD_START_BUSY_SHIFT);
 477                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 478
 479                 /* clear interrupt */
 480                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 481                                  BIT(IS_S_TX_UNDERRUN_SHIFT));
 482         }
 483
 484         /* Stop received from master in case of master read transaction */
 485         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 486                 /*
 487                  * Enable interrupt for TX FIFO becomes empty and
 488                  * less than PKT_LENGTH bytes were output on the SMBUS
 489                  */
 490                 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 491                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 492                                  iproc_i2c->slave_int_mask);
 493
 494                 /* End of SMBUS for Master Read */
 495                 val = BIT(S_TX_WR_STATUS_SHIFT);
 496                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
 497
 498                 val = BIT(S_CMD_START_BUSY_SHIFT);
 499                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 500
 501                 /* flush TX FIFOs */
 502                 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
 503                 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
 504                 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 505
 506                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 507
 508                 /* clear interrupt */
 509                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 510                                  BIT(IS_S_START_BUSY_SHIFT));
 511         }
 512
 513         /* check slave transmit status only if slave is transmitting */
 514         if (!iproc_i2c->slave_rx_only)
 515                 bcm_iproc_i2c_check_slave_status(iproc_i2c);
 516
 517         return true;
 518 }
 519
 520 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 521 {
 522         struct i2c_msg *msg = iproc_i2c->msg;
 523         uint32_t val;
 524
 525         /* Read valid data from RX FIFO */
 526         while (iproc_i2c->rx_bytes < msg->len) {
 527                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 528
 529                 /* rx fifo empty */
 530                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 531                         break;
 532
 533                 msg->buf[iproc_i2c->rx_bytes] =
 534                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 535                 iproc_i2c->rx_bytes++;
 536         }
 537 }
 538
 539 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 540 {
 541         struct i2c_msg *msg = iproc_i2c->msg;
 542         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 543         unsigned int i;
 544         u32 val;
 545
 546         /* can only fill up to the FIFO size */
 547         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 548         for (i = 0; i < tx_bytes; i++) {
 549                 /* start from where we left over */
 550                 unsigned int idx = iproc_i2c->tx_bytes + i;
 551
 552                 val = msg->buf[idx];
 553
 554                 /* mark the last byte */
 555                 if (idx == msg->len - 1) {
 556                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 557
 558                         if (iproc_i2c->irq) {
 559                                 u32 tmp;
 560
 561                                 /*
 562                                  * Since this is the last byte, we should now
 563                                  * disable TX FIFO underrun interrupt
 564                                  */
 565                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 566                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 567                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 568                                                  tmp);
 569                         }
 570                 }
 571
 572                 /* load data into TX FIFO */
 573                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 574         }
 575
 576         /* update number of transferred bytes */
 577         iproc_i2c->tx_bytes += tx_bytes;
 578 }
 579
 580 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 581 {
 582         struct i2c_msg *msg = iproc_i2c->msg;
 583         u32 bytes_left, val;
 584
 585         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 586         bytes_left = msg->len - iproc_i2c->rx_bytes;
 587         if (bytes_left == 0) {
 588                 if (iproc_i2c->irq) {
 589                         /* finished reading all data, disable rx thld event */
 590                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 591                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 592                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 593                 }
 594         } else if (bytes_left < iproc_i2c->thld_bytes) {
 595                 /* set bytes left as threshold */
 596                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 597                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 598                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 599                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 600                 iproc_i2c->thld_bytes = bytes_left;
 601         }
 602         /*
 603          * bytes_left >= iproc_i2c->thld_bytes,
 604          * hence no need to change the THRESHOLD SET.
 605          * It will remain as iproc_i2c->thld_bytes itself
 606          */
 607 }
 608
 609 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 610                                           u32 status)
 611 {
 612         /* TX FIFO is empty and we have more data to send */
 613         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 614                 bcm_iproc_i2c_send(iproc_i2c);
 615
 616         /* RX FIFO threshold is reached and data needs to be read out */
 617         if (status & BIT(IS_M_RX_THLD_SHIFT))
 618                 bcm_iproc_i2c_read(iproc_i2c);
 619
 620         /* transfer is done */
 621         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 622                 iproc_i2c->xfer_is_done = 1;
 623                 if (iproc_i2c->irq)
 624                         complete(&iproc_i2c->done);
 625         }
 626 }
 627
 628 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 629 {
 630         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 631         u32 slave_status;
 632         u32 status;
 633         bool ret;
 634
 635         status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 636         /* process only slave interrupt which are enabled */
 637         slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
 638                        ISR_MASK_SLAVE;
 639
 640         if (slave_status) {
 641                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
 642                 if (ret)
 643                         return IRQ_HANDLED;
 644                 else
 645                         return IRQ_NONE;
 646         }
 647
 648         status &= ISR_MASK;
 649         if (!status)
 650                 return IRQ_NONE;
 651
 652         /* process all master based events */
 653         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 654         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 655
 656         return IRQ_HANDLED;
 657 }
 658
 659 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 660 {
 661         u32 val;
 662
 663         /* put controller in reset */
 664         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 665         val |= BIT(CFG_RESET_SHIFT);
 666         val &= ~(BIT(CFG_EN_SHIFT));
 667         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 668
 669         /* wait 100 usec per spec */
 670         udelay(100);
 671
 672         /* bring controller out of reset */
 673         val &= ~(BIT(CFG_RESET_SHIFT));
 674         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 675
 676         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 677         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 678         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 679         /* disable all interrupts */
 680         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 681         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 682                         IE_M_ALL_INTERRUPT_SHIFT);
 683         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 684
 685         /* clear all pending interrupts */
 686         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 687
 688         return 0;
 689 }
 690
 691 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 692                                          bool enable)
 693 {
 694         u32 val;
 695
 696         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 697         if (enable)
 698                 val |= BIT(CFG_EN_SHIFT);
 699         else
 700                 val &= ~BIT(CFG_EN_SHIFT);
 701         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 702 }
 703
 704 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 705                                       struct i2c_msg *msg)
 706 {
 707         u32 val;
 708
 709         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 710         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 711
 712         switch (val) {
 713         case M_CMD_STATUS_SUCCESS:
 714                 return 0;
 715
 716         case M_CMD_STATUS_LOST_ARB:
 717                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 718                 return -EAGAIN;
 719
 720         case M_CMD_STATUS_NACK_ADDR:
 721                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 722                 return -ENXIO;
 723
 724         case M_CMD_STATUS_NACK_DATA:
 725                 dev_dbg(iproc_i2c->device, "NAK data\n");
 726                 return -ENXIO;
 727
 728         case M_CMD_STATUS_TIMEOUT:
 729                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 730                 return -ETIMEDOUT;
 731
 732         case M_CMD_STATUS_FIFO_UNDERRUN:
 733                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 734                 return -ENXIO;
 735
 736         case M_CMD_STATUS_RX_FIFO_FULL:
 737                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 738                 return -ETIMEDOUT;
 739
 740         default:
 741                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 742
 743                 /* re-initialize i2c for recovery */
 744                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 745                 bcm_iproc_i2c_init(iproc_i2c);
 746                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 747
 748                 return -EIO;
 749         }
 750 }
 751
 752 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 753                                    struct i2c_msg *msg,
 754                                    u32 cmd)
 755 {
 756         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 757         u32 val, status;
 758         int ret;
 759
 760         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 761
 762         if (iproc_i2c->irq) {
 763                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 764                                                         time_left);
 765                 /* disable all interrupts */
 766                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 767                 /* read it back to flush the write */
 768                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 769                 /* make sure the interrupt handler isn't running */
 770                 synchronize_irq(iproc_i2c->irq);
 771
 772         } else { /* polling mode */
 773                 unsigned long timeout = jiffies + time_left;
 774
 775                 do {
 776                         status = iproc_i2c_rd_reg(iproc_i2c,
 777                                                   IS_OFFSET) & ISR_MASK;
 778                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 779                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 780
 781                         if (time_after(jiffies, timeout)) {
 782                                 time_left = 0;
 783                                 break;
 784                         }
 785
 786                         cpu_relax();
 787                         cond_resched();
 788                 } while (!iproc_i2c->xfer_is_done);
 789         }
 790
 791         if (!time_left && !iproc_i2c->xfer_is_done) {
 792                 dev_err(iproc_i2c->device, "transaction timed out\n");
 793
 794                 /* flush both TX/RX FIFOs */
 795                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 796                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 797                 return -ETIMEDOUT;
 798         }
 799
 800         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 801         if (ret) {
 802                 /* flush both TX/RX FIFOs */
 803                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 804                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 805                 return ret;
 806         }
 807
 808         return 0;
 809 }
 810
 811 /*
 812  * If 'process_call' is true, then this is a multi-msg transfer that requires
 813  * a repeated start between the messages.
 814  * More specifically, it must be a write (reg) followed by a read (data).
 815  * The i2c quirks are set to enforce this rule.
 816  */
 817 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
 818                                         struct i2c_msg *msgs, bool process_call)
 819 {
 820         int i;
 821         u8 addr;
 822         u32 val, tmp, val_intr_en;
 823         unsigned int tx_bytes;
 824         struct i2c_msg *msg = &msgs[0];
 825
 826         /* check if bus is busy */
 827         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 828                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 829                 dev_warn(iproc_i2c->device, "bus is busy\n");
 830                 return -EBUSY;
 831         }
 832
 833         iproc_i2c->msg = msg;
 834
 835         /* format and load slave address into the TX FIFO */
 836         addr = i2c_8bit_addr_from_msg(msg);
 837         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 838
 839         /*
 840          * For a write transaction, load data into the TX FIFO. Only allow
 841          * loading up to TX FIFO size - 1 bytes of data since the first byte
 842          * has been used up by the slave address
 843          */
 844         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 845         if (!(msg->flags & I2C_M_RD)) {
 846                 for (i = 0; i < tx_bytes; i++) {
 847                         val = msg->buf[i];
 848
 849                         /* mark the last byte */
 850                         if (!process_call && (i == msg->len - 1))
 851                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 852
 853                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 854                 }
 855                 iproc_i2c->tx_bytes = tx_bytes;
 856         }
 857
 858         /* Process the read message if this is process call */
 859         if (process_call) {
 860                 msg++;
 861                 iproc_i2c->msg = msg;  /* point to second msg */
 862
 863                 /*
 864                  * The last byte to be sent out should be a slave
 865                  * address with read operation
 866                  */
 867                 addr = i2c_8bit_addr_from_msg(msg);
 868                 /* mark it the last byte out */
 869                 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
 870                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 871         }
 872
 873         /* mark as incomplete before starting the transaction */
 874         if (iproc_i2c->irq)
 875                 reinit_completion(&iproc_i2c->done);
 876
 877         iproc_i2c->xfer_is_done = 0;
 878
 879         /*
 880          * Enable the "start busy" interrupt, which will be triggered after the
 881          * transaction is done, i.e., the internal start_busy bit, transitions
 882          * from 1 to 0.
 883          */
 884         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 885
 886         /*
 887          * If TX data size is larger than the TX FIFO, need to enable TX
 888          * underrun interrupt, which will be triggerred when the TX FIFO is
 889          * empty. When that happens we can then pump more data into the FIFO
 890          */
 891         if (!process_call && !(msg->flags & I2C_M_RD) &&
 892             msg->len > iproc_i2c->tx_bytes)
 893                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 894
 895         /*
 896          * Now we can activate the transfer. For a read operation, specify the
 897          * number of bytes to read
 898          */
 899         val = BIT(M_CMD_START_BUSY_SHIFT);
 900
 901         if (msg->len == 0) {
 902                 /* SMBUS QUICK Command (Read/Write) */
 903                 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
 904         } else if (msg->flags & I2C_M_RD) {
 905                 u32 protocol;
 906
 907                 iproc_i2c->rx_bytes = 0;
 908                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 909                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 910                 else
 911                         iproc_i2c->thld_bytes = msg->len;
 912
 913                 /* set threshold value */
 914                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 915                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 916                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 917                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 918
 919                 /* enable the RX threshold interrupt */
 920                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 921
 922                 protocol = process_call ?
 923                                 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
 924
 925                 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
 926                        (msg->len << M_CMD_RD_CNT_SHIFT);
 927         } else {
 928                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 929         }
 930
 931         if (iproc_i2c->irq)
 932                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 933
 934         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 935 }
 936
 937 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 938                               struct i2c_msg msgs[], int num)
 939 {
 940         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 941         bool process_call = false;
 942         int ret;
 943
 944         if (num == 2) {
 945                 /* Repeated start, use process call */
 946                 process_call = true;
 947                 if (msgs[1].flags & I2C_M_NOSTART) {
 948                         dev_err(iproc_i2c->device, "Invalid repeated start\n");
 949                         return -EOPNOTSUPP;
 950                 }
 951         }
 952
 953         ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
 954         if (ret) {
 955                 dev_dbg(iproc_i2c->device, "xfer failed\n");
 956                 return ret;
 957         }
 958
 959         return num;
 960 }
 961
 962 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 963 {
 964         u32 val;
 965
 966         val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 967
 968         if (adap->algo->reg_slave)
 969                 val |= I2C_FUNC_SLAVE;
 970
 971         return val;
 972 }
 973
 974 static struct i2c_algorithm bcm_iproc_algo = {
 975         .master_xfer = bcm_iproc_i2c_xfer,
 976         .functionality = bcm_iproc_i2c_functionality,
 977         .reg_slave = bcm_iproc_i2c_reg_slave,
 978         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 979 };
 980
 981 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 982         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 983         .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
 984         .max_read_len = M_RX_MAX_READ_LEN,
 985 };
 986
 987 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 988 {
 989         unsigned int bus_speed;
 990         u32 val;
 991         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 992                                        "clock-frequency", &bus_speed);
 993         if (ret < 0) {
 994                 dev_info(iproc_i2c->device,
 995                         "unable to interpret clock-frequency DT property\n");
 996                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 997         }
 998
 999         if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
1000                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
1001                         bus_speed);
1002                 dev_err(iproc_i2c->device,
1003                         "valid speeds are 100khz and 400khz\n");
1004                 return -EINVAL;
1005         } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1006                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1007         } else {
1008                 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1009         }
1010
1011         iproc_i2c->bus_speed = bus_speed;
1012         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1013         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1014         val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1015         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1016
1017         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1018
1019         return 0;
1020 }
1021
1022 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1023 {
1024         int irq, ret = 0;
1025         struct bcm_iproc_i2c_dev *iproc_i2c;
1026         struct i2c_adapter *adap;
1027         struct resource *res;
1028
1029         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1030                                  GFP_KERNEL);
1031         if (!iproc_i2c)
1032                 return -ENOMEM;
1033
1034         platform_set_drvdata(pdev, iproc_i2c);
1035         iproc_i2c->device = &pdev->dev;
1036         iproc_i2c->type =
1037                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
1038         init_completion(&iproc_i2c->done);
1039
1040         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1041         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
1042         if (IS_ERR(iproc_i2c->base))
1043                 return PTR_ERR(iproc_i2c->base);
1044
1045         if (iproc_i2c->type == IPROC_I2C_NIC) {
1046                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1047                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1048                                                             res);
1049                 if (IS_ERR(iproc_i2c->idm_base))
1050                         return PTR_ERR(iproc_i2c->idm_base);
1051
1052                 ret = of_property_read_u32(iproc_i2c->device->of_node,
1053                                            "brcm,ape-hsls-addr-mask",
1054                                            &iproc_i2c->ape_addr_mask);
1055                 if (ret < 0) {
1056                         dev_err(iproc_i2c->device,
1057                                 "'brcm,ape-hsls-addr-mask' missing\n");
1058                         return -EINVAL;
1059                 }
1060
1061                 spin_lock_init(&iproc_i2c->idm_lock);
1062
1063                 /* no slave support */
1064                 bcm_iproc_algo.reg_slave = NULL;
1065                 bcm_iproc_algo.unreg_slave = NULL;
1066         }
1067
1068         ret = bcm_iproc_i2c_init(iproc_i2c);
1069         if (ret)
1070                 return ret;
1071
1072         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1073         if (ret)
1074                 return ret;
1075
1076         irq = platform_get_irq(pdev, 0);
1077         if (irq > 0) {
1078                 ret = devm_request_irq(iproc_i2c->device, irq,
1079                                        bcm_iproc_i2c_isr, 0, pdev->name,
1080                                        iproc_i2c);
1081                 if (ret < 0) {
1082                         dev_err(iproc_i2c->device,
1083                                 "unable to request irq %i\n", irq);
1084                         return ret;
1085                 }
1086
1087                 iproc_i2c->irq = irq;
1088         } else {
1089                 dev_warn(iproc_i2c->device,
1090                          "no irq resource, falling back to poll mode\n");
1091         }
1092
1093         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1094
1095         adap = &iproc_i2c->adapter;
1096         i2c_set_adapdata(adap, iproc_i2c);
1097         snprintf(adap->name, sizeof(adap->name),
1098                 "Broadcom iProc (%s)",
1099                 of_node_full_name(iproc_i2c->device->of_node));
1100         adap->algo = &bcm_iproc_algo;
1101         adap->quirks = &bcm_iproc_i2c_quirks;
1102         adap->dev.parent = &pdev->dev;
1103         adap->dev.of_node = pdev->dev.of_node;
1104
1105         return i2c_add_adapter(adap);
1106 }
1107
1108 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
1109 {
1110         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1111
1112         if (iproc_i2c->irq) {
1113                 /*
1114                  * Make sure there's no pending interrupt when we remove the
1115                  * adapter
1116                  */
1117                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1118                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1119                 synchronize_irq(iproc_i2c->irq);
1120         }
1121
1122         i2c_del_adapter(&iproc_i2c->adapter);
1123         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1124
1125         return 0;
1126 }
1127
1128 #ifdef CONFIG_PM_SLEEP
1129
1130 static int bcm_iproc_i2c_suspend(struct device *dev)
1131 {
1132         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1133
1134         if (iproc_i2c->irq) {
1135                 /*
1136                  * Make sure there's no pending interrupt when we go into
1137                  * suspend
1138                  */
1139                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1140                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1141                 synchronize_irq(iproc_i2c->irq);
1142         }
1143
1144         /* now disable the controller */
1145         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1146
1147         return 0;
1148 }
1149
1150 static int bcm_iproc_i2c_resume(struct device *dev)
1151 {
1152         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1153         int ret;
1154         u32 val;
1155
1156         /*
1157          * Power domain could have been shut off completely in system deep
1158          * sleep, so re-initialize the block here
1159          */
1160         ret = bcm_iproc_i2c_init(iproc_i2c);
1161         if (ret)
1162                 return ret;
1163
1164         /* configure to the desired bus speed */
1165         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1166         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1167         val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1168         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1169
1170         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1171
1172         return 0;
1173 }
1174
1175 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1176         .suspend_late = &bcm_iproc_i2c_suspend,
1177         .resume_early = &bcm_iproc_i2c_resume
1178 };
1179
1180 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1181 #else
1182 #define BCM_IPROC_I2C_PM_OPS NULL
1183 #endif /* CONFIG_PM_SLEEP */
1184
1185
1186 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1187 {
1188         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1189
1190         if (iproc_i2c->slave)
1191                 return -EBUSY;
1192
1193         if (slave->flags & I2C_CLIENT_TEN)
1194                 return -EAFNOSUPPORT;
1195
1196         iproc_i2c->slave = slave;
1197
1198         tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1199                      (unsigned long)iproc_i2c);
1200
1201         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1202         return 0;
1203 }
1204
1205 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1206 {
1207         u32 tmp;
1208         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1209
1210         if (!iproc_i2c->slave)
1211                 return -EINVAL;
1212
1213         disable_irq(iproc_i2c->irq);
1214
1215         /* disable all slave interrupts */
1216         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1217         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1218                         IE_S_ALL_INTERRUPT_SHIFT);
1219         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1220
1221         tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1222
1223         /* Erase the slave address programmed */
1224         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1225         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1226         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1227
1228         /* flush TX/RX FIFOs */
1229         tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1230         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1231
1232         /* clear all pending slave interrupts */
1233         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1234
1235         iproc_i2c->slave = NULL;
1236
1237         enable_irq(iproc_i2c->irq);
1238
1239         return 0;
1240 }
1241
1242 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1243         {
1244                 .compatible = "brcm,iproc-i2c",
1245                 .data = (int *)IPROC_I2C,
1246         }, {
1247                 .compatible = "brcm,iproc-nic-i2c",
1248                 .data = (int *)IPROC_I2C_NIC,
1249         },
1250         { /* sentinel */ }
1251 };
1252 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1253
1254 static struct platform_driver bcm_iproc_i2c_driver = {
1255         .driver = {
1256                 .name = "bcm-iproc-i2c",
1257                 .of_match_table = bcm_iproc_i2c_of_match,
1258                 .pm = BCM_IPROC_I2C_PM_OPS,
1259         },
1260         .probe = bcm_iproc_i2c_probe,
1261         .remove = bcm_iproc_i2c_remove,
1262 };
1263 module_platform_driver(bcm_iproc_i2c_driver);
1264
1265 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1266 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1267 MODULE_LICENSE("GPL v2");