2 * Aspeed 24XX/25XX I2C Controller.
4 * Copyright (C) 2012-2017 ASPEED Technology Inc.
5 * Copyright 2017 IBM Corporation
6 * Copyright 2017 Google, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/i2c.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
33 #define ASPEED_I2C_FUN_CTRL_REG 0x00
34 #define ASPEED_I2C_AC_TIMING_REG1 0x04
35 #define ASPEED_I2C_AC_TIMING_REG2 0x08
36 #define ASPEED_I2C_INTR_CTRL_REG 0x0c
37 #define ASPEED_I2C_INTR_STS_REG 0x10
38 #define ASPEED_I2C_CMD_REG 0x14
39 #define ASPEED_I2C_DEV_ADDR_REG 0x18
40 #define ASPEED_I2C_BYTE_BUF_REG 0x20
42 /* Global Register Definition */
43 /* 0x00 : I2C Interrupt Status Register */
44 /* 0x08 : I2C Interrupt Target Assignment */
46 /* Device Register Definition */
47 /* 0x00 : I2CD Function Control Register */
48 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
49 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
50 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
51 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
52 #define ASPEED_I2CD_SLAVE_EN BIT(1)
53 #define ASPEED_I2CD_MASTER_EN BIT(0)
55 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
56 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)
57 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)
58 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)
59 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
60 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
61 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
62 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
63 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
64 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
65 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
66 #define ASPEED_NO_TIMEOUT_CTRL 0
68 /* 0x0c : I2CD Interrupt Control Register &
69 * 0x10 : I2CD Interrupt Status Register
71 * These share bit definitions, so use the same values for the enable &
74 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
75 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
76 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
77 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
78 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
79 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
80 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
81 #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
82 #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
83 #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
84 #define ASPEED_I2CD_INTR_ALL \
85 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
86 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
87 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
88 ASPEED_I2CD_INTR_ABNORMAL | \
89 ASPEED_I2CD_INTR_NORMAL_STOP | \
90 ASPEED_I2CD_INTR_ARBIT_LOSS | \
91 ASPEED_I2CD_INTR_RX_DONE | \
92 ASPEED_I2CD_INTR_TX_NAK | \
93 ASPEED_I2CD_INTR_TX_ACK)
95 /* 0x14 : I2CD Command/Status Register */
96 #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
97 #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
98 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
99 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
102 #define ASPEED_I2CD_M_STOP_CMD BIT(5)
103 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
104 #define ASPEED_I2CD_M_RX_CMD BIT(3)
105 #define ASPEED_I2CD_S_TX_CMD BIT(2)
106 #define ASPEED_I2CD_M_TX_CMD BIT(1)
107 #define ASPEED_I2CD_M_START_CMD BIT(0)
109 /* 0x18 : I2CD Slave Device Address Register */
110 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
112 enum aspeed_i2c_master_state {
113 ASPEED_I2C_MASTER_INACTIVE,
114 ASPEED_I2C_MASTER_START,
115 ASPEED_I2C_MASTER_TX_FIRST,
116 ASPEED_I2C_MASTER_TX,
117 ASPEED_I2C_MASTER_RX_FIRST,
118 ASPEED_I2C_MASTER_RX,
119 ASPEED_I2C_MASTER_STOP,
122 enum aspeed_i2c_slave_state {
123 ASPEED_I2C_SLAVE_STOP,
124 ASPEED_I2C_SLAVE_START,
125 ASPEED_I2C_SLAVE_READ_REQUESTED,
126 ASPEED_I2C_SLAVE_READ_PROCESSED,
127 ASPEED_I2C_SLAVE_WRITE_REQUESTED,
128 ASPEED_I2C_SLAVE_WRITE_RECEIVED,
131 struct aspeed_i2c_bus {
132 struct i2c_adapter adap;
135 /* Synchronizes I/O mem access to base. */
137 struct completion cmd_complete;
138 u32 (*get_clk_reg_val)(struct device *dev,
140 unsigned long parent_clk_frequency;
142 /* Transaction state. */
143 enum aspeed_i2c_master_state master_state;
144 struct i2c_msg *msgs;
150 /* Protected only by i2c_lock_bus */
151 int master_xfer_result;
152 #if IS_ENABLED(CONFIG_I2C_SLAVE)
153 struct i2c_client *slave;
154 enum aspeed_i2c_slave_state slave_state;
155 #endif /* CONFIG_I2C_SLAVE */
158 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
160 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
162 unsigned long time_left, flags;
166 spin_lock_irqsave(&bus->lock, flags);
167 command = readl(bus->base + ASPEED_I2C_CMD_REG);
169 if (command & ASPEED_I2CD_SDA_LINE_STS) {
170 /* Bus is idle: no recovery needed. */
171 if (command & ASPEED_I2CD_SCL_LINE_STS)
173 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
176 reinit_completion(&bus->cmd_complete);
177 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
178 spin_unlock_irqrestore(&bus->lock, flags);
180 time_left = wait_for_completion_timeout(
181 &bus->cmd_complete, bus->adap.timeout);
183 spin_lock_irqsave(&bus->lock, flags);
186 else if (bus->cmd_err)
188 /* Recovery failed. */
189 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
190 ASPEED_I2CD_SCL_LINE_STS))
194 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
197 reinit_completion(&bus->cmd_complete);
198 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
199 writel(ASPEED_I2CD_BUS_RECOVER_CMD,
200 bus->base + ASPEED_I2C_CMD_REG);
201 spin_unlock_irqrestore(&bus->lock, flags);
203 time_left = wait_for_completion_timeout(
204 &bus->cmd_complete, bus->adap.timeout);
206 spin_lock_irqsave(&bus->lock, flags);
209 else if (bus->cmd_err)
211 /* Recovery failed. */
212 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
213 ASPEED_I2CD_SDA_LINE_STS))
218 spin_unlock_irqrestore(&bus->lock, flags);
223 spin_unlock_irqrestore(&bus->lock, flags);
225 return aspeed_i2c_reset(bus);
228 #if IS_ENABLED(CONFIG_I2C_SLAVE)
229 static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus)
231 u32 command, irq_status, status_ack = 0;
232 struct i2c_client *slave = bus->slave;
233 bool irq_handled = true;
236 spin_lock(&bus->lock);
242 command = readl(bus->base + ASPEED_I2C_CMD_REG);
243 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
245 /* Slave was requested, restart state machine. */
246 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
247 status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH;
248 bus->slave_state = ASPEED_I2C_SLAVE_START;
251 /* Slave is not currently active, irq was for someone else. */
252 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
257 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
258 irq_status, command);
260 /* Slave was sent something. */
261 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
262 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
263 /* Handle address frame. */
264 if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
267 ASPEED_I2C_SLAVE_READ_REQUESTED;
270 ASPEED_I2C_SLAVE_WRITE_REQUESTED;
272 status_ack |= ASPEED_I2CD_INTR_RX_DONE;
275 /* Slave was asked to stop. */
276 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
277 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
278 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
280 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
281 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
282 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
285 switch (bus->slave_state) {
286 case ASPEED_I2C_SLAVE_READ_REQUESTED:
287 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
288 dev_err(bus->dev, "Unexpected ACK on read request.\n");
289 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
291 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
292 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
293 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
295 case ASPEED_I2C_SLAVE_READ_PROCESSED:
296 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
297 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
299 "Expected ACK after processed read.\n");
300 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
301 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
302 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
304 case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
305 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
306 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
308 case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
309 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
311 case ASPEED_I2C_SLAVE_STOP:
312 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
315 dev_err(bus->dev, "unhandled slave_state: %d\n",
320 if (status_ack != irq_status)
322 "irq handled != irq. expected %x, but was %x\n",
323 irq_status, status_ack);
324 writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG);
327 spin_unlock(&bus->lock);
330 #endif /* CONFIG_I2C_SLAVE */
332 /* precondition: bus.lock has been acquired. */
333 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
335 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
336 struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
337 u8 slave_addr = msg->addr << 1;
339 bus->master_state = ASPEED_I2C_MASTER_START;
342 if (msg->flags & I2C_M_RD) {
344 command |= ASPEED_I2CD_M_RX_CMD;
345 /* Need to let the hardware know to NACK after RX. */
346 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
347 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
350 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
351 writel(command, bus->base + ASPEED_I2C_CMD_REG);
354 /* precondition: bus.lock has been acquired. */
355 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
357 bus->master_state = ASPEED_I2C_MASTER_STOP;
358 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
361 /* precondition: bus.lock has been acquired. */
362 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
364 if (bus->msgs_index + 1 < bus->msgs_count) {
366 aspeed_i2c_do_start(bus);
368 aspeed_i2c_do_stop(bus);
372 static int aspeed_i2c_is_irq_error(u32 irq_status)
374 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
376 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
377 ASPEED_I2CD_INTR_SCL_TIMEOUT))
379 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
385 static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
387 u32 irq_status, status_ack = 0, command = 0;
392 spin_lock(&bus->lock);
393 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
394 /* Ack all interrupt bits. */
395 writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG);
397 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
398 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
399 status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
404 * We encountered an interrupt that reports an error: the hardware
405 * should clear the command queue effectively taking us back to the
408 ret = aspeed_i2c_is_irq_error(irq_status);
410 dev_dbg(bus->dev, "received error interrupt: 0x%08x",
413 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
417 /* We are in an invalid state; reset bus to a known state. */
419 dev_err(bus->dev, "bus in unknown state");
421 if (bus->master_state != ASPEED_I2C_MASTER_STOP)
422 aspeed_i2c_do_stop(bus);
423 goto out_no_complete;
425 msg = &bus->msgs[bus->msgs_index];
428 * START is a special case because we still have to handle a subsequent
429 * TX or RX immediately after we handle it, so we handle it here and
430 * then update the state and handle the new state below.
432 if (bus->master_state == ASPEED_I2C_MASTER_START) {
433 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
434 pr_devel("no slave present at %02x", msg->addr);
435 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
436 bus->cmd_err = -ENXIO;
437 aspeed_i2c_do_stop(bus);
438 goto out_no_complete;
440 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
441 if (msg->len == 0) { /* SMBUS_QUICK */
442 aspeed_i2c_do_stop(bus);
443 goto out_no_complete;
445 if (msg->flags & I2C_M_RD)
446 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
448 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
451 switch (bus->master_state) {
452 case ASPEED_I2C_MASTER_TX:
453 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
454 dev_dbg(bus->dev, "slave NACKed TX");
455 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
457 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
458 dev_err(bus->dev, "slave failed to ACK TX");
461 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
462 /* fallthrough intended */
463 case ASPEED_I2C_MASTER_TX_FIRST:
464 if (bus->buf_index < msg->len) {
465 bus->master_state = ASPEED_I2C_MASTER_TX;
466 writel(msg->buf[bus->buf_index++],
467 bus->base + ASPEED_I2C_BYTE_BUF_REG);
468 writel(ASPEED_I2CD_M_TX_CMD,
469 bus->base + ASPEED_I2C_CMD_REG);
471 aspeed_i2c_next_msg_or_stop(bus);
473 goto out_no_complete;
474 case ASPEED_I2C_MASTER_RX_FIRST:
475 /* RX may not have completed yet (only address cycle) */
476 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
477 goto out_no_complete;
478 /* fallthrough intended */
479 case ASPEED_I2C_MASTER_RX:
480 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
481 dev_err(bus->dev, "master failed to RX");
484 status_ack |= ASPEED_I2CD_INTR_RX_DONE;
486 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
487 msg->buf[bus->buf_index++] = recv_byte;
489 if (msg->flags & I2C_M_RECV_LEN) {
490 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
491 bus->cmd_err = -EPROTO;
492 aspeed_i2c_do_stop(bus);
493 goto out_no_complete;
495 msg->len = recv_byte +
496 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
497 msg->flags &= ~I2C_M_RECV_LEN;
500 if (bus->buf_index < msg->len) {
501 bus->master_state = ASPEED_I2C_MASTER_RX;
502 command = ASPEED_I2CD_M_RX_CMD;
503 if (bus->buf_index + 1 == msg->len)
504 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
505 writel(command, bus->base + ASPEED_I2C_CMD_REG);
507 aspeed_i2c_next_msg_or_stop(bus);
509 goto out_no_complete;
510 case ASPEED_I2C_MASTER_STOP:
511 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
512 dev_err(bus->dev, "master failed to STOP");
514 /* Do not STOP as we have already tried. */
516 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
519 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
521 case ASPEED_I2C_MASTER_INACTIVE:
523 "master received interrupt 0x%08x, but is inactive",
526 /* Do not STOP as we should be inactive. */
529 WARN(1, "unknown master state\n");
530 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
531 bus->cmd_err = -EINVAL;
536 aspeed_i2c_do_stop(bus);
537 goto out_no_complete;
541 bus->master_xfer_result = bus->cmd_err;
543 bus->master_xfer_result = bus->msgs_index + 1;
544 complete(&bus->cmd_complete);
546 if (irq_status != status_ack)
548 "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
549 irq_status, status_ack);
550 spin_unlock(&bus->lock);
554 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
556 struct aspeed_i2c_bus *bus = dev_id;
558 #if IS_ENABLED(CONFIG_I2C_SLAVE)
559 if (aspeed_i2c_slave_irq(bus)) {
560 dev_dbg(bus->dev, "irq handled by slave.\n");
563 #endif /* CONFIG_I2C_SLAVE */
565 return aspeed_i2c_master_irq(bus) ? IRQ_HANDLED : IRQ_NONE;
568 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
569 struct i2c_msg *msgs, int num)
571 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
572 unsigned long time_left, flags;
575 spin_lock_irqsave(&bus->lock, flags);
578 /* If bus is busy, attempt recovery. We assume a single master
581 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
582 spin_unlock_irqrestore(&bus->lock, flags);
583 ret = aspeed_i2c_recover_bus(bus);
586 spin_lock_irqsave(&bus->lock, flags);
592 bus->msgs_count = num;
594 reinit_completion(&bus->cmd_complete);
595 aspeed_i2c_do_start(bus);
596 spin_unlock_irqrestore(&bus->lock, flags);
598 time_left = wait_for_completion_timeout(&bus->cmd_complete,
604 return bus->master_xfer_result;
607 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
609 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
612 #if IS_ENABLED(CONFIG_I2C_SLAVE)
613 /* precondition: bus.lock has been acquired. */
614 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
616 u32 addr_reg_val, func_ctrl_reg_val;
618 /* Set slave addr. */
619 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
620 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
621 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
622 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
624 /* Turn on slave mode. */
625 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
626 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
627 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
630 static int aspeed_i2c_reg_slave(struct i2c_client *client)
632 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
635 spin_lock_irqsave(&bus->lock, flags);
637 spin_unlock_irqrestore(&bus->lock, flags);
641 __aspeed_i2c_reg_slave(bus, client->addr);
644 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
645 spin_unlock_irqrestore(&bus->lock, flags);
650 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
652 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
653 u32 func_ctrl_reg_val;
656 spin_lock_irqsave(&bus->lock, flags);
658 spin_unlock_irqrestore(&bus->lock, flags);
662 /* Turn off slave mode. */
663 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
664 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
665 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
668 spin_unlock_irqrestore(&bus->lock, flags);
672 #endif /* CONFIG_I2C_SLAVE */
674 static const struct i2c_algorithm aspeed_i2c_algo = {
675 .master_xfer = aspeed_i2c_master_xfer,
676 .functionality = aspeed_i2c_functionality,
677 #if IS_ENABLED(CONFIG_I2C_SLAVE)
678 .reg_slave = aspeed_i2c_reg_slave,
679 .unreg_slave = aspeed_i2c_unreg_slave,
680 #endif /* CONFIG_I2C_SLAVE */
683 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
684 u32 clk_high_low_mask,
687 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
690 * SCL_high and SCL_low represent a value 1 greater than what is stored
691 * since a zero divider is meaningless. Thus, the max value each can
692 * store is every bit set + 1. Since SCL_high and SCL_low are added
693 * together (see below), the max value of both is the max value of one
696 clk_high_low_max = (clk_high_low_mask + 1) * 2;
699 * The actual clock frequency of SCL is:
700 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
701 * = APB_freq / divisor
702 * where base_freq is a programmable clock divider; its value is
703 * base_freq = 1 << base_clk_divisor
704 * SCL_high is the number of base_freq clock cycles that SCL stays high
705 * and SCL_low is the number of base_freq clock cycles that SCL stays
706 * low for a period of SCL.
707 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
708 * thus, they start counting at zero. So
709 * SCL_high = clk_high + 1
710 * SCL_low = clk_low + 1
712 * SCL_freq = APB_freq /
713 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
714 * The documentation recommends clk_high >= clk_high_max / 2 and
715 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
716 * gives us the following solution:
718 base_clk_divisor = divisor > clk_high_low_max ?
719 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
721 if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
722 base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
723 clk_low = clk_high_low_mask;
724 clk_high = clk_high_low_mask;
726 "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
727 divisor, (1 << base_clk_divisor) * clk_high_low_max);
729 tmp = (divisor + (1 << base_clk_divisor) - 1)
732 clk_high = tmp - clk_low;
742 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
743 & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
744 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
745 & ASPEED_I2CD_TIME_SCL_LOW_MASK)
747 & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
750 static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
753 * clk_high and clk_low are each 3 bits wide, so each can hold a max
754 * value of 8 giving a clk_high_low_max of 16.
756 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
759 static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
762 * clk_high and clk_low are each 4 bits wide, so each can hold a max
763 * value of 16 giving a clk_high_low_max of 32.
765 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
768 /* precondition: bus.lock has been acquired. */
769 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
771 u32 divisor, clk_reg_val;
773 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
774 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
775 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
776 ASPEED_I2CD_TIME_THDSTA_MASK |
777 ASPEED_I2CD_TIME_TACST_MASK);
778 clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
779 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
780 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
785 /* precondition: bus.lock has been acquired. */
786 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
787 struct platform_device *pdev)
789 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
792 /* Disable everything. */
793 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
795 ret = aspeed_i2c_init_clk(bus);
799 if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
800 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
802 /* Enable Master Mode */
803 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
804 bus->base + ASPEED_I2C_FUN_CTRL_REG);
806 #if IS_ENABLED(CONFIG_I2C_SLAVE)
807 /* If slave has already been registered, re-enable it. */
809 __aspeed_i2c_reg_slave(bus, bus->slave->addr);
810 #endif /* CONFIG_I2C_SLAVE */
812 /* Set interrupt generation of I2C controller */
813 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
818 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
820 struct platform_device *pdev = to_platform_device(bus->dev);
824 spin_lock_irqsave(&bus->lock, flags);
826 /* Disable and ack all interrupts. */
827 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
828 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
830 ret = aspeed_i2c_init(bus, pdev);
832 spin_unlock_irqrestore(&bus->lock, flags);
837 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
839 .compatible = "aspeed,ast2400-i2c-bus",
840 .data = aspeed_i2c_24xx_get_clk_reg_val,
843 .compatible = "aspeed,ast2500-i2c-bus",
844 .data = aspeed_i2c_25xx_get_clk_reg_val,
848 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
850 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
852 const struct of_device_id *match;
853 struct aspeed_i2c_bus *bus;
854 struct clk *parent_clk;
855 struct resource *res;
858 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
863 bus->base = devm_ioremap_resource(&pdev->dev, res);
864 if (IS_ERR(bus->base))
865 return PTR_ERR(bus->base);
867 parent_clk = devm_clk_get(&pdev->dev, NULL);
868 if (IS_ERR(parent_clk))
869 return PTR_ERR(parent_clk);
870 bus->parent_clk_frequency = clk_get_rate(parent_clk);
871 /* We just need the clock rate, we don't actually use the clk object. */
872 devm_clk_put(&pdev->dev, parent_clk);
874 ret = of_property_read_u32(pdev->dev.of_node,
875 "bus-frequency", &bus->bus_frequency);
878 "Could not read bus-frequency property\n");
879 bus->bus_frequency = 100000;
882 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
884 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
886 bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
889 /* Initialize the I2C adapter */
890 spin_lock_init(&bus->lock);
891 init_completion(&bus->cmd_complete);
892 bus->adap.owner = THIS_MODULE;
893 bus->adap.retries = 0;
894 bus->adap.timeout = 5 * HZ;
895 bus->adap.algo = &aspeed_i2c_algo;
896 bus->adap.dev.parent = &pdev->dev;
897 bus->adap.dev.of_node = pdev->dev.of_node;
898 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
899 i2c_set_adapdata(&bus->adap, bus);
901 bus->dev = &pdev->dev;
903 /* Clean up any left over interrupt state. */
904 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
905 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
907 * bus.lock does not need to be held because the interrupt handler has
908 * not been enabled yet.
910 ret = aspeed_i2c_init(bus, pdev);
914 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
915 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
916 0, dev_name(&pdev->dev), bus);
920 ret = i2c_add_adapter(&bus->adap);
924 platform_set_drvdata(pdev, bus);
926 dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
932 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
934 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
937 spin_lock_irqsave(&bus->lock, flags);
939 /* Disable everything. */
940 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
941 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
943 spin_unlock_irqrestore(&bus->lock, flags);
945 i2c_del_adapter(&bus->adap);
950 static struct platform_driver aspeed_i2c_bus_driver = {
951 .probe = aspeed_i2c_probe_bus,
952 .remove = aspeed_i2c_remove_bus,
954 .name = "aspeed-i2c-bus",
955 .of_match_table = aspeed_i2c_bus_of_table,
958 module_platform_driver(aspeed_i2c_bus_driver);
960 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
961 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
962 MODULE_LICENSE("GPL v2");