1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Intel(R) Trace Hub Global Trace Hub (GTH) data structures
5 * Copyright (C) 2014-2015 Intel Corporation.
8 #ifndef __INTEL_TH_GTH_H__
9 #define __INTEL_TH_GTH_H__
11 /* Map output port parameter bits to symbolic names */
12 #define TH_OUTPUT_PARM(name) \
15 enum intel_th_output_parm {
16 /* output port type */
18 /* generate NULL packet */
22 /* port in reset state */
23 TH_OUTPUT_PARM(reset),
25 TH_OUTPUT_PARM(flush),
26 /* mainenance packet frequency */
27 TH_OUTPUT_PARM(smcfreq),
34 REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */
35 REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */
36 REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */
37 REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */
38 REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */
39 REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */
40 REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */
41 REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */
42 REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
43 REG_GTH_STAT = 0xd4, /* GTH status */
44 REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */
45 REG_GTH_DESTOVR = 0xdc, /* Destination override */
46 REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */
47 REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */
48 REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */
49 REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */
50 REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */
51 REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */
54 /* waiting for Pipeline Empty bit(s) to assert for GTH */
55 #define GTH_PLE_WAITLOOP_DEPTH 10000
57 #define TSUCTRL_CTCRESYNC BIT(0)
58 #define TSCUSTAT_CTCSYNCING BIT(1)
60 #endif /* __INTEL_TH_GTH_H__ */