1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 * Description: CoreSight System Trace Macrocell driver
7 * Initial implementation by Pratik Patel
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
11 * framework by Mathieu Poirier
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
14 * Guaranteed timing and support for various packet type coming from the
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
18 #include <asm/local.h>
19 #include <linux/acpi.h>
20 #include <linux/amba/bus.h>
21 #include <linux/bitmap.h>
22 #include <linux/clk.h>
23 #include <linux/coresight.h>
24 #include <linux/coresight-stm.h>
25 #include <linux/err.h>
26 #include <linux/kernel.h>
27 #include <linux/moduleparam.h>
28 #include <linux/of_address.h>
29 #include <linux/perf_event.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/stm.h>
33 #include "coresight-priv.h"
35 #define STMDMASTARTR 0xc04
36 #define STMDMASTOPR 0xc08
37 #define STMDMASTATR 0xc0c
38 #define STMDMACTLR 0xc10
39 #define STMDMAIDR 0xcfc
41 #define STMHETER 0xd20
42 #define STMHEBSR 0xd60
43 #define STMHEMCR 0xd64
44 #define STMHEMASTR 0xdf4
45 #define STMHEFEAT1R 0xdf8
46 #define STMHEIDR 0xdfc
48 #define STMSPTER 0xe20
49 #define STMPRIVMASKR 0xe40
50 #define STMSPSCR 0xe60
51 #define STMSPMSCR 0xe64
52 #define STMSPOVERRIDER 0xe68
53 #define STMSPMOVERRIDER 0xe6c
54 #define STMSPTRIGCSR 0xe70
56 #define STMTSSTIMR 0xe84
57 #define STMTSFREQR 0xe8c
58 #define STMSYNCR 0xe90
59 #define STMAUXCR 0xe94
60 #define STMSPFEAT1R 0xea0
61 #define STMSPFEAT2R 0xea4
62 #define STMSPFEAT3R 0xea8
63 #define STMITTRIGGER 0xee8
64 #define STMITATBDATA0 0xeec
65 #define STMITATBCTR2 0xef0
66 #define STMITATBID 0xef4
67 #define STMITATBCTR0 0xef8
69 #define STM_32_CHANNEL 32
70 #define BYTES_PER_CHANNEL 256
71 #define STM_TRACE_BUF_SIZE 4096
72 #define STM_SW_MASTER_END 127
74 /* Register bit definition */
75 #define STMTCSR_BUSY_BIT 23
76 /* Reserve the first 10 channels for kernel usage */
77 #define STM_CHANNEL_OFFSET 0
80 STM_PKT_TYPE_DATA = 0x98,
81 STM_PKT_TYPE_FLAG = 0xE8,
82 STM_PKT_TYPE_TRIG = 0xF8,
85 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
86 (ch * BYTES_PER_CHANNEL))
87 #define stm_channel_off(type, opts) (type & ~opts)
89 static int boot_nr_channel;
92 * Not really modular but using module_param is the easiest way to
93 * remain consistent with existing use cases for now.
96 boot_nr_channel, boot_nr_channel, int, S_IRUGO
100 * struct channel_space - central management entity for extended ports
101 * @base: memory mapped base address where channels start.
102 * @phys: physical base address of channel region.
103 * @guaraneed: is the channel delivery guaranteed.
105 struct channel_space {
108 unsigned long *guaranteed;
111 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
114 * struct stm_drvdata - specifics associated to an STM component
115 * @base: memory mapped base address for this component.
116 * @atclk: optional clock for the core parts of the STM.
117 * @csdev: component vitals needed by the framework.
118 * @spinlock: only one at a time pls.
119 * @chs: the channels accociated to this STM.
120 * @stm: structure associated to the generic STM interface.
121 * @mode: this tracer's mode, i.e sysFS, or disabled.
122 * @traceid: value of the current ID for this component.
123 * @write_bytes: Maximus bytes this STM can write at a time.
124 * @stmsper: settings for register STMSPER.
125 * @stmspscr: settings for register STMSPSCR.
126 * @numsp: the total number of stimulus port support by this STM.
127 * @stmheer: settings for register STMHEER.
128 * @stmheter: settings for register STMHETER.
129 * @stmhebsr: settings for register STMHEBSR.
134 struct coresight_device *csdev;
136 struct channel_space chs;
149 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
151 CS_UNLOCK(drvdata->base);
153 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
154 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
155 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
156 writel_relaxed(0x01 | /* Enable HW event tracing */
157 0x04, /* Error detection on event tracing */
158 drvdata->base + STMHEMCR);
160 CS_LOCK(drvdata->base);
163 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
165 CS_UNLOCK(drvdata->base);
166 /* ATB trigger enable on direct writes to TRIG locations */
168 drvdata->base + STMSPTRIGCSR);
169 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
170 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
172 CS_LOCK(drvdata->base);
175 static void stm_enable_hw(struct stm_drvdata *drvdata)
177 if (drvdata->stmheer)
178 stm_hwevent_enable_hw(drvdata);
180 stm_port_enable_hw(drvdata);
182 CS_UNLOCK(drvdata->base);
184 /* 4096 byte between synchronisation packets */
185 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
186 writel_relaxed((drvdata->traceid << 16 | /* trace id */
187 0x02 | /* timestamp enable */
188 0x01), /* global STM enable */
189 drvdata->base + STMTCSR);
191 CS_LOCK(drvdata->base);
194 static int stm_enable(struct coresight_device *csdev,
195 struct perf_event *event, u32 mode)
198 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
200 if (mode != CS_MODE_SYSFS)
203 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
205 /* Someone is already using the tracer */
209 pm_runtime_get_sync(csdev->dev.parent);
211 spin_lock(&drvdata->spinlock);
212 stm_enable_hw(drvdata);
213 spin_unlock(&drvdata->spinlock);
215 dev_dbg(&csdev->dev, "STM tracing enabled\n");
219 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
221 CS_UNLOCK(drvdata->base);
223 writel_relaxed(0x0, drvdata->base + STMHEMCR);
224 writel_relaxed(0x0, drvdata->base + STMHEER);
225 writel_relaxed(0x0, drvdata->base + STMHETER);
227 CS_LOCK(drvdata->base);
230 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
232 CS_UNLOCK(drvdata->base);
234 writel_relaxed(0x0, drvdata->base + STMSPER);
235 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
237 CS_LOCK(drvdata->base);
240 static void stm_disable_hw(struct stm_drvdata *drvdata)
244 CS_UNLOCK(drvdata->base);
246 val = readl_relaxed(drvdata->base + STMTCSR);
247 val &= ~0x1; /* clear global STM enable [0] */
248 writel_relaxed(val, drvdata->base + STMTCSR);
250 CS_LOCK(drvdata->base);
252 stm_port_disable_hw(drvdata);
253 if (drvdata->stmheer)
254 stm_hwevent_disable_hw(drvdata);
257 static void stm_disable(struct coresight_device *csdev,
258 struct perf_event *event)
260 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
263 * For as long as the tracer isn't disabled another entity can't
264 * change its status. As such we can read the status here without
265 * fearing it will change under us.
267 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
268 spin_lock(&drvdata->spinlock);
269 stm_disable_hw(drvdata);
270 spin_unlock(&drvdata->spinlock);
272 /* Wait until the engine has completely stopped */
273 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
275 pm_runtime_put(csdev->dev.parent);
277 local_set(&drvdata->mode, CS_MODE_DISABLED);
278 dev_dbg(&csdev->dev, "STM tracing disabled\n");
282 static int stm_trace_id(struct coresight_device *csdev)
284 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
286 return drvdata->traceid;
289 static const struct coresight_ops_source stm_source_ops = {
290 .trace_id = stm_trace_id,
291 .enable = stm_enable,
292 .disable = stm_disable,
295 static const struct coresight_ops stm_cs_ops = {
296 .source_ops = &stm_source_ops,
299 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
301 return ((unsigned long)addr & (write_bytes - 1));
304 static void stm_send(void __iomem *addr, const void *data,
305 u32 size, u8 write_bytes)
309 if (stm_addr_unaligned(data, write_bytes)) {
310 memcpy(paload, data, size);
314 /* now we are 64bit/32bit aligned */
318 writeq_relaxed(*(u64 *)data, addr);
322 writel_relaxed(*(u32 *)data, addr);
325 writew_relaxed(*(u16 *)data, addr);
328 writeb_relaxed(*(u8 *)data, addr);
335 static int stm_generic_link(struct stm_data *stm_data,
336 unsigned int master, unsigned int channel)
338 struct stm_drvdata *drvdata = container_of(stm_data,
339 struct stm_drvdata, stm);
340 if (!drvdata || !drvdata->csdev)
343 return coresight_enable(drvdata->csdev);
346 static void stm_generic_unlink(struct stm_data *stm_data,
347 unsigned int master, unsigned int channel)
349 struct stm_drvdata *drvdata = container_of(stm_data,
350 struct stm_drvdata, stm);
351 if (!drvdata || !drvdata->csdev)
354 coresight_disable(drvdata->csdev);
358 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
359 unsigned int channel, unsigned int nr_chans)
361 struct stm_drvdata *drvdata = container_of(stm_data,
362 struct stm_drvdata, stm);
365 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
367 if (offset_in_page(addr) ||
368 offset_in_page(nr_chans * BYTES_PER_CHANNEL))
374 static long stm_generic_set_options(struct stm_data *stm_data,
376 unsigned int channel,
377 unsigned int nr_chans,
378 unsigned long options)
380 struct stm_drvdata *drvdata = container_of(stm_data,
381 struct stm_drvdata, stm);
382 if (!(drvdata && local_read(&drvdata->mode)))
385 if (channel >= drvdata->numsp)
389 case STM_OPTION_GUARANTEED:
390 set_bit(channel, drvdata->chs.guaranteed);
393 case STM_OPTION_INVARIANT:
394 clear_bit(channel, drvdata->chs.guaranteed);
404 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
406 unsigned int channel,
410 const unsigned char *payload)
412 void __iomem *ch_addr;
413 struct stm_drvdata *drvdata = container_of(stm_data,
414 struct stm_drvdata, stm);
415 unsigned int stm_flags;
417 if (!(drvdata && local_read(&drvdata->mode)))
420 if (channel >= drvdata->numsp)
423 ch_addr = stm_channel_addr(drvdata, channel);
425 stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
426 STM_FLAG_TIMESTAMPED : 0;
427 stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
428 STM_FLAG_GUARANTEED : 0;
430 if (size > drvdata->write_bytes)
431 size = drvdata->write_bytes;
433 size = rounddown_pow_of_two(size);
436 case STP_PACKET_FLAG:
437 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
440 * The generic STM core sets a size of '0' on flag packets.
441 * As such send a flag packet of size '1' and tell the
444 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
448 case STP_PACKET_DATA:
449 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
450 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
451 stm_send(ch_addr, payload, size,
452 drvdata->write_bytes);
462 static ssize_t hwevent_enable_show(struct device *dev,
463 struct device_attribute *attr, char *buf)
465 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
466 unsigned long val = drvdata->stmheer;
468 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
471 static ssize_t hwevent_enable_store(struct device *dev,
472 struct device_attribute *attr,
473 const char *buf, size_t size)
475 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
479 ret = kstrtoul(buf, 16, &val);
483 drvdata->stmheer = val;
484 /* HW event enable and trigger go hand in hand */
485 drvdata->stmheter = val;
489 static DEVICE_ATTR_RW(hwevent_enable);
491 static ssize_t hwevent_select_show(struct device *dev,
492 struct device_attribute *attr, char *buf)
494 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
495 unsigned long val = drvdata->stmhebsr;
497 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
500 static ssize_t hwevent_select_store(struct device *dev,
501 struct device_attribute *attr,
502 const char *buf, size_t size)
504 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
508 ret = kstrtoul(buf, 16, &val);
512 drvdata->stmhebsr = val;
516 static DEVICE_ATTR_RW(hwevent_select);
518 static ssize_t port_select_show(struct device *dev,
519 struct device_attribute *attr, char *buf)
521 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
524 if (!local_read(&drvdata->mode)) {
525 val = drvdata->stmspscr;
527 spin_lock(&drvdata->spinlock);
528 val = readl_relaxed(drvdata->base + STMSPSCR);
529 spin_unlock(&drvdata->spinlock);
532 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
535 static ssize_t port_select_store(struct device *dev,
536 struct device_attribute *attr,
537 const char *buf, size_t size)
539 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
540 unsigned long val, stmsper;
543 ret = kstrtoul(buf, 16, &val);
547 spin_lock(&drvdata->spinlock);
548 drvdata->stmspscr = val;
550 if (local_read(&drvdata->mode)) {
551 CS_UNLOCK(drvdata->base);
552 /* Process as per ARM's TRM recommendation */
553 stmsper = readl_relaxed(drvdata->base + STMSPER);
554 writel_relaxed(0x0, drvdata->base + STMSPER);
555 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
556 writel_relaxed(stmsper, drvdata->base + STMSPER);
557 CS_LOCK(drvdata->base);
559 spin_unlock(&drvdata->spinlock);
563 static DEVICE_ATTR_RW(port_select);
565 static ssize_t port_enable_show(struct device *dev,
566 struct device_attribute *attr, char *buf)
568 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
571 if (!local_read(&drvdata->mode)) {
572 val = drvdata->stmsper;
574 spin_lock(&drvdata->spinlock);
575 val = readl_relaxed(drvdata->base + STMSPER);
576 spin_unlock(&drvdata->spinlock);
579 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
582 static ssize_t port_enable_store(struct device *dev,
583 struct device_attribute *attr,
584 const char *buf, size_t size)
586 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
590 ret = kstrtoul(buf, 16, &val);
594 spin_lock(&drvdata->spinlock);
595 drvdata->stmsper = val;
597 if (local_read(&drvdata->mode)) {
598 CS_UNLOCK(drvdata->base);
599 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
600 CS_LOCK(drvdata->base);
602 spin_unlock(&drvdata->spinlock);
606 static DEVICE_ATTR_RW(port_enable);
608 static ssize_t traceid_show(struct device *dev,
609 struct device_attribute *attr, char *buf)
612 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
614 val = drvdata->traceid;
615 return sprintf(buf, "%#lx\n", val);
618 static ssize_t traceid_store(struct device *dev,
619 struct device_attribute *attr,
620 const char *buf, size_t size)
624 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
626 ret = kstrtoul(buf, 16, &val);
630 /* traceid field is 7bit wide on STM32 */
631 drvdata->traceid = val & 0x7f;
634 static DEVICE_ATTR_RW(traceid);
636 #define coresight_stm_reg(name, offset) \
637 coresight_simple_reg32(struct stm_drvdata, name, offset)
639 coresight_stm_reg(tcsr, STMTCSR);
640 coresight_stm_reg(tsfreqr, STMTSFREQR);
641 coresight_stm_reg(syncr, STMSYNCR);
642 coresight_stm_reg(sper, STMSPER);
643 coresight_stm_reg(spter, STMSPTER);
644 coresight_stm_reg(privmaskr, STMPRIVMASKR);
645 coresight_stm_reg(spscr, STMSPSCR);
646 coresight_stm_reg(spmscr, STMSPMSCR);
647 coresight_stm_reg(spfeat1r, STMSPFEAT1R);
648 coresight_stm_reg(spfeat2r, STMSPFEAT2R);
649 coresight_stm_reg(spfeat3r, STMSPFEAT3R);
650 coresight_stm_reg(devid, CORESIGHT_DEVID);
652 static struct attribute *coresight_stm_attrs[] = {
653 &dev_attr_hwevent_enable.attr,
654 &dev_attr_hwevent_select.attr,
655 &dev_attr_port_enable.attr,
656 &dev_attr_port_select.attr,
657 &dev_attr_traceid.attr,
661 static struct attribute *coresight_stm_mgmt_attrs[] = {
663 &dev_attr_tsfreqr.attr,
664 &dev_attr_syncr.attr,
666 &dev_attr_spter.attr,
667 &dev_attr_privmaskr.attr,
668 &dev_attr_spscr.attr,
669 &dev_attr_spmscr.attr,
670 &dev_attr_spfeat1r.attr,
671 &dev_attr_spfeat2r.attr,
672 &dev_attr_spfeat3r.attr,
673 &dev_attr_devid.attr,
677 static const struct attribute_group coresight_stm_group = {
678 .attrs = coresight_stm_attrs,
681 static const struct attribute_group coresight_stm_mgmt_group = {
682 .attrs = coresight_stm_mgmt_attrs,
686 static const struct attribute_group *coresight_stm_groups[] = {
687 &coresight_stm_group,
688 &coresight_stm_mgmt_group,
693 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
695 const char *name = NULL;
696 int index = 0, found = 0;
697 struct device_node *np = dev->of_node;
699 while (!of_property_read_string_index(np, "reg-names", index, &name)) {
700 if (strcmp("stm-stimulus-base", name)) {
705 /* We have a match and @index is where it's at */
713 return of_address_to_resource(np, index, res);
716 static inline int of_stm_get_stimulus_area(struct device *dev,
717 struct resource *res)
724 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
727 bool found_base = false;
728 struct resource_entry *rent;
731 struct acpi_device *adev = ACPI_COMPANION(dev);
733 rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
738 * The stimulus base for STM device must be listed as the second memory
739 * resource, followed by the programming base address as described in
740 * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
741 * document (DEN0067).
744 list_for_each_entry(rent, &res_list, node) {
745 if (resource_type(rent->res) != IORESOURCE_MEM)
756 acpi_dev_free_resource_list(&res_list);
760 static inline int acpi_stm_get_stimulus_area(struct device *dev,
761 struct resource *res)
767 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
769 struct fwnode_handle *fwnode = dev_fwnode(dev);
771 if (is_of_node(fwnode))
772 return of_stm_get_stimulus_area(dev, res);
773 else if (is_acpi_node(fwnode))
774 return acpi_stm_get_stimulus_area(dev, res);
778 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
782 if (!IS_ENABLED(CONFIG_64BIT))
785 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
788 * bit[15:12] represents the fundamental data size
792 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
795 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
799 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
801 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
802 * 32 stimulus ports are supported.
806 numsp = STM_32_CHANNEL;
810 static void stm_init_default_data(struct stm_drvdata *drvdata)
812 /* Don't use port selection */
813 drvdata->stmspscr = 0x0;
815 * Enable all channel regardless of their number. When port
816 * selection isn't used (see above) STMSPER applies to all
817 * 32 channel group available, hence setting all 32 bits to 1
819 drvdata->stmsper = ~0x0;
822 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
823 * anything equal to or higher than 0x70 is reserved. Since 0x00 is
824 * also reserved the STM trace ID needs to be higher than 0x00 and
827 drvdata->traceid = 0x1;
829 /* Set invariant transaction timing on all channels */
830 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
833 static void stm_init_generic_data(struct stm_drvdata *drvdata,
836 drvdata->stm.name = name;
839 * MasterIDs are assigned at HW design phase. As such the core is
840 * using a single master for interaction with this device.
842 drvdata->stm.sw_start = 1;
843 drvdata->stm.sw_end = 1;
844 drvdata->stm.hw_override = true;
845 drvdata->stm.sw_nchannels = drvdata->numsp;
846 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
847 drvdata->stm.packet = stm_generic_packet;
848 drvdata->stm.mmio_addr = stm_mmio_addr;
849 drvdata->stm.link = stm_generic_link;
850 drvdata->stm.unlink = stm_generic_unlink;
851 drvdata->stm.set_options = stm_generic_set_options;
854 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
858 unsigned long *guaranteed;
859 struct device *dev = &adev->dev;
860 struct coresight_platform_data *pdata = NULL;
861 struct stm_drvdata *drvdata;
862 struct resource *res = &adev->res;
863 struct resource ch_res;
865 struct coresight_desc desc = { 0 };
867 desc.name = coresight_alloc_device_name(&stm_devs, dev);
871 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
875 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
876 if (!IS_ERR(drvdata->atclk)) {
877 ret = clk_prepare_enable(drvdata->atclk);
881 dev_set_drvdata(dev, drvdata);
883 base = devm_ioremap_resource(dev, res);
885 return PTR_ERR(base);
886 drvdata->base = base;
888 ret = stm_get_stimulus_area(dev, &ch_res);
891 drvdata->chs.phys = ch_res.start;
893 base = devm_ioremap_resource(dev, &ch_res);
895 return PTR_ERR(base);
896 drvdata->chs.base = base;
898 drvdata->write_bytes = stm_fundamental_data_size(drvdata);
901 drvdata->numsp = boot_nr_channel;
903 drvdata->numsp = stm_num_stimulus_port(drvdata);
905 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
907 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
910 drvdata->chs.guaranteed = guaranteed;
912 spin_lock_init(&drvdata->spinlock);
914 stm_init_default_data(drvdata);
915 stm_init_generic_data(drvdata, desc.name);
917 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
919 "%s : stm_register_device failed, probing deferred\n",
921 return -EPROBE_DEFER;
924 pdata = coresight_get_platform_data(dev);
926 ret = PTR_ERR(pdata);
929 adev->dev.platform_data = pdata;
931 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
932 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
933 desc.ops = &stm_cs_ops;
936 desc.groups = coresight_stm_groups;
937 drvdata->csdev = coresight_register(&desc);
938 if (IS_ERR(drvdata->csdev)) {
939 ret = PTR_ERR(drvdata->csdev);
943 pm_runtime_put(&adev->dev);
945 dev_info(&drvdata->csdev->dev, "%s initialized\n",
946 (char *)coresight_get_uci_data(id));
950 stm_unregister_device(&drvdata->stm);
954 static void stm_remove(struct amba_device *adev)
956 struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
958 coresight_unregister(drvdata->csdev);
960 stm_unregister_device(&drvdata->stm);
964 static int stm_runtime_suspend(struct device *dev)
966 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
968 if (drvdata && !IS_ERR(drvdata->atclk))
969 clk_disable_unprepare(drvdata->atclk);
974 static int stm_runtime_resume(struct device *dev)
976 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
978 if (drvdata && !IS_ERR(drvdata->atclk))
979 clk_prepare_enable(drvdata->atclk);
985 static const struct dev_pm_ops stm_dev_pm_ops = {
986 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
989 static const struct amba_id stm_ids[] = {
990 CS_AMBA_ID_DATA(0x000bb962, "STM32"),
991 CS_AMBA_ID_DATA(0x000bb963, "STM500"),
995 MODULE_DEVICE_TABLE(amba, stm_ids);
997 static struct amba_driver stm_driver = {
999 .name = "coresight-stm",
1000 .owner = THIS_MODULE,
1001 .pm = &stm_dev_pm_ops,
1002 .suppress_bind_attrs = true,
1005 .remove = stm_remove,
1006 .id_table = stm_ids,
1009 module_amba_driver(stm_driver);
1011 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1012 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
1013 MODULE_LICENSE("GPL v2");