drivers/hwtracing/coresight/coresight-stm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   4  *
   5  * Description: CoreSight System Trace Macrocell driver
   6  *
   7  * Initial implementation by Pratik Patel
   8  * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
   9  *
  10  * Serious refactoring, code cleanup and upgrading to the Coresight upstream
  11  * framework by Mathieu Poirier
  12  * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
  13  *
  14  * Guaranteed timing and support for various packet type coming from the
  15  * generic STM API by Chunyan Zhang
  16  * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
  17  */
  18 #include <asm/local.h>
  19 #include <linux/acpi.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/bitmap.h>
  22 #include <linux/clk.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-stm.h>
  25 #include <linux/err.h>
  26 #include <linux/kernel.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/of_address.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/stm.h>
  32
  33 #include "coresight-priv.h"
  34
  35 #define STMDMASTARTR                    0xc04
  36 #define STMDMASTOPR                     0xc08
  37 #define STMDMASTATR                     0xc0c
  38 #define STMDMACTLR                      0xc10
  39 #define STMDMAIDR                       0xcfc
  40 #define STMHEER                         0xd00
  41 #define STMHETER                        0xd20
  42 #define STMHEBSR                        0xd60
  43 #define STMHEMCR                        0xd64
  44 #define STMHEMASTR                      0xdf4
  45 #define STMHEFEAT1R                     0xdf8
  46 #define STMHEIDR                        0xdfc
  47 #define STMSPER                         0xe00
  48 #define STMSPTER                        0xe20
  49 #define STMPRIVMASKR                    0xe40
  50 #define STMSPSCR                        0xe60
  51 #define STMSPMSCR                       0xe64
  52 #define STMSPOVERRIDER                  0xe68
  53 #define STMSPMOVERRIDER                 0xe6c
  54 #define STMSPTRIGCSR                    0xe70
  55 #define STMTCSR                         0xe80
  56 #define STMTSSTIMR                      0xe84
  57 #define STMTSFREQR                      0xe8c
  58 #define STMSYNCR                        0xe90
  59 #define STMAUXCR                        0xe94
  60 #define STMSPFEAT1R                     0xea0
  61 #define STMSPFEAT2R                     0xea4
  62 #define STMSPFEAT3R                     0xea8
  63 #define STMITTRIGGER                    0xee8
  64 #define STMITATBDATA0                   0xeec
  65 #define STMITATBCTR2                    0xef0
  66 #define STMITATBID                      0xef4
  67 #define STMITATBCTR0                    0xef8
  68
  69 #define STM_32_CHANNEL                  32
  70 #define BYTES_PER_CHANNEL               256
  71 #define STM_TRACE_BUF_SIZE              4096
  72 #define STM_SW_MASTER_END               127
  73
  74 /* Register bit definition */
  75 #define STMTCSR_BUSY_BIT                23
  76 /* Reserve the first 10 channels for kernel usage */
  77 #define STM_CHANNEL_OFFSET              0
  78
  79 enum stm_pkt_type {
  80         STM_PKT_TYPE_DATA       = 0x98,
  81         STM_PKT_TYPE_FLAG       = 0xE8,
  82         STM_PKT_TYPE_TRIG       = 0xF8,
  83 };
  84
  85 #define stm_channel_addr(drvdata, ch)   (drvdata->chs.base +    \
  86                                         (ch * BYTES_PER_CHANNEL))
  87 #define stm_channel_off(type, opts)     (type & ~opts)
  88
  89 static int boot_nr_channel;
  90
  91 /*
  92  * Not really modular but using module_param is the easiest way to
  93  * remain consistent with existing use cases for now.
  94  */
  95 module_param_named(
  96         boot_nr_channel, boot_nr_channel, int, S_IRUGO
  97 );
  98
  99 /**
 100  * struct channel_space - central management entity for extended ports
 101  * @base:               memory mapped base address where channels start.
 102  * @phys:               physical base address of channel region.
 103  * @guaraneed:          is the channel delivery guaranteed.
 104  */
 105 struct channel_space {
 106         void __iomem            *base;
 107         phys_addr_t             phys;
 108         unsigned long           *guaranteed;
 109 };
 110
 111 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
 112
 113 /**
 114  * struct stm_drvdata - specifics associated to an STM component
 115  * @base:               memory mapped base address for this component.
 116  * @atclk:              optional clock for the core parts of the STM.
 117  * @csdev:              component vitals needed by the framework.
 118  * @spinlock:           only one at a time pls.
 119  * @chs:                the channels accociated to this STM.
 120  * @stm:                structure associated to the generic STM interface.
 121  * @mode:               this tracer's mode, i.e sysFS, or disabled.
 122  * @traceid:            value of the current ID for this component.
 123  * @write_bytes:        Maximus bytes this STM can write at a time.
 124  * @stmsper:            settings for register STMSPER.
 125  * @stmspscr:           settings for register STMSPSCR.
 126  * @numsp:              the total number of stimulus port support by this STM.
 127  * @stmheer:            settings for register STMHEER.
 128  * @stmheter:           settings for register STMHETER.
 129  * @stmhebsr:           settings for register STMHEBSR.
 130  */
 131 struct stm_drvdata {
 132         void __iomem            *base;
 133         struct clk              *atclk;
 134         struct coresight_device *csdev;
 135         spinlock_t              spinlock;
 136         struct channel_space    chs;
 137         struct stm_data         stm;
 138         local_t                 mode;
 139         u8                      traceid;
 140         u32                     write_bytes;
 141         u32                     stmsper;
 142         u32                     stmspscr;
 143         u32                     numsp;
 144         u32                     stmheer;
 145         u32                     stmheter;
 146         u32                     stmhebsr;
 147 };
 148
 149 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
 150 {
 151         CS_UNLOCK(drvdata->base);
 152
 153         writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
 154         writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
 155         writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
 156         writel_relaxed(0x01 |   /* Enable HW event tracing */
 157                        0x04,    /* Error detection on event tracing */
 158                        drvdata->base + STMHEMCR);
 159
 160         CS_LOCK(drvdata->base);
 161 }
 162
 163 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
 164 {
 165         CS_UNLOCK(drvdata->base);
 166         /* ATB trigger enable on direct writes to TRIG locations */
 167         writel_relaxed(0x10,
 168                        drvdata->base + STMSPTRIGCSR);
 169         writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 170         writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 171
 172         CS_LOCK(drvdata->base);
 173 }
 174
 175 static void stm_enable_hw(struct stm_drvdata *drvdata)
 176 {
 177         if (drvdata->stmheer)
 178                 stm_hwevent_enable_hw(drvdata);
 179
 180         stm_port_enable_hw(drvdata);
 181
 182         CS_UNLOCK(drvdata->base);
 183
 184         /* 4096 byte between synchronisation packets */
 185         writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
 186         writel_relaxed((drvdata->traceid << 16 | /* trace id */
 187                         0x02 |                   /* timestamp enable */
 188                         0x01),                   /* global STM enable */
 189                         drvdata->base + STMTCSR);
 190
 191         CS_LOCK(drvdata->base);
 192 }
 193
 194 static int stm_enable(struct coresight_device *csdev,
 195                       struct perf_event *event, u32 mode)
 196 {
 197         u32 val;
 198         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 199
 200         if (mode != CS_MODE_SYSFS)
 201                 return -EINVAL;
 202
 203         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 204
 205         /* Someone is already using the tracer */
 206         if (val)
 207                 return -EBUSY;
 208
 209         pm_runtime_get_sync(csdev->dev.parent);
 210
 211         spin_lock(&drvdata->spinlock);
 212         stm_enable_hw(drvdata);
 213         spin_unlock(&drvdata->spinlock);
 214
 215         dev_dbg(&csdev->dev, "STM tracing enabled\n");
 216         return 0;
 217 }
 218
 219 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
 220 {
 221         CS_UNLOCK(drvdata->base);
 222
 223         writel_relaxed(0x0, drvdata->base + STMHEMCR);
 224         writel_relaxed(0x0, drvdata->base + STMHEER);
 225         writel_relaxed(0x0, drvdata->base + STMHETER);
 226
 227         CS_LOCK(drvdata->base);
 228 }
 229
 230 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
 231 {
 232         CS_UNLOCK(drvdata->base);
 233
 234         writel_relaxed(0x0, drvdata->base + STMSPER);
 235         writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
 236
 237         CS_LOCK(drvdata->base);
 238 }
 239
 240 static void stm_disable_hw(struct stm_drvdata *drvdata)
 241 {
 242         u32 val;
 243
 244         CS_UNLOCK(drvdata->base);
 245
 246         val = readl_relaxed(drvdata->base + STMTCSR);
 247         val &= ~0x1; /* clear global STM enable [0] */
 248         writel_relaxed(val, drvdata->base + STMTCSR);
 249
 250         CS_LOCK(drvdata->base);
 251
 252         stm_port_disable_hw(drvdata);
 253         if (drvdata->stmheer)
 254                 stm_hwevent_disable_hw(drvdata);
 255 }
 256
 257 static void stm_disable(struct coresight_device *csdev,
 258                         struct perf_event *event)
 259 {
 260         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 261
 262         /*
 263          * For as long as the tracer isn't disabled another entity can't
 264          * change its status.  As such we can read the status here without
 265          * fearing it will change under us.
 266          */
 267         if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
 268                 spin_lock(&drvdata->spinlock);
 269                 stm_disable_hw(drvdata);
 270                 spin_unlock(&drvdata->spinlock);
 271
 272                 /* Wait until the engine has completely stopped */
 273                 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
 274
 275                 pm_runtime_put(csdev->dev.parent);
 276
 277                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 278                 dev_dbg(&csdev->dev, "STM tracing disabled\n");
 279         }
 280 }
 281
 282 static int stm_trace_id(struct coresight_device *csdev)
 283 {
 284         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 285
 286         return drvdata->traceid;
 287 }
 288
 289 static const struct coresight_ops_source stm_source_ops = {
 290         .trace_id       = stm_trace_id,
 291         .enable         = stm_enable,
 292         .disable        = stm_disable,
 293 };
 294
 295 static const struct coresight_ops stm_cs_ops = {
 296         .source_ops     = &stm_source_ops,
 297 };
 298
 299 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
 300 {
 301         return ((unsigned long)addr & (write_bytes - 1));
 302 }
 303
 304 static void stm_send(void __iomem *addr, const void *data,
 305                      u32 size, u8 write_bytes)
 306 {
 307         u8 paload[8];
 308
 309         if (stm_addr_unaligned(data, write_bytes)) {
 310                 memcpy(paload, data, size);
 311                 data = paload;
 312         }
 313
 314         /* now we are 64bit/32bit aligned */
 315         switch (size) {
 316 #ifdef CONFIG_64BIT
 317         case 8:
 318                 writeq_relaxed(*(u64 *)data, addr);
 319                 break;
 320 #endif
 321         case 4:
 322                 writel_relaxed(*(u32 *)data, addr);
 323                 break;
 324         case 2:
 325                 writew_relaxed(*(u16 *)data, addr);
 326                 break;
 327         case 1:
 328                 writeb_relaxed(*(u8 *)data, addr);
 329                 break;
 330         default:
 331                 break;
 332         }
 333 }
 334
 335 static int stm_generic_link(struct stm_data *stm_data,
 336                             unsigned int master,  unsigned int channel)
 337 {
 338         struct stm_drvdata *drvdata = container_of(stm_data,
 339                                                    struct stm_drvdata, stm);
 340         if (!drvdata || !drvdata->csdev)
 341                 return -EINVAL;
 342
 343         return coresight_enable(drvdata->csdev);
 344 }
 345
 346 static void stm_generic_unlink(struct stm_data *stm_data,
 347                                unsigned int master,  unsigned int channel)
 348 {
 349         struct stm_drvdata *drvdata = container_of(stm_data,
 350                                                    struct stm_drvdata, stm);
 351         if (!drvdata || !drvdata->csdev)
 352                 return;
 353
 354         coresight_disable(drvdata->csdev);
 355 }
 356
 357 static phys_addr_t
 358 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
 359               unsigned int channel, unsigned int nr_chans)
 360 {
 361         struct stm_drvdata *drvdata = container_of(stm_data,
 362                                                    struct stm_drvdata, stm);
 363         phys_addr_t addr;
 364
 365         addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
 366
 367         if (offset_in_page(addr) ||
 368             offset_in_page(nr_chans * BYTES_PER_CHANNEL))
 369                 return 0;
 370
 371         return addr;
 372 }
 373
 374 static long stm_generic_set_options(struct stm_data *stm_data,
 375                                     unsigned int master,
 376                                     unsigned int channel,
 377                                     unsigned int nr_chans,
 378                                     unsigned long options)
 379 {
 380         struct stm_drvdata *drvdata = container_of(stm_data,
 381                                                    struct stm_drvdata, stm);
 382         if (!(drvdata && local_read(&drvdata->mode)))
 383                 return -EINVAL;
 384
 385         if (channel >= drvdata->numsp)
 386                 return -EINVAL;
 387
 388         switch (options) {
 389         case STM_OPTION_GUARANTEED:
 390                 set_bit(channel, drvdata->chs.guaranteed);
 391                 break;
 392
 393         case STM_OPTION_INVARIANT:
 394                 clear_bit(channel, drvdata->chs.guaranteed);
 395                 break;
 396
 397         default:
 398                 return -EINVAL;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
 405                                   unsigned int master,
 406                                   unsigned int channel,
 407                                   unsigned int packet,
 408                                   unsigned int flags,
 409                                   unsigned int size,
 410                                   const unsigned char *payload)
 411 {
 412         void __iomem *ch_addr;
 413         struct stm_drvdata *drvdata = container_of(stm_data,
 414                                                    struct stm_drvdata, stm);
 415         unsigned int stm_flags;
 416
 417         if (!(drvdata && local_read(&drvdata->mode)))
 418                 return -EACCES;
 419
 420         if (channel >= drvdata->numsp)
 421                 return -EINVAL;
 422
 423         ch_addr = stm_channel_addr(drvdata, channel);
 424
 425         stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
 426                         STM_FLAG_TIMESTAMPED : 0;
 427         stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
 428                            STM_FLAG_GUARANTEED : 0;
 429
 430         if (size > drvdata->write_bytes)
 431                 size = drvdata->write_bytes;
 432         else
 433                 size = rounddown_pow_of_two(size);
 434
 435         switch (packet) {
 436         case STP_PACKET_FLAG:
 437                 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
 438
 439                 /*
 440                  * The generic STM core sets a size of '0' on flag packets.
 441                  * As such send a flag packet of size '1' and tell the
 442                  * core we did so.
 443                  */
 444                 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
 445                 size = 1;
 446                 break;
 447
 448         case STP_PACKET_DATA:
 449                 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
 450                 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
 451                 stm_send(ch_addr, payload, size,
 452                                 drvdata->write_bytes);
 453                 break;
 454
 455         default:
 456                 return -ENOTSUPP;
 457         }
 458
 459         return size;
 460 }
 461
 462 static ssize_t hwevent_enable_show(struct device *dev,
 463                                    struct device_attribute *attr, char *buf)
 464 {
 465         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 466         unsigned long val = drvdata->stmheer;
 467
 468         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 469 }
 470
 471 static ssize_t hwevent_enable_store(struct device *dev,
 472                                     struct device_attribute *attr,
 473                                     const char *buf, size_t size)
 474 {
 475         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 476         unsigned long val;
 477         int ret = 0;
 478
 479         ret = kstrtoul(buf, 16, &val);
 480         if (ret)
 481                 return -EINVAL;
 482
 483         drvdata->stmheer = val;
 484         /* HW event enable and trigger go hand in hand */
 485         drvdata->stmheter = val;
 486
 487         return size;
 488 }
 489 static DEVICE_ATTR_RW(hwevent_enable);
 490
 491 static ssize_t hwevent_select_show(struct device *dev,
 492                                    struct device_attribute *attr, char *buf)
 493 {
 494         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 495         unsigned long val = drvdata->stmhebsr;
 496
 497         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 498 }
 499
 500 static ssize_t hwevent_select_store(struct device *dev,
 501                                     struct device_attribute *attr,
 502                                     const char *buf, size_t size)
 503 {
 504         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 505         unsigned long val;
 506         int ret = 0;
 507
 508         ret = kstrtoul(buf, 16, &val);
 509         if (ret)
 510                 return -EINVAL;
 511
 512         drvdata->stmhebsr = val;
 513
 514         return size;
 515 }
 516 static DEVICE_ATTR_RW(hwevent_select);
 517
 518 static ssize_t port_select_show(struct device *dev,
 519                                 struct device_attribute *attr, char *buf)
 520 {
 521         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 522         unsigned long val;
 523
 524         if (!local_read(&drvdata->mode)) {
 525                 val = drvdata->stmspscr;
 526         } else {
 527                 spin_lock(&drvdata->spinlock);
 528                 val = readl_relaxed(drvdata->base + STMSPSCR);
 529                 spin_unlock(&drvdata->spinlock);
 530         }
 531
 532         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 533 }
 534
 535 static ssize_t port_select_store(struct device *dev,
 536                                  struct device_attribute *attr,
 537                                  const char *buf, size_t size)
 538 {
 539         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 540         unsigned long val, stmsper;
 541         int ret = 0;
 542
 543         ret = kstrtoul(buf, 16, &val);
 544         if (ret)
 545                 return ret;
 546
 547         spin_lock(&drvdata->spinlock);
 548         drvdata->stmspscr = val;
 549
 550         if (local_read(&drvdata->mode)) {
 551                 CS_UNLOCK(drvdata->base);
 552                 /* Process as per ARM's TRM recommendation */
 553                 stmsper = readl_relaxed(drvdata->base + STMSPER);
 554                 writel_relaxed(0x0, drvdata->base + STMSPER);
 555                 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 556                 writel_relaxed(stmsper, drvdata->base + STMSPER);
 557                 CS_LOCK(drvdata->base);
 558         }
 559         spin_unlock(&drvdata->spinlock);
 560
 561         return size;
 562 }
 563 static DEVICE_ATTR_RW(port_select);
 564
 565 static ssize_t port_enable_show(struct device *dev,
 566                                 struct device_attribute *attr, char *buf)
 567 {
 568         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 569         unsigned long val;
 570
 571         if (!local_read(&drvdata->mode)) {
 572                 val = drvdata->stmsper;
 573         } else {
 574                 spin_lock(&drvdata->spinlock);
 575                 val = readl_relaxed(drvdata->base + STMSPER);
 576                 spin_unlock(&drvdata->spinlock);
 577         }
 578
 579         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 580 }
 581
 582 static ssize_t port_enable_store(struct device *dev,
 583                                  struct device_attribute *attr,
 584                                  const char *buf, size_t size)
 585 {
 586         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 587         unsigned long val;
 588         int ret = 0;
 589
 590         ret = kstrtoul(buf, 16, &val);
 591         if (ret)
 592                 return ret;
 593
 594         spin_lock(&drvdata->spinlock);
 595         drvdata->stmsper = val;
 596
 597         if (local_read(&drvdata->mode)) {
 598                 CS_UNLOCK(drvdata->base);
 599                 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 600                 CS_LOCK(drvdata->base);
 601         }
 602         spin_unlock(&drvdata->spinlock);
 603
 604         return size;
 605 }
 606 static DEVICE_ATTR_RW(port_enable);
 607
 608 static ssize_t traceid_show(struct device *dev,
 609                             struct device_attribute *attr, char *buf)
 610 {
 611         unsigned long val;
 612         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 613
 614         val = drvdata->traceid;
 615         return sprintf(buf, "%#lx\n", val);
 616 }
 617
 618 static ssize_t traceid_store(struct device *dev,
 619                              struct device_attribute *attr,
 620                              const char *buf, size_t size)
 621 {
 622         int ret;
 623         unsigned long val;
 624         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 625
 626         ret = kstrtoul(buf, 16, &val);
 627         if (ret)
 628                 return ret;
 629
 630         /* traceid field is 7bit wide on STM32 */
 631         drvdata->traceid = val & 0x7f;
 632         return size;
 633 }
 634 static DEVICE_ATTR_RW(traceid);
 635
 636 #define coresight_stm_reg(name, offset) \
 637         coresight_simple_reg32(struct stm_drvdata, name, offset)
 638
 639 coresight_stm_reg(tcsr, STMTCSR);
 640 coresight_stm_reg(tsfreqr, STMTSFREQR);
 641 coresight_stm_reg(syncr, STMSYNCR);
 642 coresight_stm_reg(sper, STMSPER);
 643 coresight_stm_reg(spter, STMSPTER);
 644 coresight_stm_reg(privmaskr, STMPRIVMASKR);
 645 coresight_stm_reg(spscr, STMSPSCR);
 646 coresight_stm_reg(spmscr, STMSPMSCR);
 647 coresight_stm_reg(spfeat1r, STMSPFEAT1R);
 648 coresight_stm_reg(spfeat2r, STMSPFEAT2R);
 649 coresight_stm_reg(spfeat3r, STMSPFEAT3R);
 650 coresight_stm_reg(devid, CORESIGHT_DEVID);
 651
 652 static struct attribute *coresight_stm_attrs[] = {
 653         &dev_attr_hwevent_enable.attr,
 654         &dev_attr_hwevent_select.attr,
 655         &dev_attr_port_enable.attr,
 656         &dev_attr_port_select.attr,
 657         &dev_attr_traceid.attr,
 658         NULL,
 659 };
 660
 661 static struct attribute *coresight_stm_mgmt_attrs[] = {
 662         &dev_attr_tcsr.attr,
 663         &dev_attr_tsfreqr.attr,
 664         &dev_attr_syncr.attr,
 665         &dev_attr_sper.attr,
 666         &dev_attr_spter.attr,
 667         &dev_attr_privmaskr.attr,
 668         &dev_attr_spscr.attr,
 669         &dev_attr_spmscr.attr,
 670         &dev_attr_spfeat1r.attr,
 671         &dev_attr_spfeat2r.attr,
 672         &dev_attr_spfeat3r.attr,
 673         &dev_attr_devid.attr,
 674         NULL,
 675 };
 676
 677 static const struct attribute_group coresight_stm_group = {
 678         .attrs = coresight_stm_attrs,
 679 };
 680
 681 static const struct attribute_group coresight_stm_mgmt_group = {
 682         .attrs = coresight_stm_mgmt_attrs,
 683         .name = "mgmt",
 684 };
 685
 686 static const struct attribute_group *coresight_stm_groups[] = {
 687         &coresight_stm_group,
 688         &coresight_stm_mgmt_group,
 689         NULL,
 690 };
 691
 692 #ifdef CONFIG_OF
 693 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
 694 {
 695         const char *name = NULL;
 696         int index = 0, found = 0;
 697         struct device_node *np = dev->of_node;
 698
 699         while (!of_property_read_string_index(np, "reg-names", index, &name)) {
 700                 if (strcmp("stm-stimulus-base", name)) {
 701                         index++;
 702                         continue;
 703                 }
 704
 705                 /* We have a match and @index is where it's at */
 706                 found = 1;
 707                 break;
 708         }
 709
 710         if (!found)
 711                 return -EINVAL;
 712
 713         return of_address_to_resource(np, index, res);
 714 }
 715 #else
 716 static inline int of_stm_get_stimulus_area(struct device *dev,
 717                                            struct resource *res)
 718 {
 719         return -ENOENT;
 720 }
 721 #endif
 722
 723 #ifdef CONFIG_ACPI
 724 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
 725 {
 726         int rc;
 727         bool found_base = false;
 728         struct resource_entry *rent;
 729         LIST_HEAD(res_list);
 730
 731         struct acpi_device *adev = ACPI_COMPANION(dev);
 732
 733         rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
 734         if (rc < 0)
 735                 return rc;
 736
 737         /*
 738          * The stimulus base for STM device must be listed as the second memory
 739          * resource, followed by the programming base address as described in
 740          * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
 741          * document (DEN0067).
 742          */
 743         rc = -ENOENT;
 744         list_for_each_entry(rent, &res_list, node) {
 745                 if (resource_type(rent->res) != IORESOURCE_MEM)
 746                         continue;
 747                 if (found_base) {
 748                         *res = *rent->res;
 749                         rc = 0;
 750                         break;
 751                 }
 752
 753                 found_base = true;
 754         }
 755
 756         acpi_dev_free_resource_list(&res_list);
 757         return rc;
 758 }
 759 #else
 760 static inline int acpi_stm_get_stimulus_area(struct device *dev,
 761                                              struct resource *res)
 762 {
 763         return -ENOENT;
 764 }
 765 #endif
 766
 767 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
 768 {
 769         struct fwnode_handle *fwnode = dev_fwnode(dev);
 770
 771         if (is_of_node(fwnode))
 772                 return of_stm_get_stimulus_area(dev, res);
 773         else if (is_acpi_node(fwnode))
 774                 return acpi_stm_get_stimulus_area(dev, res);
 775         return -ENOENT;
 776 }
 777
 778 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
 779 {
 780         u32 stmspfeat2r;
 781
 782         if (!IS_ENABLED(CONFIG_64BIT))
 783                 return 4;
 784
 785         stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
 786
 787         /*
 788          * bit[15:12] represents the fundamental data size
 789          * 0 - 32-bit data
 790          * 1 - 64-bit data
 791          */
 792         return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
 793 }
 794
 795 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
 796 {
 797         u32 numsp;
 798
 799         numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 800         /*
 801          * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
 802          * 32 stimulus ports are supported.
 803          */
 804         numsp &= 0x1ffff;
 805         if (!numsp)
 806                 numsp = STM_32_CHANNEL;
 807         return numsp;
 808 }
 809
 810 static void stm_init_default_data(struct stm_drvdata *drvdata)
 811 {
 812         /* Don't use port selection */
 813         drvdata->stmspscr = 0x0;
 814         /*
 815          * Enable all channel regardless of their number.  When port
 816          * selection isn't used (see above) STMSPER applies to all
 817          * 32 channel group available, hence setting all 32 bits to 1
 818          */
 819         drvdata->stmsper = ~0x0;
 820
 821         /*
 822          * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
 823          * anything equal to or higher than 0x70 is reserved.  Since 0x00 is
 824          * also reserved the STM trace ID needs to be higher than 0x00 and
 825          * lowner than 0x10.
 826          */
 827         drvdata->traceid = 0x1;
 828
 829         /* Set invariant transaction timing on all channels */
 830         bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
 831 }
 832
 833 static void stm_init_generic_data(struct stm_drvdata *drvdata,
 834                                   const char *name)
 835 {
 836         drvdata->stm.name = name;
 837
 838         /*
 839          * MasterIDs are assigned at HW design phase. As such the core is
 840          * using a single master for interaction with this device.
 841          */
 842         drvdata->stm.sw_start = 1;
 843         drvdata->stm.sw_end = 1;
 844         drvdata->stm.hw_override = true;
 845         drvdata->stm.sw_nchannels = drvdata->numsp;
 846         drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
 847         drvdata->stm.packet = stm_generic_packet;
 848         drvdata->stm.mmio_addr = stm_mmio_addr;
 849         drvdata->stm.link = stm_generic_link;
 850         drvdata->stm.unlink = stm_generic_unlink;
 851         drvdata->stm.set_options = stm_generic_set_options;
 852 }
 853
 854 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
 855 {
 856         int ret;
 857         void __iomem *base;
 858         unsigned long *guaranteed;
 859         struct device *dev = &adev->dev;
 860         struct coresight_platform_data *pdata = NULL;
 861         struct stm_drvdata *drvdata;
 862         struct resource *res = &adev->res;
 863         struct resource ch_res;
 864         size_t bitmap_size;
 865         struct coresight_desc desc = { 0 };
 866
 867         desc.name = coresight_alloc_device_name(&stm_devs, dev);
 868         if (!desc.name)
 869                 return -ENOMEM;
 870
 871         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 872         if (!drvdata)
 873                 return -ENOMEM;
 874
 875         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 876         if (!IS_ERR(drvdata->atclk)) {
 877                 ret = clk_prepare_enable(drvdata->atclk);
 878                 if (ret)
 879                         return ret;
 880         }
 881         dev_set_drvdata(dev, drvdata);
 882
 883         base = devm_ioremap_resource(dev, res);
 884         if (IS_ERR(base))
 885                 return PTR_ERR(base);
 886         drvdata->base = base;
 887
 888         ret = stm_get_stimulus_area(dev, &ch_res);
 889         if (ret)
 890                 return ret;
 891         drvdata->chs.phys = ch_res.start;
 892
 893         base = devm_ioremap_resource(dev, &ch_res);
 894         if (IS_ERR(base))
 895                 return PTR_ERR(base);
 896         drvdata->chs.base = base;
 897
 898         drvdata->write_bytes = stm_fundamental_data_size(drvdata);
 899
 900         if (boot_nr_channel)
 901                 drvdata->numsp = boot_nr_channel;
 902         else
 903                 drvdata->numsp = stm_num_stimulus_port(drvdata);
 904
 905         bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
 906
 907         guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
 908         if (!guaranteed)
 909                 return -ENOMEM;
 910         drvdata->chs.guaranteed = guaranteed;
 911
 912         spin_lock_init(&drvdata->spinlock);
 913
 914         stm_init_default_data(drvdata);
 915         stm_init_generic_data(drvdata, desc.name);
 916
 917         if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
 918                 dev_info(dev,
 919                          "%s : stm_register_device failed, probing deferred\n",
 920                          desc.name);
 921                 return -EPROBE_DEFER;
 922         }
 923
 924         pdata = coresight_get_platform_data(dev);
 925         if (IS_ERR(pdata)) {
 926                 ret = PTR_ERR(pdata);
 927                 goto stm_unregister;
 928         }
 929         adev->dev.platform_data = pdata;
 930
 931         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
 932         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
 933         desc.ops = &stm_cs_ops;
 934         desc.pdata = pdata;
 935         desc.dev = dev;
 936         desc.groups = coresight_stm_groups;
 937         drvdata->csdev = coresight_register(&desc);
 938         if (IS_ERR(drvdata->csdev)) {
 939                 ret = PTR_ERR(drvdata->csdev);
 940                 goto stm_unregister;
 941         }
 942
 943         pm_runtime_put(&adev->dev);
 944
 945         dev_info(&drvdata->csdev->dev, "%s initialized\n",
 946                  (char *)coresight_get_uci_data(id));
 947         return 0;
 948
 949 stm_unregister:
 950         stm_unregister_device(&drvdata->stm);
 951         return ret;
 952 }
 953
 954 static void stm_remove(struct amba_device *adev)
 955 {
 956         struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
 957
 958         coresight_unregister(drvdata->csdev);
 959
 960         stm_unregister_device(&drvdata->stm);
 961 }
 962
 963 #ifdef CONFIG_PM
 964 static int stm_runtime_suspend(struct device *dev)
 965 {
 966         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 967
 968         if (drvdata && !IS_ERR(drvdata->atclk))
 969                 clk_disable_unprepare(drvdata->atclk);
 970
 971         return 0;
 972 }
 973
 974 static int stm_runtime_resume(struct device *dev)
 975 {
 976         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 977
 978         if (drvdata && !IS_ERR(drvdata->atclk))
 979                 clk_prepare_enable(drvdata->atclk);
 980
 981         return 0;
 982 }
 983 #endif
 984
 985 static const struct dev_pm_ops stm_dev_pm_ops = {
 986         SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
 987 };
 988
 989 static const struct amba_id stm_ids[] = {
 990         CS_AMBA_ID_DATA(0x000bb962, "STM32"),
 991         CS_AMBA_ID_DATA(0x000bb963, "STM500"),
 992         { 0, 0},
 993 };
 994
 995 MODULE_DEVICE_TABLE(amba, stm_ids);
 996
 997 static struct amba_driver stm_driver = {
 998         .drv = {
 999                 .name   = "coresight-stm",
1000                 .owner  = THIS_MODULE,
1001                 .pm     = &stm_dev_pm_ops,
1002                 .suppress_bind_attrs = true,
1003         },
1004         .probe          = stm_probe,
1005         .remove         = stm_remove,
1006         .id_table       = stm_ids,
1007 };
1008
1009 module_amba_driver(stm_driver);
1010
1011 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1012 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
1013 MODULE_LICENSE("GPL v2");