drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/coresight-pmu.h>
  30 #include <linux/pm_wakeup.h>
  31 #include <linux/amba/bus.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/uaccess.h>
  34 #include <linux/perf_event.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/sections.h>
  37 #include <asm/local.h>
  38 #include <asm/virt.h>
  39
  40 #include "coresight-etm4x.h"
  41 #include "coresight-etm-perf.h"
  42
  43 static int boot_enable;
  44 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  45
  46 /* The number of ETMv4 currently registered */
  47 static int etm4_count;
  48 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  49 static void etm4_set_default_config(struct etmv4_config *config);
  50 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  51                                   struct perf_event *event);
  52
  53 static enum cpuhp_state hp_online;
  54
  55 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  56 {
  57         /* Writing any value to ETMOSLAR unlocks the trace registers */
  58         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  59         drvdata->os_unlock = true;
  60         isb();
  61 }
  62
  63 static bool etm4_arch_supported(u8 arch)
  64 {
  65         /* Mask out the minor version number */
  66         switch (arch & 0xf0) {
  67         case ETM_ARCH_V4:
  68                 break;
  69         default:
  70                 return false;
  71         }
  72         return true;
  73 }
  74
  75 static int etm4_cpu_id(struct coresight_device *csdev)
  76 {
  77         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  78
  79         return drvdata->cpu;
  80 }
  81
  82 static int etm4_trace_id(struct coresight_device *csdev)
  83 {
  84         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  85
  86         return drvdata->trcid;
  87 }
  88
  89 static void etm4_enable_hw(void *info)
  90 {
  91         int i;
  92         struct etmv4_drvdata *drvdata = info;
  93         struct etmv4_config *config = &drvdata->config;
  94
  95         CS_UNLOCK(drvdata->base);
  96
  97         etm4_os_unlock(drvdata);
  98
  99         /* Disable the trace unit before programming trace registers */
 100         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
 101
 102         /* wait for TRCSTATR.IDLE to go up */
 103         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 104                 dev_err(drvdata->dev,
 105                         "timeout while waiting for Idle Trace Status\n");
 106
 107         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 108         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 109         /* nothing specific implemented */
 110         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 111         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 112         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 113         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 114         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 115         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 116         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 117         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 118         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 119         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 120         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 121         writel_relaxed(config->vissctlr,
 122                        drvdata->base + TRCVISSCTLR);
 123         writel_relaxed(config->vipcssctlr,
 124                        drvdata->base + TRCVIPCSSCTLR);
 125         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 126                 writel_relaxed(config->seq_ctrl[i],
 127                                drvdata->base + TRCSEQEVRn(i));
 128         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 129         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 130         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 131         for (i = 0; i < drvdata->nr_cntr; i++) {
 132                 writel_relaxed(config->cntrldvr[i],
 133                                drvdata->base + TRCCNTRLDVRn(i));
 134                 writel_relaxed(config->cntr_ctrl[i],
 135                                drvdata->base + TRCCNTCTLRn(i));
 136                 writel_relaxed(config->cntr_val[i],
 137                                drvdata->base + TRCCNTVRn(i));
 138         }
 139
 140         /* Resource selector pair 0 is always implemented and reserved */
 141         for (i = 0; i < drvdata->nr_resource * 2; i++)
 142                 writel_relaxed(config->res_ctrl[i],
 143                                drvdata->base + TRCRSCTLRn(i));
 144
 145         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 146                 writel_relaxed(config->ss_ctrl[i],
 147                                drvdata->base + TRCSSCCRn(i));
 148                 writel_relaxed(config->ss_status[i],
 149                                drvdata->base + TRCSSCSRn(i));
 150                 writel_relaxed(config->ss_pe_cmp[i],
 151                                drvdata->base + TRCSSPCICRn(i));
 152         }
 153         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 154                 writeq_relaxed(config->addr_val[i],
 155                                drvdata->base + TRCACVRn(i));
 156                 writeq_relaxed(config->addr_acc[i],
 157                                drvdata->base + TRCACATRn(i));
 158         }
 159         for (i = 0; i < drvdata->numcidc; i++)
 160                 writeq_relaxed(config->ctxid_pid[i],
 161                                drvdata->base + TRCCIDCVRn(i));
 162         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 163         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 164
 165         for (i = 0; i < drvdata->numvmidc; i++)
 166                 writeq_relaxed(config->vmid_val[i],
 167                                drvdata->base + TRCVMIDCVRn(i));
 168         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 169         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 170
 171         /*
 172          * Request to keep the trace unit powered and also
 173          * emulation of powerdown
 174          */
 175         writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
 176                        drvdata->base + TRCPDCR);
 177
 178         /* Enable the trace unit */
 179         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 180
 181         /* wait for TRCSTATR.IDLE to go back down to '0' */
 182         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 183                 dev_err(drvdata->dev,
 184                         "timeout while waiting for Idle Trace Status\n");
 185         /*
 186          * As recommended by section 4.3.7 ("Synchronization when using the
 187          * memory-mapped interface") of ARM IHI 0064D
 188          */
 189         dsb(sy);
 190         isb();
 191
 192         CS_LOCK(drvdata->base);
 193
 194         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 195 }
 196
 197 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 198                                    struct perf_event *event)
 199 {
 200         int ret = 0;
 201         struct etmv4_config *config = &drvdata->config;
 202         struct perf_event_attr *attr = &event->attr;
 203
 204         if (!attr) {
 205                 ret = -EINVAL;
 206                 goto out;
 207         }
 208
 209         /* Clear configuration from previous run */
 210         memset(config, 0, sizeof(struct etmv4_config));
 211
 212         if (attr->exclude_kernel)
 213                 config->mode = ETM_MODE_EXCL_KERN;
 214
 215         if (attr->exclude_user)
 216                 config->mode = ETM_MODE_EXCL_USER;
 217
 218         /* Always start from the default config */
 219         etm4_set_default_config(config);
 220
 221         /* Configure filters specified on the perf cmd line, if any. */
 222         ret = etm4_set_event_filters(drvdata, event);
 223         if (ret)
 224                 goto out;
 225
 226         /* Go from generic option to ETMv4 specifics */
 227         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 228                 config->cfg |= BIT(4);
 229                 /* TRM: Must program this for cycacc to work */
 230                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 231         }
 232         if (attr->config & BIT(ETM_OPT_TS))
 233                 /* bit[11], Global timestamp tracing bit */
 234                 config->cfg |= BIT(11);
 235         /* return stack - enable if selected and supported */
 236         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 237                 /* bit[12], Return stack enable bit */
 238                 config->cfg |= BIT(12);
 239
 240 out:
 241         return ret;
 242 }
 243
 244 static int etm4_enable_perf(struct coresight_device *csdev,
 245                             struct perf_event *event)
 246 {
 247         int ret = 0;
 248         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 249
 250         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 251                 ret = -EINVAL;
 252                 goto out;
 253         }
 254
 255         /* Configure the tracer based on the session's specifics */
 256         ret = etm4_parse_event_config(drvdata, event);
 257         if (ret)
 258                 goto out;
 259         /* And enable it */
 260         etm4_enable_hw(drvdata);
 261
 262 out:
 263         return ret;
 264 }
 265
 266 static int etm4_enable_sysfs(struct coresight_device *csdev)
 267 {
 268         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 269         int ret;
 270
 271         spin_lock(&drvdata->spinlock);
 272
 273         /*
 274          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 275          * ensures that register writes occur when cpu is powered.
 276          */
 277         ret = smp_call_function_single(drvdata->cpu,
 278                                        etm4_enable_hw, drvdata, 1);
 279         if (ret)
 280                 goto err;
 281
 282         drvdata->sticky_enable = true;
 283         spin_unlock(&drvdata->spinlock);
 284
 285         dev_info(drvdata->dev, "ETM tracing enabled\n");
 286         return 0;
 287
 288 err:
 289         spin_unlock(&drvdata->spinlock);
 290         return ret;
 291 }
 292
 293 static int etm4_enable(struct coresight_device *csdev,
 294                        struct perf_event *event, u32 mode)
 295 {
 296         int ret;
 297         u32 val;
 298         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 299
 300         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 301
 302         /* Someone is already using the tracer */
 303         if (val)
 304                 return -EBUSY;
 305
 306         switch (mode) {
 307         case CS_MODE_SYSFS:
 308                 ret = etm4_enable_sysfs(csdev);
 309                 break;
 310         case CS_MODE_PERF:
 311                 ret = etm4_enable_perf(csdev, event);
 312                 break;
 313         default:
 314                 ret = -EINVAL;
 315         }
 316
 317         /* The tracer didn't start */
 318         if (ret)
 319                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 320
 321         return ret;
 322 }
 323
 324 static void etm4_disable_hw(void *info)
 325 {
 326         u32 control;
 327         struct etmv4_drvdata *drvdata = info;
 328
 329         CS_UNLOCK(drvdata->base);
 330
 331         /* power can be removed from the trace unit now */
 332         control = readl_relaxed(drvdata->base + TRCPDCR);
 333         control &= ~TRCPDCR_PU;
 334         writel_relaxed(control, drvdata->base + TRCPDCR);
 335
 336         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 337
 338         /* EN, bit[0] Trace unit enable bit */
 339         control &= ~0x1;
 340
 341         /*
 342          * Make sure everything completes before disabling, as recommended
 343          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 344          * SSTATUS") of ARM IHI 0064D
 345          */
 346         dsb(sy);
 347         isb();
 348         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 349
 350         CS_LOCK(drvdata->base);
 351
 352         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 353 }
 354
 355 static int etm4_disable_perf(struct coresight_device *csdev,
 356                              struct perf_event *event)
 357 {
 358         u32 control;
 359         struct etm_filters *filters = event->hw.addr_filters;
 360         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 361
 362         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 363                 return -EINVAL;
 364
 365         etm4_disable_hw(drvdata);
 366
 367         /*
 368          * Check if the start/stop logic was active when the unit was stopped.
 369          * That way we can re-enable the start/stop logic when the process is
 370          * scheduled again.  Configuration of the start/stop logic happens in
 371          * function etm4_set_event_filters().
 372          */
 373         control = readl_relaxed(drvdata->base + TRCVICTLR);
 374         /* TRCVICTLR::SSSTATUS, bit[9] */
 375         filters->ssstatus = (control & BIT(9));
 376
 377         return 0;
 378 }
 379
 380 static void etm4_disable_sysfs(struct coresight_device *csdev)
 381 {
 382         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 383
 384         /*
 385          * Taking hotplug lock here protects from clocks getting disabled
 386          * with tracing being left on (crash scenario) if user disable occurs
 387          * after cpu online mask indicates the cpu is offline but before the
 388          * DYING hotplug callback is serviced by the ETM driver.
 389          */
 390         cpus_read_lock();
 391         spin_lock(&drvdata->spinlock);
 392
 393         /*
 394          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 395          * ensures that register writes occur when cpu is powered.
 396          */
 397         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 398
 399         spin_unlock(&drvdata->spinlock);
 400         cpus_read_unlock();
 401
 402         dev_info(drvdata->dev, "ETM tracing disabled\n");
 403 }
 404
 405 static void etm4_disable(struct coresight_device *csdev,
 406                          struct perf_event *event)
 407 {
 408         u32 mode;
 409         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 410
 411         /*
 412          * For as long as the tracer isn't disabled another entity can't
 413          * change its status.  As such we can read the status here without
 414          * fearing it will change under us.
 415          */
 416         mode = local_read(&drvdata->mode);
 417
 418         switch (mode) {
 419         case CS_MODE_DISABLED:
 420                 break;
 421         case CS_MODE_SYSFS:
 422                 etm4_disable_sysfs(csdev);
 423                 break;
 424         case CS_MODE_PERF:
 425                 etm4_disable_perf(csdev, event);
 426                 break;
 427         }
 428
 429         if (mode)
 430                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 431 }
 432
 433 static const struct coresight_ops_source etm4_source_ops = {
 434         .cpu_id         = etm4_cpu_id,
 435         .trace_id       = etm4_trace_id,
 436         .enable         = etm4_enable,
 437         .disable        = etm4_disable,
 438 };
 439
 440 static const struct coresight_ops etm4_cs_ops = {
 441         .source_ops     = &etm4_source_ops,
 442 };
 443
 444 static void etm4_init_arch_data(void *info)
 445 {
 446         u32 etmidr0;
 447         u32 etmidr1;
 448         u32 etmidr2;
 449         u32 etmidr3;
 450         u32 etmidr4;
 451         u32 etmidr5;
 452         struct etmv4_drvdata *drvdata = info;
 453
 454         /* Make sure all registers are accessible */
 455         etm4_os_unlock(drvdata);
 456
 457         CS_UNLOCK(drvdata->base);
 458
 459         /* find all capabilities of the tracing unit */
 460         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 461
 462         /* INSTP0, bits[2:1] P0 tracing support field */
 463         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 464                 drvdata->instrp0 = true;
 465         else
 466                 drvdata->instrp0 = false;
 467
 468         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 469         if (BMVAL(etmidr0, 5, 5))
 470                 drvdata->trcbb = true;
 471         else
 472                 drvdata->trcbb = false;
 473
 474         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 475         if (BMVAL(etmidr0, 6, 6))
 476                 drvdata->trccond = true;
 477         else
 478                 drvdata->trccond = false;
 479
 480         /* TRCCCI, bit[7] Cycle counting instruction bit */
 481         if (BMVAL(etmidr0, 7, 7))
 482                 drvdata->trccci = true;
 483         else
 484                 drvdata->trccci = false;
 485
 486         /* RETSTACK, bit[9] Return stack bit */
 487         if (BMVAL(etmidr0, 9, 9))
 488                 drvdata->retstack = true;
 489         else
 490                 drvdata->retstack = false;
 491
 492         /* NUMEVENT, bits[11:10] Number of events field */
 493         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 494         /* QSUPP, bits[16:15] Q element support field */
 495         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 496         /* TSSIZE, bits[28:24] Global timestamp size field */
 497         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 498
 499         /* base architecture of trace unit */
 500         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 501         /*
 502          * TRCARCHMIN, bits[7:4] architecture the minor version number
 503          * TRCARCHMAJ, bits[11:8] architecture major versin number
 504          */
 505         drvdata->arch = BMVAL(etmidr1, 4, 11);
 506
 507         /* maximum size of resources */
 508         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 509         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 510         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 511         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 512         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 513         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 514         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 515
 516         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 517         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 518         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 519         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 520         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 521         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 522         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 523
 524         /*
 525          * TRCERR, bit[24] whether a trace unit can trace a
 526          * system error exception.
 527          */
 528         if (BMVAL(etmidr3, 24, 24))
 529                 drvdata->trc_error = true;
 530         else
 531                 drvdata->trc_error = false;
 532
 533         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 534         if (BMVAL(etmidr3, 25, 25))
 535                 drvdata->syncpr = true;
 536         else
 537                 drvdata->syncpr = false;
 538
 539         /* STALLCTL, bit[26] is stall control implemented? */
 540         if (BMVAL(etmidr3, 26, 26))
 541                 drvdata->stallctl = true;
 542         else
 543                 drvdata->stallctl = false;
 544
 545         /* SYSSTALL, bit[27] implementation can support stall control? */
 546         if (BMVAL(etmidr3, 27, 27))
 547                 drvdata->sysstall = true;
 548         else
 549                 drvdata->sysstall = false;
 550
 551         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 552         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 553
 554         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 555         if (BMVAL(etmidr3, 31, 31))
 556                 drvdata->nooverflow = true;
 557         else
 558                 drvdata->nooverflow = false;
 559
 560         /* number of resources trace unit supports */
 561         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 562         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 563         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 564         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 565         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 566         /*
 567          * NUMRSPAIR, bits[19:16]
 568          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 569          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 570          * As such add 1 to the value of NUMRSPAIR for a better representation.
 571          */
 572         drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 573         /*
 574          * NUMSSCC, bits[23:20] the number of single-shot
 575          * comparator control for tracing
 576          */
 577         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 578         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 579         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 580         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 581         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 582
 583         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 584         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 585         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 586         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 587         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 588         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 589         if (BMVAL(etmidr5, 22, 22))
 590                 drvdata->atbtrig = true;
 591         else
 592                 drvdata->atbtrig = false;
 593         /*
 594          * LPOVERRIDE, bit[23] implementation supports
 595          * low-power state override
 596          */
 597         if (BMVAL(etmidr5, 23, 23))
 598                 drvdata->lpoverride = true;
 599         else
 600                 drvdata->lpoverride = false;
 601         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 602         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 603         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 604         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 605         CS_LOCK(drvdata->base);
 606 }
 607
 608 static void etm4_set_default_config(struct etmv4_config *config)
 609 {
 610         /* disable all events tracing */
 611         config->eventctrl0 = 0x0;
 612         config->eventctrl1 = 0x0;
 613
 614         /* disable stalling */
 615         config->stall_ctrl = 0x0;
 616
 617         /* enable trace synchronization every 4096 bytes, if available */
 618         config->syncfreq = 0xC;
 619
 620         /* disable timestamp event */
 621         config->ts_ctrl = 0x0;
 622
 623         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 624         config->vinst_ctrl |= BIT(0);
 625 }
 626
 627 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 628 {
 629         u64 access_type = 0;
 630
 631         /*
 632          * EXLEVEL_NS, bits[15:12]
 633          * The Exception levels are:
 634          *   Bit[12] Exception level 0 - Application
 635          *   Bit[13] Exception level 1 - OS
 636          *   Bit[14] Exception level 2 - Hypervisor
 637          *   Bit[15] Never implemented
 638          */
 639         if (!is_kernel_in_hyp_mode()) {
 640                 /* Stay away from hypervisor mode for non-VHE */
 641                 access_type =  ETM_EXLEVEL_NS_HYP;
 642                 if (config->mode & ETM_MODE_EXCL_KERN)
 643                         access_type |= ETM_EXLEVEL_NS_OS;
 644         } else if (config->mode & ETM_MODE_EXCL_KERN) {
 645                 access_type = ETM_EXLEVEL_NS_HYP;
 646         }
 647
 648         if (config->mode & ETM_MODE_EXCL_USER)
 649                 access_type |= ETM_EXLEVEL_NS_APP;
 650
 651         return access_type;
 652 }
 653
 654 static u64 etm4_get_access_type(struct etmv4_config *config)
 655 {
 656         u64 access_type = etm4_get_ns_access_type(config);
 657
 658         /*
 659          * EXLEVEL_S, bits[11:8], don't trace anything happening
 660          * in secure state.
 661          */
 662         access_type |= (ETM_EXLEVEL_S_APP       |
 663                         ETM_EXLEVEL_S_OS        |
 664                         ETM_EXLEVEL_S_HYP);
 665
 666         return access_type;
 667 }
 668
 669 static void etm4_set_comparator_filter(struct etmv4_config *config,
 670                                        u64 start, u64 stop, int comparator)
 671 {
 672         u64 access_type = etm4_get_access_type(config);
 673
 674         /* First half of default address comparator */
 675         config->addr_val[comparator] = start;
 676         config->addr_acc[comparator] = access_type;
 677         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 678
 679         /* Second half of default address comparator */
 680         config->addr_val[comparator + 1] = stop;
 681         config->addr_acc[comparator + 1] = access_type;
 682         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 683
 684         /*
 685          * Configure the ViewInst function to include this address range
 686          * comparator.
 687          *
 688          * @comparator is divided by two since it is the index in the
 689          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
 690          * address range comparator _pairs_.
 691          *
 692          * Therefore:
 693          *      index 0 -> compatator pair 0
 694          *      index 2 -> comparator pair 1
 695          *      index 4 -> comparator pair 2
 696          *      ...
 697          *      index 14 -> comparator pair 7
 698          */
 699         config->viiectlr |= BIT(comparator / 2);
 700 }
 701
 702 static void etm4_set_start_stop_filter(struct etmv4_config *config,
 703                                        u64 address, int comparator,
 704                                        enum etm_addr_type type)
 705 {
 706         int shift;
 707         u64 access_type = etm4_get_access_type(config);
 708
 709         /* Configure the comparator */
 710         config->addr_val[comparator] = address;
 711         config->addr_acc[comparator] = access_type;
 712         config->addr_type[comparator] = type;
 713
 714         /*
 715          * Configure ViewInst Start-Stop control register.
 716          * Addresses configured to start tracing go from bit 0 to n-1,
 717          * while those configured to stop tracing from 16 to 16 + n-1.
 718          */
 719         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
 720         config->vissctlr |= BIT(shift + comparator);
 721 }
 722
 723 static void etm4_set_default_filter(struct etmv4_config *config)
 724 {
 725         u64 start, stop;
 726
 727         /*
 728          * Configure address range comparator '0' to encompass all
 729          * possible addresses.
 730          */
 731         start = 0x0;
 732         stop = ~0x0;
 733
 734         etm4_set_comparator_filter(config, start, stop,
 735                                    ETM_DEFAULT_ADDR_COMP);
 736
 737         /*
 738          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 739          * in the started state
 740          */
 741         config->vinst_ctrl |= BIT(9);
 742
 743         /* No start-stop filtering for ViewInst */
 744         config->vissctlr = 0x0;
 745 }
 746
 747 static void etm4_set_default(struct etmv4_config *config)
 748 {
 749         if (WARN_ON_ONCE(!config))
 750                 return;
 751
 752         /*
 753          * Make default initialisation trace everything
 754          *
 755          * Select the "always true" resource selector on the
 756          * "Enablign Event" line and configure address range comparator
 757          * '0' to trace all the possible address range.  From there
 758          * configure the "include/exclude" engine to include address
 759          * range comparator '0'.
 760          */
 761         etm4_set_default_config(config);
 762         etm4_set_default_filter(config);
 763 }
 764
 765 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
 766 {
 767         int nr_comparator, index = 0;
 768         struct etmv4_config *config = &drvdata->config;
 769
 770         /*
 771          * nr_addr_cmp holds the number of comparator _pair_, so time 2
 772          * for the total number of comparators.
 773          */
 774         nr_comparator = drvdata->nr_addr_cmp * 2;
 775
 776         /* Go through the tally of comparators looking for a free one. */
 777         while (index < nr_comparator) {
 778                 switch (type) {
 779                 case ETM_ADDR_TYPE_RANGE:
 780                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
 781                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
 782                                 return index;
 783
 784                         /* Address range comparators go in pairs */
 785                         index += 2;
 786                         break;
 787                 case ETM_ADDR_TYPE_START:
 788                 case ETM_ADDR_TYPE_STOP:
 789                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
 790                                 return index;
 791
 792                         /* Start/stop address can have odd indexes */
 793                         index += 1;
 794                         break;
 795                 default:
 796                         return -EINVAL;
 797                 }
 798         }
 799
 800         /* If we are here all the comparators have been used. */
 801         return -ENOSPC;
 802 }
 803
 804 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
 805                                   struct perf_event *event)
 806 {
 807         int i, comparator, ret = 0;
 808         u64 address;
 809         struct etmv4_config *config = &drvdata->config;
 810         struct etm_filters *filters = event->hw.addr_filters;
 811
 812         if (!filters)
 813                 goto default_filter;
 814
 815         /* Sync events with what Perf got */
 816         perf_event_addr_filters_sync(event);
 817
 818         /*
 819          * If there are no filters to deal with simply go ahead with
 820          * the default filter, i.e the entire address range.
 821          */
 822         if (!filters->nr_filters)
 823                 goto default_filter;
 824
 825         for (i = 0; i < filters->nr_filters; i++) {
 826                 struct etm_filter *filter = &filters->etm_filter[i];
 827                 enum etm_addr_type type = filter->type;
 828
 829                 /* See if a comparator is free. */
 830                 comparator = etm4_get_next_comparator(drvdata, type);
 831                 if (comparator < 0) {
 832                         ret = comparator;
 833                         goto out;
 834                 }
 835
 836                 switch (type) {
 837                 case ETM_ADDR_TYPE_RANGE:
 838                         etm4_set_comparator_filter(config,
 839                                                    filter->start_addr,
 840                                                    filter->stop_addr,
 841                                                    comparator);
 842                         /*
 843                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 844                          * in the started state
 845                          */
 846                         config->vinst_ctrl |= BIT(9);
 847
 848                         /* No start-stop filtering for ViewInst */
 849                         config->vissctlr = 0x0;
 850                         break;
 851                 case ETM_ADDR_TYPE_START:
 852                 case ETM_ADDR_TYPE_STOP:
 853                         /* Get the right start or stop address */
 854                         address = (type == ETM_ADDR_TYPE_START ?
 855                                    filter->start_addr :
 856                                    filter->stop_addr);
 857
 858                         /* Configure comparator */
 859                         etm4_set_start_stop_filter(config, address,
 860                                                    comparator, type);
 861
 862                         /*
 863                          * If filters::ssstatus == 1, trace acquisition was
 864                          * started but the process was yanked away before the
 865                          * the stop address was hit.  As such the start/stop
 866                          * logic needs to be re-started so that tracing can
 867                          * resume where it left.
 868                          *
 869                          * The start/stop logic status when a process is
 870                          * scheduled out is checked in function
 871                          * etm4_disable_perf().
 872                          */
 873                         if (filters->ssstatus)
 874                                 config->vinst_ctrl |= BIT(9);
 875
 876                         /* No include/exclude filtering for ViewInst */
 877                         config->viiectlr = 0x0;
 878                         break;
 879                 default:
 880                         ret = -EINVAL;
 881                         goto out;
 882                 }
 883         }
 884
 885         goto out;
 886
 887
 888 default_filter:
 889         etm4_set_default_filter(config);
 890
 891 out:
 892         return ret;
 893 }
 894
 895 void etm4_config_trace_mode(struct etmv4_config *config)
 896 {
 897         u32 addr_acc, mode;
 898
 899         mode = config->mode;
 900         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
 901
 902         /* excluding kernel AND user space doesn't make sense */
 903         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
 904
 905         /* nothing to do if neither flags are set */
 906         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
 907                 return;
 908
 909         addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
 910         /* clear default config */
 911         addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
 912                       ETM_EXLEVEL_NS_HYP);
 913
 914         addr_acc |= etm4_get_ns_access_type(config);
 915
 916         config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
 917         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
 918 }
 919
 920 static int etm4_online_cpu(unsigned int cpu)
 921 {
 922         if (!etmdrvdata[cpu])
 923                 return 0;
 924
 925         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
 926                 coresight_enable(etmdrvdata[cpu]->csdev);
 927         return 0;
 928 }
 929
 930 static int etm4_starting_cpu(unsigned int cpu)
 931 {
 932         if (!etmdrvdata[cpu])
 933                 return 0;
 934
 935         spin_lock(&etmdrvdata[cpu]->spinlock);
 936         if (!etmdrvdata[cpu]->os_unlock) {
 937                 etm4_os_unlock(etmdrvdata[cpu]);
 938                 etmdrvdata[cpu]->os_unlock = true;
 939         }
 940
 941         if (local_read(&etmdrvdata[cpu]->mode))
 942                 etm4_enable_hw(etmdrvdata[cpu]);
 943         spin_unlock(&etmdrvdata[cpu]->spinlock);
 944         return 0;
 945 }
 946
 947 static int etm4_dying_cpu(unsigned int cpu)
 948 {
 949         if (!etmdrvdata[cpu])
 950                 return 0;
 951
 952         spin_lock(&etmdrvdata[cpu]->spinlock);
 953         if (local_read(&etmdrvdata[cpu]->mode))
 954                 etm4_disable_hw(etmdrvdata[cpu]);
 955         spin_unlock(&etmdrvdata[cpu]->spinlock);
 956         return 0;
 957 }
 958
 959 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
 960 {
 961         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
 962 }
 963
 964 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 965 {
 966         int ret;
 967         void __iomem *base;
 968         struct device *dev = &adev->dev;
 969         struct coresight_platform_data *pdata = NULL;
 970         struct etmv4_drvdata *drvdata;
 971         struct resource *res = &adev->res;
 972         struct coresight_desc desc = { 0 };
 973         struct device_node *np = adev->dev.of_node;
 974
 975         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 976         if (!drvdata)
 977                 return -ENOMEM;
 978
 979         if (np) {
 980                 pdata = of_get_coresight_platform_data(dev, np);
 981                 if (IS_ERR(pdata))
 982                         return PTR_ERR(pdata);
 983                 adev->dev.platform_data = pdata;
 984         }
 985
 986         drvdata->dev = &adev->dev;
 987         dev_set_drvdata(dev, drvdata);
 988
 989         /* Validity for the resource is already checked by the AMBA core */
 990         base = devm_ioremap_resource(dev, res);
 991         if (IS_ERR(base))
 992                 return PTR_ERR(base);
 993
 994         drvdata->base = base;
 995
 996         spin_lock_init(&drvdata->spinlock);
 997
 998         drvdata->cpu = pdata ? pdata->cpu : 0;
 999
1000         cpus_read_lock();
1001         etmdrvdata[drvdata->cpu] = drvdata;
1002
1003         if (smp_call_function_single(drvdata->cpu,
1004                                 etm4_init_arch_data,  drvdata, 1))
1005                 dev_err(dev, "ETM arch init failed\n");
1006
1007         if (!etm4_count++) {
1008                 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
1009                                                      "arm/coresight4:starting",
1010                                                      etm4_starting_cpu, etm4_dying_cpu);
1011                 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
1012                                                            "arm/coresight4:online",
1013                                                            etm4_online_cpu, NULL);
1014                 if (ret < 0)
1015                         goto err_arch_supported;
1016                 hp_online = ret;
1017         }
1018
1019         cpus_read_unlock();
1020
1021         if (etm4_arch_supported(drvdata->arch) == false) {
1022                 ret = -EINVAL;
1023                 goto err_arch_supported;
1024         }
1025
1026         etm4_init_trace_id(drvdata);
1027         etm4_set_default(&drvdata->config);
1028
1029         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1030         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1031         desc.ops = &etm4_cs_ops;
1032         desc.pdata = pdata;
1033         desc.dev = dev;
1034         desc.groups = coresight_etmv4_groups;
1035         drvdata->csdev = coresight_register(&desc);
1036         if (IS_ERR(drvdata->csdev)) {
1037                 ret = PTR_ERR(drvdata->csdev);
1038                 goto err_arch_supported;
1039         }
1040
1041         ret = etm_perf_symlink(drvdata->csdev, true);
1042         if (ret) {
1043                 coresight_unregister(drvdata->csdev);
1044                 goto err_arch_supported;
1045         }
1046
1047         pm_runtime_put(&adev->dev);
1048         dev_info(dev, "CPU%d: ETM v%d.%d initialized\n",
1049                  drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1050
1051         if (boot_enable) {
1052                 coresight_enable(drvdata->csdev);
1053                 drvdata->boot_enable = true;
1054         }
1055
1056         return 0;
1057
1058 err_arch_supported:
1059         if (--etm4_count == 0) {
1060                 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1061                 if (hp_online)
1062                         cpuhp_remove_state_nocalls(hp_online);
1063         }
1064         return ret;
1065 }
1066
1067 #define ETM4x_AMBA_ID(pid)                      \
1068         {                                       \
1069                 .id     = pid,                  \
1070                 .mask   = 0x000fffff,           \
1071         }
1072
1073 static const struct amba_id etm4_ids[] = {
1074         ETM4x_AMBA_ID(0x000bb95d),              /* Cortex-A53 */
1075         ETM4x_AMBA_ID(0x000bb95e),              /* Cortex-A57 */
1076         ETM4x_AMBA_ID(0x000bb95a),              /* Cortex-A72 */
1077         ETM4x_AMBA_ID(0x000bb959),              /* Cortex-A73 */
1078         ETM4x_AMBA_ID(0x000bb9da),              /* Cortex-A35 */
1079         {},
1080 };
1081
1082 static struct amba_driver etm4x_driver = {
1083         .drv = {
1084                 .name   = "coresight-etm4x",
1085                 .suppress_bind_attrs = true,
1086         },
1087         .probe          = etm4_probe,
1088         .id_table       = etm4_ids,
1089 };
1090 builtin_amba_driver(etm4x_driver);