drivers/hwtracing/coresight/coresight-etm4x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/moduleparam.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/device.h>
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <linux/fs.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/smp.h>
  17 #include <linux/sysfs.h>
  18 #include <linux/stat.h>
  19 #include <linux/clk.h>
  20 #include <linux/cpu.h>
  21 #include <linux/coresight.h>
  22 #include <linux/coresight-pmu.h>
  23 #include <linux/pm_wakeup.h>
  24 #include <linux/amba/bus.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/uaccess.h>
  27 #include <linux/perf_event.h>
  28 #include <linux/pm_runtime.h>
  29 #include <asm/sections.h>
  30 #include <asm/local.h>
  31 #include <asm/virt.h>
  32
  33 #include "coresight-etm4x.h"
  34 #include "coresight-etm-perf.h"
  35
  36 static int boot_enable;
  37 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  38
  39 /* The number of ETMv4 currently registered */
  40 static int etm4_count;
  41 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  42 static void etm4_set_default_config(struct etmv4_config *config);
  43 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  44                                   struct perf_event *event);
  45
  46 static enum cpuhp_state hp_online;
  47
  48 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  49 {
  50         /* Writing any value to ETMOSLAR unlocks the trace registers */
  51         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  52         drvdata->os_unlock = true;
  53         isb();
  54 }
  55
  56 static bool etm4_arch_supported(u8 arch)
  57 {
  58         /* Mask out the minor version number */
  59         switch (arch & 0xf0) {
  60         case ETM_ARCH_V4:
  61                 break;
  62         default:
  63                 return false;
  64         }
  65         return true;
  66 }
  67
  68 static int etm4_cpu_id(struct coresight_device *csdev)
  69 {
  70         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  71
  72         return drvdata->cpu;
  73 }
  74
  75 static int etm4_trace_id(struct coresight_device *csdev)
  76 {
  77         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  78
  79         return drvdata->trcid;
  80 }
  81
  82 static void etm4_enable_hw(void *info)
  83 {
  84         int i;
  85         struct etmv4_drvdata *drvdata = info;
  86         struct etmv4_config *config = &drvdata->config;
  87
  88         CS_UNLOCK(drvdata->base);
  89
  90         etm4_os_unlock(drvdata);
  91
  92         /* Disable the trace unit before programming trace registers */
  93         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
  94
  95         /* wait for TRCSTATR.IDLE to go up */
  96         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
  97                 dev_err(drvdata->dev,
  98                         "timeout while waiting for Idle Trace Status\n");
  99
 100         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 101         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 102         /* nothing specific implemented */
 103         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 104         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 105         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 106         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 107         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 108         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 109         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 110         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 111         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 112         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 113         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 114         writel_relaxed(config->vissctlr,
 115                        drvdata->base + TRCVISSCTLR);
 116         writel_relaxed(config->vipcssctlr,
 117                        drvdata->base + TRCVIPCSSCTLR);
 118         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 119                 writel_relaxed(config->seq_ctrl[i],
 120                                drvdata->base + TRCSEQEVRn(i));
 121         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 122         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 123         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 124         for (i = 0; i < drvdata->nr_cntr; i++) {
 125                 writel_relaxed(config->cntrldvr[i],
 126                                drvdata->base + TRCCNTRLDVRn(i));
 127                 writel_relaxed(config->cntr_ctrl[i],
 128                                drvdata->base + TRCCNTCTLRn(i));
 129                 writel_relaxed(config->cntr_val[i],
 130                                drvdata->base + TRCCNTVRn(i));
 131         }
 132
 133         /* Resource selector pair 0 is always implemented and reserved */
 134         for (i = 0; i < drvdata->nr_resource * 2; i++)
 135                 writel_relaxed(config->res_ctrl[i],
 136                                drvdata->base + TRCRSCTLRn(i));
 137
 138         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 139                 writel_relaxed(config->ss_ctrl[i],
 140                                drvdata->base + TRCSSCCRn(i));
 141                 writel_relaxed(config->ss_status[i],
 142                                drvdata->base + TRCSSCSRn(i));
 143                 writel_relaxed(config->ss_pe_cmp[i],
 144                                drvdata->base + TRCSSPCICRn(i));
 145         }
 146         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 147                 writeq_relaxed(config->addr_val[i],
 148                                drvdata->base + TRCACVRn(i));
 149                 writeq_relaxed(config->addr_acc[i],
 150                                drvdata->base + TRCACATRn(i));
 151         }
 152         for (i = 0; i < drvdata->numcidc; i++)
 153                 writeq_relaxed(config->ctxid_pid[i],
 154                                drvdata->base + TRCCIDCVRn(i));
 155         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 156         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 157
 158         for (i = 0; i < drvdata->numvmidc; i++)
 159                 writeq_relaxed(config->vmid_val[i],
 160                                drvdata->base + TRCVMIDCVRn(i));
 161         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 162         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 163
 164         /*
 165          * Request to keep the trace unit powered and also
 166          * emulation of powerdown
 167          */
 168         writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
 169                        drvdata->base + TRCPDCR);
 170
 171         /* Enable the trace unit */
 172         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 173
 174         /* wait for TRCSTATR.IDLE to go back down to '0' */
 175         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 176                 dev_err(drvdata->dev,
 177                         "timeout while waiting for Idle Trace Status\n");
 178         /*
 179          * As recommended by section 4.3.7 ("Synchronization when using the
 180          * memory-mapped interface") of ARM IHI 0064D
 181          */
 182         dsb(sy);
 183         isb();
 184
 185         CS_LOCK(drvdata->base);
 186
 187         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 188 }
 189
 190 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 191                                    struct perf_event *event)
 192 {
 193         int ret = 0;
 194         struct etmv4_config *config = &drvdata->config;
 195         struct perf_event_attr *attr = &event->attr;
 196
 197         if (!attr) {
 198                 ret = -EINVAL;
 199                 goto out;
 200         }
 201
 202         /* Clear configuration from previous run */
 203         memset(config, 0, sizeof(struct etmv4_config));
 204
 205         if (attr->exclude_kernel)
 206                 config->mode = ETM_MODE_EXCL_KERN;
 207
 208         if (attr->exclude_user)
 209                 config->mode = ETM_MODE_EXCL_USER;
 210
 211         /* Always start from the default config */
 212         etm4_set_default_config(config);
 213
 214         /* Configure filters specified on the perf cmd line, if any. */
 215         ret = etm4_set_event_filters(drvdata, event);
 216         if (ret)
 217                 goto out;
 218
 219         /* Go from generic option to ETMv4 specifics */
 220         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 221                 config->cfg |= BIT(4);
 222                 /* TRM: Must program this for cycacc to work */
 223                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 224         }
 225         if (attr->config & BIT(ETM_OPT_TS))
 226                 /* bit[11], Global timestamp tracing bit */
 227                 config->cfg |= BIT(11);
 228         /* return stack - enable if selected and supported */
 229         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 230                 /* bit[12], Return stack enable bit */
 231                 config->cfg |= BIT(12);
 232
 233 out:
 234         return ret;
 235 }
 236
 237 static int etm4_enable_perf(struct coresight_device *csdev,
 238                             struct perf_event *event)
 239 {
 240         int ret = 0;
 241         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 242
 243         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 244                 ret = -EINVAL;
 245                 goto out;
 246         }
 247
 248         /* Configure the tracer based on the session's specifics */
 249         ret = etm4_parse_event_config(drvdata, event);
 250         if (ret)
 251                 goto out;
 252         /* And enable it */
 253         etm4_enable_hw(drvdata);
 254
 255 out:
 256         return ret;
 257 }
 258
 259 static int etm4_enable_sysfs(struct coresight_device *csdev)
 260 {
 261         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 262         int ret;
 263
 264         spin_lock(&drvdata->spinlock);
 265
 266         /*
 267          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 268          * ensures that register writes occur when cpu is powered.
 269          */
 270         ret = smp_call_function_single(drvdata->cpu,
 271                                        etm4_enable_hw, drvdata, 1);
 272         if (ret)
 273                 goto err;
 274
 275         drvdata->sticky_enable = true;
 276         spin_unlock(&drvdata->spinlock);
 277
 278         dev_info(drvdata->dev, "ETM tracing enabled\n");
 279         return 0;
 280
 281 err:
 282         spin_unlock(&drvdata->spinlock);
 283         return ret;
 284 }
 285
 286 static int etm4_enable(struct coresight_device *csdev,
 287                        struct perf_event *event, u32 mode)
 288 {
 289         int ret;
 290         u32 val;
 291         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 292
 293         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 294
 295         /* Someone is already using the tracer */
 296         if (val)
 297                 return -EBUSY;
 298
 299         switch (mode) {
 300         case CS_MODE_SYSFS:
 301                 ret = etm4_enable_sysfs(csdev);
 302                 break;
 303         case CS_MODE_PERF:
 304                 ret = etm4_enable_perf(csdev, event);
 305                 break;
 306         default:
 307                 ret = -EINVAL;
 308         }
 309
 310         /* The tracer didn't start */
 311         if (ret)
 312                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 313
 314         return ret;
 315 }
 316
 317 static void etm4_disable_hw(void *info)
 318 {
 319         u32 control;
 320         struct etmv4_drvdata *drvdata = info;
 321
 322         CS_UNLOCK(drvdata->base);
 323
 324         /* power can be removed from the trace unit now */
 325         control = readl_relaxed(drvdata->base + TRCPDCR);
 326         control &= ~TRCPDCR_PU;
 327         writel_relaxed(control, drvdata->base + TRCPDCR);
 328
 329         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 330
 331         /* EN, bit[0] Trace unit enable bit */
 332         control &= ~0x1;
 333
 334         /*
 335          * Make sure everything completes before disabling, as recommended
 336          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 337          * SSTATUS") of ARM IHI 0064D
 338          */
 339         dsb(sy);
 340         isb();
 341         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 342
 343         CS_LOCK(drvdata->base);
 344
 345         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 346 }
 347
 348 static int etm4_disable_perf(struct coresight_device *csdev,
 349                              struct perf_event *event)
 350 {
 351         u32 control;
 352         struct etm_filters *filters = event->hw.addr_filters;
 353         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 354
 355         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 356                 return -EINVAL;
 357
 358         etm4_disable_hw(drvdata);
 359
 360         /*
 361          * Check if the start/stop logic was active when the unit was stopped.
 362          * That way we can re-enable the start/stop logic when the process is
 363          * scheduled again.  Configuration of the start/stop logic happens in
 364          * function etm4_set_event_filters().
 365          */
 366         control = readl_relaxed(drvdata->base + TRCVICTLR);
 367         /* TRCVICTLR::SSSTATUS, bit[9] */
 368         filters->ssstatus = (control & BIT(9));
 369
 370         return 0;
 371 }
 372
 373 static void etm4_disable_sysfs(struct coresight_device *csdev)
 374 {
 375         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 376
 377         /*
 378          * Taking hotplug lock here protects from clocks getting disabled
 379          * with tracing being left on (crash scenario) if user disable occurs
 380          * after cpu online mask indicates the cpu is offline but before the
 381          * DYING hotplug callback is serviced by the ETM driver.
 382          */
 383         cpus_read_lock();
 384         spin_lock(&drvdata->spinlock);
 385
 386         /*
 387          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 388          * ensures that register writes occur when cpu is powered.
 389          */
 390         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 391
 392         spin_unlock(&drvdata->spinlock);
 393         cpus_read_unlock();
 394
 395         dev_info(drvdata->dev, "ETM tracing disabled\n");
 396 }
 397
 398 static void etm4_disable(struct coresight_device *csdev,
 399                          struct perf_event *event)
 400 {
 401         u32 mode;
 402         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 403
 404         /*
 405          * For as long as the tracer isn't disabled another entity can't
 406          * change its status.  As such we can read the status here without
 407          * fearing it will change under us.
 408          */
 409         mode = local_read(&drvdata->mode);
 410
 411         switch (mode) {
 412         case CS_MODE_DISABLED:
 413                 break;
 414         case CS_MODE_SYSFS:
 415                 etm4_disable_sysfs(csdev);
 416                 break;
 417         case CS_MODE_PERF:
 418                 etm4_disable_perf(csdev, event);
 419                 break;
 420         }
 421
 422         if (mode)
 423                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 424 }
 425
 426 static const struct coresight_ops_source etm4_source_ops = {
 427         .cpu_id         = etm4_cpu_id,
 428         .trace_id       = etm4_trace_id,
 429         .enable         = etm4_enable,
 430         .disable        = etm4_disable,
 431 };
 432
 433 static const struct coresight_ops etm4_cs_ops = {
 434         .source_ops     = &etm4_source_ops,
 435 };
 436
 437 static void etm4_init_arch_data(void *info)
 438 {
 439         u32 etmidr0;
 440         u32 etmidr1;
 441         u32 etmidr2;
 442         u32 etmidr3;
 443         u32 etmidr4;
 444         u32 etmidr5;
 445         struct etmv4_drvdata *drvdata = info;
 446
 447         /* Make sure all registers are accessible */
 448         etm4_os_unlock(drvdata);
 449
 450         CS_UNLOCK(drvdata->base);
 451
 452         /* find all capabilities of the tracing unit */
 453         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 454
 455         /* INSTP0, bits[2:1] P0 tracing support field */
 456         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 457                 drvdata->instrp0 = true;
 458         else
 459                 drvdata->instrp0 = false;
 460
 461         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 462         if (BMVAL(etmidr0, 5, 5))
 463                 drvdata->trcbb = true;
 464         else
 465                 drvdata->trcbb = false;
 466
 467         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 468         if (BMVAL(etmidr0, 6, 6))
 469                 drvdata->trccond = true;
 470         else
 471                 drvdata->trccond = false;
 472
 473         /* TRCCCI, bit[7] Cycle counting instruction bit */
 474         if (BMVAL(etmidr0, 7, 7))
 475                 drvdata->trccci = true;
 476         else
 477                 drvdata->trccci = false;
 478
 479         /* RETSTACK, bit[9] Return stack bit */
 480         if (BMVAL(etmidr0, 9, 9))
 481                 drvdata->retstack = true;
 482         else
 483                 drvdata->retstack = false;
 484
 485         /* NUMEVENT, bits[11:10] Number of events field */
 486         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 487         /* QSUPP, bits[16:15] Q element support field */
 488         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 489         /* TSSIZE, bits[28:24] Global timestamp size field */
 490         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 491
 492         /* base architecture of trace unit */
 493         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 494         /*
 495          * TRCARCHMIN, bits[7:4] architecture the minor version number
 496          * TRCARCHMAJ, bits[11:8] architecture major versin number
 497          */
 498         drvdata->arch = BMVAL(etmidr1, 4, 11);
 499
 500         /* maximum size of resources */
 501         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 502         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 503         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 504         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 505         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 506         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 507         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 508
 509         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 510         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 511         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 512         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 513         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 514         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 515         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 516
 517         /*
 518          * TRCERR, bit[24] whether a trace unit can trace a
 519          * system error exception.
 520          */
 521         if (BMVAL(etmidr3, 24, 24))
 522                 drvdata->trc_error = true;
 523         else
 524                 drvdata->trc_error = false;
 525
 526         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 527         if (BMVAL(etmidr3, 25, 25))
 528                 drvdata->syncpr = true;
 529         else
 530                 drvdata->syncpr = false;
 531
 532         /* STALLCTL, bit[26] is stall control implemented? */
 533         if (BMVAL(etmidr3, 26, 26))
 534                 drvdata->stallctl = true;
 535         else
 536                 drvdata->stallctl = false;
 537
 538         /* SYSSTALL, bit[27] implementation can support stall control? */
 539         if (BMVAL(etmidr3, 27, 27))
 540                 drvdata->sysstall = true;
 541         else
 542                 drvdata->sysstall = false;
 543
 544         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 545         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 546
 547         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 548         if (BMVAL(etmidr3, 31, 31))
 549                 drvdata->nooverflow = true;
 550         else
 551                 drvdata->nooverflow = false;
 552
 553         /* number of resources trace unit supports */
 554         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 555         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 556         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 557         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 558         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 559         /*
 560          * NUMRSPAIR, bits[19:16]
 561          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 562          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 563          * As such add 1 to the value of NUMRSPAIR for a better representation.
 564          */
 565         drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 566         /*
 567          * NUMSSCC, bits[23:20] the number of single-shot
 568          * comparator control for tracing
 569          */
 570         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 571         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 572         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 573         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 574         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 575
 576         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 577         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 578         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 579         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 580         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 581         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 582         if (BMVAL(etmidr5, 22, 22))
 583                 drvdata->atbtrig = true;
 584         else
 585                 drvdata->atbtrig = false;
 586         /*
 587          * LPOVERRIDE, bit[23] implementation supports
 588          * low-power state override
 589          */
 590         if (BMVAL(etmidr5, 23, 23))
 591                 drvdata->lpoverride = true;
 592         else
 593                 drvdata->lpoverride = false;
 594         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 595         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 596         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 597         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 598         CS_LOCK(drvdata->base);
 599 }
 600
 601 static void etm4_set_default_config(struct etmv4_config *config)
 602 {
 603         /* disable all events tracing */
 604         config->eventctrl0 = 0x0;
 605         config->eventctrl1 = 0x0;
 606
 607         /* disable stalling */
 608         config->stall_ctrl = 0x0;
 609
 610         /* enable trace synchronization every 4096 bytes, if available */
 611         config->syncfreq = 0xC;
 612
 613         /* disable timestamp event */
 614         config->ts_ctrl = 0x0;
 615
 616         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 617         config->vinst_ctrl |= BIT(0);
 618 }
 619
 620 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 621 {
 622         u64 access_type = 0;
 623
 624         /*
 625          * EXLEVEL_NS, bits[15:12]
 626          * The Exception levels are:
 627          *   Bit[12] Exception level 0 - Application
 628          *   Bit[13] Exception level 1 - OS
 629          *   Bit[14] Exception level 2 - Hypervisor
 630          *   Bit[15] Never implemented
 631          */
 632         if (!is_kernel_in_hyp_mode()) {
 633                 /* Stay away from hypervisor mode for non-VHE */
 634                 access_type =  ETM_EXLEVEL_NS_HYP;
 635                 if (config->mode & ETM_MODE_EXCL_KERN)
 636                         access_type |= ETM_EXLEVEL_NS_OS;
 637         } else if (config->mode & ETM_MODE_EXCL_KERN) {
 638                 access_type = ETM_EXLEVEL_NS_HYP;
 639         }
 640
 641         if (config->mode & ETM_MODE_EXCL_USER)
 642                 access_type |= ETM_EXLEVEL_NS_APP;
 643
 644         return access_type;
 645 }
 646
 647 static u64 etm4_get_access_type(struct etmv4_config *config)
 648 {
 649         u64 access_type = etm4_get_ns_access_type(config);
 650
 651         /*
 652          * EXLEVEL_S, bits[11:8], don't trace anything happening
 653          * in secure state.
 654          */
 655         access_type |= (ETM_EXLEVEL_S_APP       |
 656                         ETM_EXLEVEL_S_OS        |
 657                         ETM_EXLEVEL_S_HYP);
 658
 659         return access_type;
 660 }
 661
 662 static void etm4_set_comparator_filter(struct etmv4_config *config,
 663                                        u64 start, u64 stop, int comparator)
 664 {
 665         u64 access_type = etm4_get_access_type(config);
 666
 667         /* First half of default address comparator */
 668         config->addr_val[comparator] = start;
 669         config->addr_acc[comparator] = access_type;
 670         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 671
 672         /* Second half of default address comparator */
 673         config->addr_val[comparator + 1] = stop;
 674         config->addr_acc[comparator + 1] = access_type;
 675         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 676
 677         /*
 678          * Configure the ViewInst function to include this address range
 679          * comparator.
 680          *
 681          * @comparator is divided by two since it is the index in the
 682          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
 683          * address range comparator _pairs_.
 684          *
 685          * Therefore:
 686          *      index 0 -> compatator pair 0
 687          *      index 2 -> comparator pair 1
 688          *      index 4 -> comparator pair 2
 689          *      ...
 690          *      index 14 -> comparator pair 7
 691          */
 692         config->viiectlr |= BIT(comparator / 2);
 693 }
 694
 695 static void etm4_set_start_stop_filter(struct etmv4_config *config,
 696                                        u64 address, int comparator,
 697                                        enum etm_addr_type type)
 698 {
 699         int shift;
 700         u64 access_type = etm4_get_access_type(config);
 701
 702         /* Configure the comparator */
 703         config->addr_val[comparator] = address;
 704         config->addr_acc[comparator] = access_type;
 705         config->addr_type[comparator] = type;
 706
 707         /*
 708          * Configure ViewInst Start-Stop control register.
 709          * Addresses configured to start tracing go from bit 0 to n-1,
 710          * while those configured to stop tracing from 16 to 16 + n-1.
 711          */
 712         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
 713         config->vissctlr |= BIT(shift + comparator);
 714 }
 715
 716 static void etm4_set_default_filter(struct etmv4_config *config)
 717 {
 718         u64 start, stop;
 719
 720         /*
 721          * Configure address range comparator '0' to encompass all
 722          * possible addresses.
 723          */
 724         start = 0x0;
 725         stop = ~0x0;
 726
 727         etm4_set_comparator_filter(config, start, stop,
 728                                    ETM_DEFAULT_ADDR_COMP);
 729
 730         /*
 731          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 732          * in the started state
 733          */
 734         config->vinst_ctrl |= BIT(9);
 735
 736         /* No start-stop filtering for ViewInst */
 737         config->vissctlr = 0x0;
 738 }
 739
 740 static void etm4_set_default(struct etmv4_config *config)
 741 {
 742         if (WARN_ON_ONCE(!config))
 743                 return;
 744
 745         /*
 746          * Make default initialisation trace everything
 747          *
 748          * Select the "always true" resource selector on the
 749          * "Enablign Event" line and configure address range comparator
 750          * '0' to trace all the possible address range.  From there
 751          * configure the "include/exclude" engine to include address
 752          * range comparator '0'.
 753          */
 754         etm4_set_default_config(config);
 755         etm4_set_default_filter(config);
 756 }
 757
 758 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
 759 {
 760         int nr_comparator, index = 0;
 761         struct etmv4_config *config = &drvdata->config;
 762
 763         /*
 764          * nr_addr_cmp holds the number of comparator _pair_, so time 2
 765          * for the total number of comparators.
 766          */
 767         nr_comparator = drvdata->nr_addr_cmp * 2;
 768
 769         /* Go through the tally of comparators looking for a free one. */
 770         while (index < nr_comparator) {
 771                 switch (type) {
 772                 case ETM_ADDR_TYPE_RANGE:
 773                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
 774                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
 775                                 return index;
 776
 777                         /* Address range comparators go in pairs */
 778                         index += 2;
 779                         break;
 780                 case ETM_ADDR_TYPE_START:
 781                 case ETM_ADDR_TYPE_STOP:
 782                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
 783                                 return index;
 784
 785                         /* Start/stop address can have odd indexes */
 786                         index += 1;
 787                         break;
 788                 default:
 789                         return -EINVAL;
 790                 }
 791         }
 792
 793         /* If we are here all the comparators have been used. */
 794         return -ENOSPC;
 795 }
 796
 797 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
 798                                   struct perf_event *event)
 799 {
 800         int i, comparator, ret = 0;
 801         u64 address;
 802         struct etmv4_config *config = &drvdata->config;
 803         struct etm_filters *filters = event->hw.addr_filters;
 804
 805         if (!filters)
 806                 goto default_filter;
 807
 808         /* Sync events with what Perf got */
 809         perf_event_addr_filters_sync(event);
 810
 811         /*
 812          * If there are no filters to deal with simply go ahead with
 813          * the default filter, i.e the entire address range.
 814          */
 815         if (!filters->nr_filters)
 816                 goto default_filter;
 817
 818         for (i = 0; i < filters->nr_filters; i++) {
 819                 struct etm_filter *filter = &filters->etm_filter[i];
 820                 enum etm_addr_type type = filter->type;
 821
 822                 /* See if a comparator is free. */
 823                 comparator = etm4_get_next_comparator(drvdata, type);
 824                 if (comparator < 0) {
 825                         ret = comparator;
 826                         goto out;
 827                 }
 828
 829                 switch (type) {
 830                 case ETM_ADDR_TYPE_RANGE:
 831                         etm4_set_comparator_filter(config,
 832                                                    filter->start_addr,
 833                                                    filter->stop_addr,
 834                                                    comparator);
 835                         /*
 836                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 837                          * in the started state
 838                          */
 839                         config->vinst_ctrl |= BIT(9);
 840
 841                         /* No start-stop filtering for ViewInst */
 842                         config->vissctlr = 0x0;
 843                         break;
 844                 case ETM_ADDR_TYPE_START:
 845                 case ETM_ADDR_TYPE_STOP:
 846                         /* Get the right start or stop address */
 847                         address = (type == ETM_ADDR_TYPE_START ?
 848                                    filter->start_addr :
 849                                    filter->stop_addr);
 850
 851                         /* Configure comparator */
 852                         etm4_set_start_stop_filter(config, address,
 853                                                    comparator, type);
 854
 855                         /*
 856                          * If filters::ssstatus == 1, trace acquisition was
 857                          * started but the process was yanked away before the
 858                          * the stop address was hit.  As such the start/stop
 859                          * logic needs to be re-started so that tracing can
 860                          * resume where it left.
 861                          *
 862                          * The start/stop logic status when a process is
 863                          * scheduled out is checked in function
 864                          * etm4_disable_perf().
 865                          */
 866                         if (filters->ssstatus)
 867                                 config->vinst_ctrl |= BIT(9);
 868
 869                         /* No include/exclude filtering for ViewInst */
 870                         config->viiectlr = 0x0;
 871                         break;
 872                 default:
 873                         ret = -EINVAL;
 874                         goto out;
 875                 }
 876         }
 877
 878         goto out;
 879
 880
 881 default_filter:
 882         etm4_set_default_filter(config);
 883
 884 out:
 885         return ret;
 886 }
 887
 888 void etm4_config_trace_mode(struct etmv4_config *config)
 889 {
 890         u32 addr_acc, mode;
 891
 892         mode = config->mode;
 893         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
 894
 895         /* excluding kernel AND user space doesn't make sense */
 896         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
 897
 898         /* nothing to do if neither flags are set */
 899         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
 900                 return;
 901
 902         addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
 903         /* clear default config */
 904         addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
 905                       ETM_EXLEVEL_NS_HYP);
 906
 907         addr_acc |= etm4_get_ns_access_type(config);
 908
 909         config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
 910         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
 911 }
 912
 913 static int etm4_online_cpu(unsigned int cpu)
 914 {
 915         if (!etmdrvdata[cpu])
 916                 return 0;
 917
 918         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
 919                 coresight_enable(etmdrvdata[cpu]->csdev);
 920         return 0;
 921 }
 922
 923 static int etm4_starting_cpu(unsigned int cpu)
 924 {
 925         if (!etmdrvdata[cpu])
 926                 return 0;
 927
 928         spin_lock(&etmdrvdata[cpu]->spinlock);
 929         if (!etmdrvdata[cpu]->os_unlock) {
 930                 etm4_os_unlock(etmdrvdata[cpu]);
 931                 etmdrvdata[cpu]->os_unlock = true;
 932         }
 933
 934         if (local_read(&etmdrvdata[cpu]->mode))
 935                 etm4_enable_hw(etmdrvdata[cpu]);
 936         spin_unlock(&etmdrvdata[cpu]->spinlock);
 937         return 0;
 938 }
 939
 940 static int etm4_dying_cpu(unsigned int cpu)
 941 {
 942         if (!etmdrvdata[cpu])
 943                 return 0;
 944
 945         spin_lock(&etmdrvdata[cpu]->spinlock);
 946         if (local_read(&etmdrvdata[cpu]->mode))
 947                 etm4_disable_hw(etmdrvdata[cpu]);
 948         spin_unlock(&etmdrvdata[cpu]->spinlock);
 949         return 0;
 950 }
 951
 952 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
 953 {
 954         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
 955 }
 956
 957 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 958 {
 959         int ret;
 960         void __iomem *base;
 961         struct device *dev = &adev->dev;
 962         struct coresight_platform_data *pdata = NULL;
 963         struct etmv4_drvdata *drvdata;
 964         struct resource *res = &adev->res;
 965         struct coresight_desc desc = { 0 };
 966         struct device_node *np = adev->dev.of_node;
 967
 968         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 969         if (!drvdata)
 970                 return -ENOMEM;
 971
 972         if (np) {
 973                 pdata = of_get_coresight_platform_data(dev, np);
 974                 if (IS_ERR(pdata))
 975                         return PTR_ERR(pdata);
 976                 adev->dev.platform_data = pdata;
 977         }
 978
 979         drvdata->dev = &adev->dev;
 980         dev_set_drvdata(dev, drvdata);
 981
 982         /* Validity for the resource is already checked by the AMBA core */
 983         base = devm_ioremap_resource(dev, res);
 984         if (IS_ERR(base))
 985                 return PTR_ERR(base);
 986
 987         drvdata->base = base;
 988
 989         spin_lock_init(&drvdata->spinlock);
 990
 991         drvdata->cpu = pdata ? pdata->cpu : 0;
 992
 993         cpus_read_lock();
 994         etmdrvdata[drvdata->cpu] = drvdata;
 995
 996         if (smp_call_function_single(drvdata->cpu,
 997                                 etm4_init_arch_data,  drvdata, 1))
 998                 dev_err(dev, "ETM arch init failed\n");
 999
1000         if (!etm4_count++) {
1001                 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
1002                                                      "arm/coresight4:starting",
1003                                                      etm4_starting_cpu, etm4_dying_cpu);
1004                 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
1005                                                            "arm/coresight4:online",
1006                                                            etm4_online_cpu, NULL);
1007                 if (ret < 0)
1008                         goto err_arch_supported;
1009                 hp_online = ret;
1010         }
1011
1012         cpus_read_unlock();
1013
1014         if (etm4_arch_supported(drvdata->arch) == false) {
1015                 ret = -EINVAL;
1016                 goto err_arch_supported;
1017         }
1018
1019         etm4_init_trace_id(drvdata);
1020         etm4_set_default(&drvdata->config);
1021
1022         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1023         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1024         desc.ops = &etm4_cs_ops;
1025         desc.pdata = pdata;
1026         desc.dev = dev;
1027         desc.groups = coresight_etmv4_groups;
1028         drvdata->csdev = coresight_register(&desc);
1029         if (IS_ERR(drvdata->csdev)) {
1030                 ret = PTR_ERR(drvdata->csdev);
1031                 goto err_arch_supported;
1032         }
1033
1034         ret = etm_perf_symlink(drvdata->csdev, true);
1035         if (ret) {
1036                 coresight_unregister(drvdata->csdev);
1037                 goto err_arch_supported;
1038         }
1039
1040         pm_runtime_put(&adev->dev);
1041         dev_info(dev, "CPU%d: ETM v%d.%d initialized\n",
1042                  drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1043
1044         if (boot_enable) {
1045                 coresight_enable(drvdata->csdev);
1046                 drvdata->boot_enable = true;
1047         }
1048
1049         return 0;
1050
1051 err_arch_supported:
1052         if (--etm4_count == 0) {
1053                 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1054                 if (hp_online)
1055                         cpuhp_remove_state_nocalls(hp_online);
1056         }
1057         return ret;
1058 }
1059
1060 #define ETM4x_AMBA_ID(pid)                      \
1061         {                                       \
1062                 .id     = pid,                  \
1063                 .mask   = 0x000fffff,           \
1064         }
1065
1066 static const struct amba_id etm4_ids[] = {
1067         ETM4x_AMBA_ID(0x000bb95d),              /* Cortex-A53 */
1068         ETM4x_AMBA_ID(0x000bb95e),              /* Cortex-A57 */
1069         ETM4x_AMBA_ID(0x000bb95a),              /* Cortex-A72 */
1070         ETM4x_AMBA_ID(0x000bb959),              /* Cortex-A73 */
1071         ETM4x_AMBA_ID(0x000bb9da),              /* Cortex-A35 */
1072         {},
1073 };
1074
1075 static struct amba_driver etm4x_driver = {
1076         .drv = {
1077                 .name   = "coresight-etm4x",
1078                 .suppress_bind_attrs = true,
1079         },
1080         .probe          = etm4_probe,
1081         .id_table       = etm4_ids,
1082 };
1083 builtin_amba_driver(etm4x_driver);