drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/coresight-pmu.h>
  30 #include <linux/pm_wakeup.h>
  31 #include <linux/amba/bus.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/uaccess.h>
  34 #include <linux/perf_event.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/sections.h>
  37 #include <asm/local.h>
  38 #include <asm/virt.h>
  39
  40 #include "coresight-etm4x.h"
  41 #include "coresight-etm-perf.h"
  42
  43 static int boot_enable;
  44 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  45
  46 /* The number of ETMv4 currently registered */
  47 static int etm4_count;
  48 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  49 static void etm4_set_default_config(struct etmv4_config *config);
  50 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  51                                   struct perf_event *event);
  52
  53 static enum cpuhp_state hp_online;
  54
  55 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  56 {
  57         /* Writing any value to ETMOSLAR unlocks the trace registers */
  58         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  59         drvdata->os_unlock = true;
  60         isb();
  61 }
  62
  63 static bool etm4_arch_supported(u8 arch)
  64 {
  65         /* Mask out the minor version number */
  66         switch (arch & 0xf0) {
  67         case ETM_ARCH_V4:
  68                 break;
  69         default:
  70                 return false;
  71         }
  72         return true;
  73 }
  74
  75 static int etm4_cpu_id(struct coresight_device *csdev)
  76 {
  77         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  78
  79         return drvdata->cpu;
  80 }
  81
  82 static int etm4_trace_id(struct coresight_device *csdev)
  83 {
  84         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  85
  86         return drvdata->trcid;
  87 }
  88
  89 static void etm4_enable_hw(void *info)
  90 {
  91         int i;
  92         struct etmv4_drvdata *drvdata = info;
  93         struct etmv4_config *config = &drvdata->config;
  94
  95         CS_UNLOCK(drvdata->base);
  96
  97         etm4_os_unlock(drvdata);
  98
  99         /* Disable the trace unit before programming trace registers */
 100         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
 101
 102         /* wait for TRCSTATR.IDLE to go up */
 103         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 104                 dev_err(drvdata->dev,
 105                         "timeout while waiting for Idle Trace Status\n");
 106
 107         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 108         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 109         /* nothing specific implemented */
 110         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 111         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 112         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 113         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 114         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 115         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 116         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 117         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 118         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 119         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 120         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 121         writel_relaxed(config->vissctlr,
 122                        drvdata->base + TRCVISSCTLR);
 123         writel_relaxed(config->vipcssctlr,
 124                        drvdata->base + TRCVIPCSSCTLR);
 125         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 126                 writel_relaxed(config->seq_ctrl[i],
 127                                drvdata->base + TRCSEQEVRn(i));
 128         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 129         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 130         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 131         for (i = 0; i < drvdata->nr_cntr; i++) {
 132                 writel_relaxed(config->cntrldvr[i],
 133                                drvdata->base + TRCCNTRLDVRn(i));
 134                 writel_relaxed(config->cntr_ctrl[i],
 135                                drvdata->base + TRCCNTCTLRn(i));
 136                 writel_relaxed(config->cntr_val[i],
 137                                drvdata->base + TRCCNTVRn(i));
 138         }
 139
 140         /* Resource selector pair 0 is always implemented and reserved */
 141         for (i = 0; i < drvdata->nr_resource * 2; i++)
 142                 writel_relaxed(config->res_ctrl[i],
 143                                drvdata->base + TRCRSCTLRn(i));
 144
 145         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 146                 writel_relaxed(config->ss_ctrl[i],
 147                                drvdata->base + TRCSSCCRn(i));
 148                 writel_relaxed(config->ss_status[i],
 149                                drvdata->base + TRCSSCSRn(i));
 150                 writel_relaxed(config->ss_pe_cmp[i],
 151                                drvdata->base + TRCSSPCICRn(i));
 152         }
 153         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 154                 writeq_relaxed(config->addr_val[i],
 155                                drvdata->base + TRCACVRn(i));
 156                 writeq_relaxed(config->addr_acc[i],
 157                                drvdata->base + TRCACATRn(i));
 158         }
 159         for (i = 0; i < drvdata->numcidc; i++)
 160                 writeq_relaxed(config->ctxid_pid[i],
 161                                drvdata->base + TRCCIDCVRn(i));
 162         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 163         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 164
 165         for (i = 0; i < drvdata->numvmidc; i++)
 166                 writeq_relaxed(config->vmid_val[i],
 167                                drvdata->base + TRCVMIDCVRn(i));
 168         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 169         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 170
 171         /*
 172          * Request to keep the trace unit powered and also
 173          * emulation of powerdown
 174          */
 175         writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
 176                        drvdata->base + TRCPDCR);
 177
 178         /* Enable the trace unit */
 179         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 180
 181         /* wait for TRCSTATR.IDLE to go back down to '0' */
 182         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 183                 dev_err(drvdata->dev,
 184                         "timeout while waiting for Idle Trace Status\n");
 185         /*
 186          * As recommended by section 4.3.7 ("Synchronization when using the
 187          * memory-mapped interface") of ARM IHI 0064D
 188          */
 189         dsb(sy);
 190         isb();
 191
 192         CS_LOCK(drvdata->base);
 193
 194         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 195 }
 196
 197 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 198                                    struct perf_event *event)
 199 {
 200         int ret = 0;
 201         struct etmv4_config *config = &drvdata->config;
 202         struct perf_event_attr *attr = &event->attr;
 203
 204         if (!attr) {
 205                 ret = -EINVAL;
 206                 goto out;
 207         }
 208
 209         /* Clear configuration from previous run */
 210         memset(config, 0, sizeof(struct etmv4_config));
 211
 212         if (attr->exclude_kernel)
 213                 config->mode = ETM_MODE_EXCL_KERN;
 214
 215         if (attr->exclude_user)
 216                 config->mode = ETM_MODE_EXCL_USER;
 217
 218         /* Always start from the default config */
 219         etm4_set_default_config(config);
 220
 221         /* Configure filters specified on the perf cmd line, if any. */
 222         ret = etm4_set_event_filters(drvdata, event);
 223         if (ret)
 224                 goto out;
 225
 226         /* Go from generic option to ETMv4 specifics */
 227         if (attr->config & BIT(ETM_OPT_CYCACC))
 228                 config->cfg |= ETMv4_MODE_CYCACC;
 229         if (attr->config & BIT(ETM_OPT_TS))
 230                 config->cfg |= ETMv4_MODE_TIMESTAMP;
 231
 232 out:
 233         return ret;
 234 }
 235
 236 static int etm4_enable_perf(struct coresight_device *csdev,
 237                             struct perf_event *event)
 238 {
 239         int ret = 0;
 240         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 241
 242         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 243                 ret = -EINVAL;
 244                 goto out;
 245         }
 246
 247         /* Configure the tracer based on the session's specifics */
 248         ret = etm4_parse_event_config(drvdata, event);
 249         if (ret)
 250                 goto out;
 251         /* And enable it */
 252         etm4_enable_hw(drvdata);
 253
 254 out:
 255         return ret;
 256 }
 257
 258 static int etm4_enable_sysfs(struct coresight_device *csdev)
 259 {
 260         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 261         int ret;
 262
 263         spin_lock(&drvdata->spinlock);
 264
 265         /*
 266          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 267          * ensures that register writes occur when cpu is powered.
 268          */
 269         ret = smp_call_function_single(drvdata->cpu,
 270                                        etm4_enable_hw, drvdata, 1);
 271         if (ret)
 272                 goto err;
 273
 274         drvdata->sticky_enable = true;
 275         spin_unlock(&drvdata->spinlock);
 276
 277         dev_info(drvdata->dev, "ETM tracing enabled\n");
 278         return 0;
 279
 280 err:
 281         spin_unlock(&drvdata->spinlock);
 282         return ret;
 283 }
 284
 285 static int etm4_enable(struct coresight_device *csdev,
 286                        struct perf_event *event, u32 mode)
 287 {
 288         int ret;
 289         u32 val;
 290         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 291
 292         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 293
 294         /* Someone is already using the tracer */
 295         if (val)
 296                 return -EBUSY;
 297
 298         switch (mode) {
 299         case CS_MODE_SYSFS:
 300                 ret = etm4_enable_sysfs(csdev);
 301                 break;
 302         case CS_MODE_PERF:
 303                 ret = etm4_enable_perf(csdev, event);
 304                 break;
 305         default:
 306                 ret = -EINVAL;
 307         }
 308
 309         /* The tracer didn't start */
 310         if (ret)
 311                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 312
 313         return ret;
 314 }
 315
 316 static void etm4_disable_hw(void *info)
 317 {
 318         u32 control;
 319         struct etmv4_drvdata *drvdata = info;
 320
 321         CS_UNLOCK(drvdata->base);
 322
 323         /* power can be removed from the trace unit now */
 324         control = readl_relaxed(drvdata->base + TRCPDCR);
 325         control &= ~TRCPDCR_PU;
 326         writel_relaxed(control, drvdata->base + TRCPDCR);
 327
 328         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 329
 330         /* EN, bit[0] Trace unit enable bit */
 331         control &= ~0x1;
 332
 333         /*
 334          * Make sure everything completes before disabling, as recommended
 335          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 336          * SSTATUS") of ARM IHI 0064D
 337          */
 338         dsb(sy);
 339         isb();
 340         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 341
 342         CS_LOCK(drvdata->base);
 343
 344         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 345 }
 346
 347 static int etm4_disable_perf(struct coresight_device *csdev,
 348                              struct perf_event *event)
 349 {
 350         u32 control;
 351         struct etm_filters *filters = event->hw.addr_filters;
 352         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 353
 354         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 355                 return -EINVAL;
 356
 357         etm4_disable_hw(drvdata);
 358
 359         /*
 360          * Check if the start/stop logic was active when the unit was stopped.
 361          * That way we can re-enable the start/stop logic when the process is
 362          * scheduled again.  Configuration of the start/stop logic happens in
 363          * function etm4_set_event_filters().
 364          */
 365         control = readl_relaxed(drvdata->base + TRCVICTLR);
 366         /* TRCVICTLR::SSSTATUS, bit[9] */
 367         filters->ssstatus = (control & BIT(9));
 368
 369         return 0;
 370 }
 371
 372 static void etm4_disable_sysfs(struct coresight_device *csdev)
 373 {
 374         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 375
 376         /*
 377          * Taking hotplug lock here protects from clocks getting disabled
 378          * with tracing being left on (crash scenario) if user disable occurs
 379          * after cpu online mask indicates the cpu is offline but before the
 380          * DYING hotplug callback is serviced by the ETM driver.
 381          */
 382         get_online_cpus();
 383         spin_lock(&drvdata->spinlock);
 384
 385         /*
 386          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 387          * ensures that register writes occur when cpu is powered.
 388          */
 389         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 390
 391         spin_unlock(&drvdata->spinlock);
 392         put_online_cpus();
 393
 394         dev_info(drvdata->dev, "ETM tracing disabled\n");
 395 }
 396
 397 static void etm4_disable(struct coresight_device *csdev,
 398                          struct perf_event *event)
 399 {
 400         u32 mode;
 401         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 402
 403         /*
 404          * For as long as the tracer isn't disabled another entity can't
 405          * change its status.  As such we can read the status here without
 406          * fearing it will change under us.
 407          */
 408         mode = local_read(&drvdata->mode);
 409
 410         switch (mode) {
 411         case CS_MODE_DISABLED:
 412                 break;
 413         case CS_MODE_SYSFS:
 414                 etm4_disable_sysfs(csdev);
 415                 break;
 416         case CS_MODE_PERF:
 417                 etm4_disable_perf(csdev, event);
 418                 break;
 419         }
 420
 421         if (mode)
 422                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 423 }
 424
 425 static const struct coresight_ops_source etm4_source_ops = {
 426         .cpu_id         = etm4_cpu_id,
 427         .trace_id       = etm4_trace_id,
 428         .enable         = etm4_enable,
 429         .disable        = etm4_disable,
 430 };
 431
 432 static const struct coresight_ops etm4_cs_ops = {
 433         .source_ops     = &etm4_source_ops,
 434 };
 435
 436 static void etm4_init_arch_data(void *info)
 437 {
 438         u32 etmidr0;
 439         u32 etmidr1;
 440         u32 etmidr2;
 441         u32 etmidr3;
 442         u32 etmidr4;
 443         u32 etmidr5;
 444         struct etmv4_drvdata *drvdata = info;
 445
 446         /* Make sure all registers are accessible */
 447         etm4_os_unlock(drvdata);
 448
 449         CS_UNLOCK(drvdata->base);
 450
 451         /* find all capabilities of the tracing unit */
 452         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 453
 454         /* INSTP0, bits[2:1] P0 tracing support field */
 455         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 456                 drvdata->instrp0 = true;
 457         else
 458                 drvdata->instrp0 = false;
 459
 460         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 461         if (BMVAL(etmidr0, 5, 5))
 462                 drvdata->trcbb = true;
 463         else
 464                 drvdata->trcbb = false;
 465
 466         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 467         if (BMVAL(etmidr0, 6, 6))
 468                 drvdata->trccond = true;
 469         else
 470                 drvdata->trccond = false;
 471
 472         /* TRCCCI, bit[7] Cycle counting instruction bit */
 473         if (BMVAL(etmidr0, 7, 7))
 474                 drvdata->trccci = true;
 475         else
 476                 drvdata->trccci = false;
 477
 478         /* RETSTACK, bit[9] Return stack bit */
 479         if (BMVAL(etmidr0, 9, 9))
 480                 drvdata->retstack = true;
 481         else
 482                 drvdata->retstack = false;
 483
 484         /* NUMEVENT, bits[11:10] Number of events field */
 485         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 486         /* QSUPP, bits[16:15] Q element support field */
 487         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 488         /* TSSIZE, bits[28:24] Global timestamp size field */
 489         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 490
 491         /* base architecture of trace unit */
 492         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 493         /*
 494          * TRCARCHMIN, bits[7:4] architecture the minor version number
 495          * TRCARCHMAJ, bits[11:8] architecture major versin number
 496          */
 497         drvdata->arch = BMVAL(etmidr1, 4, 11);
 498
 499         /* maximum size of resources */
 500         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 501         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 502         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 503         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 504         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 505         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 506         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 507
 508         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 509         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 510         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 511         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 512         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 513         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 514         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 515
 516         /*
 517          * TRCERR, bit[24] whether a trace unit can trace a
 518          * system error exception.
 519          */
 520         if (BMVAL(etmidr3, 24, 24))
 521                 drvdata->trc_error = true;
 522         else
 523                 drvdata->trc_error = false;
 524
 525         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 526         if (BMVAL(etmidr3, 25, 25))
 527                 drvdata->syncpr = true;
 528         else
 529                 drvdata->syncpr = false;
 530
 531         /* STALLCTL, bit[26] is stall control implemented? */
 532         if (BMVAL(etmidr3, 26, 26))
 533                 drvdata->stallctl = true;
 534         else
 535                 drvdata->stallctl = false;
 536
 537         /* SYSSTALL, bit[27] implementation can support stall control? */
 538         if (BMVAL(etmidr3, 27, 27))
 539                 drvdata->sysstall = true;
 540         else
 541                 drvdata->sysstall = false;
 542
 543         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 544         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 545
 546         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 547         if (BMVAL(etmidr3, 31, 31))
 548                 drvdata->nooverflow = true;
 549         else
 550                 drvdata->nooverflow = false;
 551
 552         /* number of resources trace unit supports */
 553         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 554         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 555         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 556         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 557         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 558         /*
 559          * NUMRSPAIR, bits[19:16]
 560          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 561          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 562          * As such add 1 to the value of NUMRSPAIR for a better representation.
 563          */
 564         drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 565         /*
 566          * NUMSSCC, bits[23:20] the number of single-shot
 567          * comparator control for tracing
 568          */
 569         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 570         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 571         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 572         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 573         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 574
 575         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 576         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 577         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 578         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 579         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 580         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 581         if (BMVAL(etmidr5, 22, 22))
 582                 drvdata->atbtrig = true;
 583         else
 584                 drvdata->atbtrig = false;
 585         /*
 586          * LPOVERRIDE, bit[23] implementation supports
 587          * low-power state override
 588          */
 589         if (BMVAL(etmidr5, 23, 23))
 590                 drvdata->lpoverride = true;
 591         else
 592                 drvdata->lpoverride = false;
 593         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 594         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 595         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 596         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 597         CS_LOCK(drvdata->base);
 598 }
 599
 600 static void etm4_set_default_config(struct etmv4_config *config)
 601 {
 602         /* disable all events tracing */
 603         config->eventctrl0 = 0x0;
 604         config->eventctrl1 = 0x0;
 605
 606         /* disable stalling */
 607         config->stall_ctrl = 0x0;
 608
 609         /* enable trace synchronization every 4096 bytes, if available */
 610         config->syncfreq = 0xC;
 611
 612         /* disable timestamp event */
 613         config->ts_ctrl = 0x0;
 614
 615         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 616         config->vinst_ctrl |= BIT(0);
 617 }
 618
 619 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 620 {
 621         u64 access_type = 0;
 622
 623         /*
 624          * EXLEVEL_NS, bits[15:12]
 625          * The Exception levels are:
 626          *   Bit[12] Exception level 0 - Application
 627          *   Bit[13] Exception level 1 - OS
 628          *   Bit[14] Exception level 2 - Hypervisor
 629          *   Bit[15] Never implemented
 630          */
 631         if (!is_kernel_in_hyp_mode()) {
 632                 /* Stay away from hypervisor mode for non-VHE */
 633                 access_type =  ETM_EXLEVEL_NS_HYP;
 634                 if (config->mode & ETM_MODE_EXCL_KERN)
 635                         access_type |= ETM_EXLEVEL_NS_OS;
 636         } else if (config->mode & ETM_MODE_EXCL_KERN) {
 637                 access_type = ETM_EXLEVEL_NS_HYP;
 638         }
 639
 640         if (config->mode & ETM_MODE_EXCL_USER)
 641                 access_type |= ETM_EXLEVEL_NS_APP;
 642
 643         return access_type;
 644 }
 645
 646 static u64 etm4_get_access_type(struct etmv4_config *config)
 647 {
 648         u64 access_type = etm4_get_ns_access_type(config);
 649
 650         /*
 651          * EXLEVEL_S, bits[11:8], don't trace anything happening
 652          * in secure state.
 653          */
 654         access_type |= (ETM_EXLEVEL_S_APP       |
 655                         ETM_EXLEVEL_S_OS        |
 656                         ETM_EXLEVEL_S_HYP);
 657
 658         return access_type;
 659 }
 660
 661 static void etm4_set_comparator_filter(struct etmv4_config *config,
 662                                        u64 start, u64 stop, int comparator)
 663 {
 664         u64 access_type = etm4_get_access_type(config);
 665
 666         /* First half of default address comparator */
 667         config->addr_val[comparator] = start;
 668         config->addr_acc[comparator] = access_type;
 669         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 670
 671         /* Second half of default address comparator */
 672         config->addr_val[comparator + 1] = stop;
 673         config->addr_acc[comparator + 1] = access_type;
 674         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 675
 676         /*
 677          * Configure the ViewInst function to include this address range
 678          * comparator.
 679          *
 680          * @comparator is divided by two since it is the index in the
 681          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
 682          * address range comparator _pairs_.
 683          *
 684          * Therefore:
 685          *      index 0 -> compatator pair 0
 686          *      index 2 -> comparator pair 1
 687          *      index 4 -> comparator pair 2
 688          *      ...
 689          *      index 14 -> comparator pair 7
 690          */
 691         config->viiectlr |= BIT(comparator / 2);
 692 }
 693
 694 static void etm4_set_start_stop_filter(struct etmv4_config *config,
 695                                        u64 address, int comparator,
 696                                        enum etm_addr_type type)
 697 {
 698         int shift;
 699         u64 access_type = etm4_get_access_type(config);
 700
 701         /* Configure the comparator */
 702         config->addr_val[comparator] = address;
 703         config->addr_acc[comparator] = access_type;
 704         config->addr_type[comparator] = type;
 705
 706         /*
 707          * Configure ViewInst Start-Stop control register.
 708          * Addresses configured to start tracing go from bit 0 to n-1,
 709          * while those configured to stop tracing from 16 to 16 + n-1.
 710          */
 711         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
 712         config->vissctlr |= BIT(shift + comparator);
 713 }
 714
 715 static void etm4_set_default_filter(struct etmv4_config *config)
 716 {
 717         u64 start, stop;
 718
 719         /*
 720          * Configure address range comparator '0' to encompass all
 721          * possible addresses.
 722          */
 723         start = 0x0;
 724         stop = ~0x0;
 725
 726         etm4_set_comparator_filter(config, start, stop,
 727                                    ETM_DEFAULT_ADDR_COMP);
 728
 729         /*
 730          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 731          * in the started state
 732          */
 733         config->vinst_ctrl |= BIT(9);
 734
 735         /* No start-stop filtering for ViewInst */
 736         config->vissctlr = 0x0;
 737 }
 738
 739 static void etm4_set_default(struct etmv4_config *config)
 740 {
 741         if (WARN_ON_ONCE(!config))
 742                 return;
 743
 744         /*
 745          * Make default initialisation trace everything
 746          *
 747          * Select the "always true" resource selector on the
 748          * "Enablign Event" line and configure address range comparator
 749          * '0' to trace all the possible address range.  From there
 750          * configure the "include/exclude" engine to include address
 751          * range comparator '0'.
 752          */
 753         etm4_set_default_config(config);
 754         etm4_set_default_filter(config);
 755 }
 756
 757 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
 758 {
 759         int nr_comparator, index = 0;
 760         struct etmv4_config *config = &drvdata->config;
 761
 762         /*
 763          * nr_addr_cmp holds the number of comparator _pair_, so time 2
 764          * for the total number of comparators.
 765          */
 766         nr_comparator = drvdata->nr_addr_cmp * 2;
 767
 768         /* Go through the tally of comparators looking for a free one. */
 769         while (index < nr_comparator) {
 770                 switch (type) {
 771                 case ETM_ADDR_TYPE_RANGE:
 772                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
 773                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
 774                                 return index;
 775
 776                         /* Address range comparators go in pairs */
 777                         index += 2;
 778                         break;
 779                 case ETM_ADDR_TYPE_START:
 780                 case ETM_ADDR_TYPE_STOP:
 781                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
 782                                 return index;
 783
 784                         /* Start/stop address can have odd indexes */
 785                         index += 1;
 786                         break;
 787                 default:
 788                         return -EINVAL;
 789                 }
 790         }
 791
 792         /* If we are here all the comparators have been used. */
 793         return -ENOSPC;
 794 }
 795
 796 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
 797                                   struct perf_event *event)
 798 {
 799         int i, comparator, ret = 0;
 800         u64 address;
 801         struct etmv4_config *config = &drvdata->config;
 802         struct etm_filters *filters = event->hw.addr_filters;
 803
 804         if (!filters)
 805                 goto default_filter;
 806
 807         /* Sync events with what Perf got */
 808         perf_event_addr_filters_sync(event);
 809
 810         /*
 811          * If there are no filters to deal with simply go ahead with
 812          * the default filter, i.e the entire address range.
 813          */
 814         if (!filters->nr_filters)
 815                 goto default_filter;
 816
 817         for (i = 0; i < filters->nr_filters; i++) {
 818                 struct etm_filter *filter = &filters->etm_filter[i];
 819                 enum etm_addr_type type = filter->type;
 820
 821                 /* See if a comparator is free. */
 822                 comparator = etm4_get_next_comparator(drvdata, type);
 823                 if (comparator < 0) {
 824                         ret = comparator;
 825                         goto out;
 826                 }
 827
 828                 switch (type) {
 829                 case ETM_ADDR_TYPE_RANGE:
 830                         etm4_set_comparator_filter(config,
 831                                                    filter->start_addr,
 832                                                    filter->stop_addr,
 833                                                    comparator);
 834                         /*
 835                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 836                          * in the started state
 837                          */
 838                         config->vinst_ctrl |= BIT(9);
 839
 840                         /* No start-stop filtering for ViewInst */
 841                         config->vissctlr = 0x0;
 842                         break;
 843                 case ETM_ADDR_TYPE_START:
 844                 case ETM_ADDR_TYPE_STOP:
 845                         /* Get the right start or stop address */
 846                         address = (type == ETM_ADDR_TYPE_START ?
 847                                    filter->start_addr :
 848                                    filter->stop_addr);
 849
 850                         /* Configure comparator */
 851                         etm4_set_start_stop_filter(config, address,
 852                                                    comparator, type);
 853
 854                         /*
 855                          * If filters::ssstatus == 1, trace acquisition was
 856                          * started but the process was yanked away before the
 857                          * the stop address was hit.  As such the start/stop
 858                          * logic needs to be re-started so that tracing can
 859                          * resume where it left.
 860                          *
 861                          * The start/stop logic status when a process is
 862                          * scheduled out is checked in function
 863                          * etm4_disable_perf().
 864                          */
 865                         if (filters->ssstatus)
 866                                 config->vinst_ctrl |= BIT(9);
 867
 868                         /* No include/exclude filtering for ViewInst */
 869                         config->viiectlr = 0x0;
 870                         break;
 871                 default:
 872                         ret = -EINVAL;
 873                         goto out;
 874                 }
 875         }
 876
 877         goto out;
 878
 879
 880 default_filter:
 881         etm4_set_default_filter(config);
 882
 883 out:
 884         return ret;
 885 }
 886
 887 void etm4_config_trace_mode(struct etmv4_config *config)
 888 {
 889         u32 addr_acc, mode;
 890
 891         mode = config->mode;
 892         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
 893
 894         /* excluding kernel AND user space doesn't make sense */
 895         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
 896
 897         /* nothing to do if neither flags are set */
 898         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
 899                 return;
 900
 901         addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
 902         /* clear default config */
 903         addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
 904                       ETM_EXLEVEL_NS_HYP);
 905
 906         addr_acc |= etm4_get_ns_access_type(config);
 907
 908         config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
 909         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
 910 }
 911
 912 static int etm4_online_cpu(unsigned int cpu)
 913 {
 914         if (!etmdrvdata[cpu])
 915                 return 0;
 916
 917         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
 918                 coresight_enable(etmdrvdata[cpu]->csdev);
 919         return 0;
 920 }
 921
 922 static int etm4_starting_cpu(unsigned int cpu)
 923 {
 924         if (!etmdrvdata[cpu])
 925                 return 0;
 926
 927         spin_lock(&etmdrvdata[cpu]->spinlock);
 928         if (!etmdrvdata[cpu]->os_unlock) {
 929                 etm4_os_unlock(etmdrvdata[cpu]);
 930                 etmdrvdata[cpu]->os_unlock = true;
 931         }
 932
 933         if (local_read(&etmdrvdata[cpu]->mode))
 934                 etm4_enable_hw(etmdrvdata[cpu]);
 935         spin_unlock(&etmdrvdata[cpu]->spinlock);
 936         return 0;
 937 }
 938
 939 static int etm4_dying_cpu(unsigned int cpu)
 940 {
 941         if (!etmdrvdata[cpu])
 942                 return 0;
 943
 944         spin_lock(&etmdrvdata[cpu]->spinlock);
 945         if (local_read(&etmdrvdata[cpu]->mode))
 946                 etm4_disable_hw(etmdrvdata[cpu]);
 947         spin_unlock(&etmdrvdata[cpu]->spinlock);
 948         return 0;
 949 }
 950
 951 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
 952 {
 953         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
 954 }
 955
 956 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 957 {
 958         int ret;
 959         void __iomem *base;
 960         struct device *dev = &adev->dev;
 961         struct coresight_platform_data *pdata = NULL;
 962         struct etmv4_drvdata *drvdata;
 963         struct resource *res = &adev->res;
 964         struct coresight_desc desc = { 0 };
 965         struct device_node *np = adev->dev.of_node;
 966
 967         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 968         if (!drvdata)
 969                 return -ENOMEM;
 970
 971         if (np) {
 972                 pdata = of_get_coresight_platform_data(dev, np);
 973                 if (IS_ERR(pdata))
 974                         return PTR_ERR(pdata);
 975                 adev->dev.platform_data = pdata;
 976         }
 977
 978         drvdata->dev = &adev->dev;
 979         dev_set_drvdata(dev, drvdata);
 980
 981         /* Validity for the resource is already checked by the AMBA core */
 982         base = devm_ioremap_resource(dev, res);
 983         if (IS_ERR(base))
 984                 return PTR_ERR(base);
 985
 986         drvdata->base = base;
 987
 988         spin_lock_init(&drvdata->spinlock);
 989
 990         drvdata->cpu = pdata ? pdata->cpu : 0;
 991
 992         get_online_cpus();
 993         etmdrvdata[drvdata->cpu] = drvdata;
 994
 995         if (smp_call_function_single(drvdata->cpu,
 996                                 etm4_init_arch_data,  drvdata, 1))
 997                 dev_err(dev, "ETM arch init failed\n");
 998
 999         if (!etm4_count++) {
1000                 cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT4_STARTING,
1001                                           "AP_ARM_CORESIGHT4_STARTING",
1002                                           etm4_starting_cpu, etm4_dying_cpu);
1003                 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1004                                                 "AP_ARM_CORESIGHT4_ONLINE",
1005                                                 etm4_online_cpu, NULL);
1006                 if (ret < 0)
1007                         goto err_arch_supported;
1008                 hp_online = ret;
1009         }
1010
1011         put_online_cpus();
1012
1013         if (etm4_arch_supported(drvdata->arch) == false) {
1014                 ret = -EINVAL;
1015                 goto err_arch_supported;
1016         }
1017
1018         etm4_init_trace_id(drvdata);
1019         etm4_set_default(&drvdata->config);
1020
1021         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1022         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1023         desc.ops = &etm4_cs_ops;
1024         desc.pdata = pdata;
1025         desc.dev = dev;
1026         desc.groups = coresight_etmv4_groups;
1027         drvdata->csdev = coresight_register(&desc);
1028         if (IS_ERR(drvdata->csdev)) {
1029                 ret = PTR_ERR(drvdata->csdev);
1030                 goto err_arch_supported;
1031         }
1032
1033         ret = etm_perf_symlink(drvdata->csdev, true);
1034         if (ret) {
1035                 coresight_unregister(drvdata->csdev);
1036                 goto err_arch_supported;
1037         }
1038
1039         pm_runtime_put(&adev->dev);
1040         dev_info(dev, "%s initialized\n", (char *)id->data);
1041
1042         if (boot_enable) {
1043                 coresight_enable(drvdata->csdev);
1044                 drvdata->boot_enable = true;
1045         }
1046
1047         return 0;
1048
1049 err_arch_supported:
1050         if (--etm4_count == 0) {
1051                 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT4_STARTING);
1052                 if (hp_online)
1053                         cpuhp_remove_state_nocalls(hp_online);
1054         }
1055         return ret;
1056 }
1057
1058 static struct amba_id etm4_ids[] = {
1059         {       /* ETM 4.0 - Cortex-A53  */
1060                 .id     = 0x000bb95d,
1061                 .mask   = 0x000fffff,
1062                 .data   = "ETM 4.0",
1063         },
1064         {       /* ETM 4.0 - Cortex-A57 */
1065                 .id     = 0x000bb95e,
1066                 .mask   = 0x000fffff,
1067                 .data   = "ETM 4.0",
1068         },
1069         {       /* ETM 4.0 - A72, Maia, HiSilicon */
1070                 .id = 0x000bb95a,
1071                 .mask = 0x000fffff,
1072                 .data = "ETM 4.0",
1073         },
1074         { 0, 0},
1075 };
1076
1077 static struct amba_driver etm4x_driver = {
1078         .drv = {
1079                 .name   = "coresight-etm4x",
1080                 .suppress_bind_attrs = true,
1081         },
1082         .probe          = etm4_probe,
1083         .id_table       = etm4_ids,
1084 };
1085 builtin_amba_driver(etm4x_driver);