2 * Copyright (c) 2017 Linaro Limited. All rights reserved.
4 * Author: Leo Yan <leo.yan@linaro.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/amba/bus.h>
20 #include <linux/coresight.h>
21 #include <linux/cpu.h>
22 #include <linux/debugfs.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
28 #include <linux/iopoll.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/pm_qos.h>
33 #include <linux/slab.h>
34 #include <linux/smp.h>
35 #include <linux/types.h>
36 #include <linux/uaccess.h>
38 #include "coresight-priv.h"
43 #define EDPCSR_HI 0x0AC
47 #define EDDEVID1 0xFC4
50 #define EDPCSR_PROHIBITED 0xFFFFFFFF
52 /* bits definition for EDPCSR */
53 #define EDPCSR_THUMB BIT(0)
54 #define EDPCSR_ARM_INST_MASK GENMASK(31, 2)
55 #define EDPCSR_THUMB_INST_MASK GENMASK(31, 1)
57 /* bits definition for EDPRCR */
58 #define EDPRCR_COREPURQ BIT(3)
59 #define EDPRCR_CORENPDRQ BIT(0)
61 /* bits definition for EDPRSR */
62 #define EDPRSR_DLK BIT(6)
63 #define EDPRSR_PU BIT(0)
65 /* bits definition for EDVIDSR */
66 #define EDVIDSR_NS BIT(31)
67 #define EDVIDSR_E2 BIT(30)
68 #define EDVIDSR_E3 BIT(29)
69 #define EDVIDSR_HV BIT(28)
70 #define EDVIDSR_VMID GENMASK(7, 0)
73 * bits definition for EDDEVID1:PSCROffset
75 * NOTE: armv8 and armv7 have different definition for the register,
76 * so consolidate the bits definition as below:
78 * 0b0000 - Sample offset applies based on the instruction state, we
79 * rely on EDDEVID to check if EDPCSR is implemented or not
80 * 0b0001 - No offset applies.
81 * 0b0010 - No offset applies, but do not use in AArch32 mode
84 #define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0)
85 #define EDDEVID1_PCSR_OFFSET_INS_SET (0x0)
86 #define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 (0x2)
88 /* bits definition for EDDEVID */
89 #define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0)
90 #define EDDEVID_IMPL_EDPCSR (0x1)
91 #define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2)
92 #define EDDEVID_IMPL_FULL (0x3)
94 #define DEBUG_WAIT_SLEEP 1000
95 #define DEBUG_WAIT_TIMEOUT 32000
97 struct debug_drvdata {
103 bool edcidsr_present;
104 bool edvidsr_present;
114 static DEFINE_MUTEX(debug_lock);
115 static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata);
116 static int debug_count;
117 static struct dentry *debug_debugfs_dir;
119 static bool debug_enable;
120 module_param_named(enable, debug_enable, bool, 0600);
121 MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
123 static void debug_os_unlock(struct debug_drvdata *drvdata)
125 /* Unlocks the debug registers */
126 writel_relaxed(0x0, drvdata->base + EDOSLAR);
128 /* Make sure the registers are unlocked before accessing */
133 * According to ARM DDI 0487A.k, before access external debug
134 * registers should firstly check the access permission; if any
135 * below condition has been met then cannot access debug
136 * registers to avoid lockup issue:
138 * - CPU power domain is powered off;
139 * - The OS Double Lock is locked;
141 * By checking EDPRSR can get to know if meet these conditions.
143 static bool debug_access_permitted(struct debug_drvdata *drvdata)
145 /* CPU is powered off */
146 if (!(drvdata->edprsr & EDPRSR_PU))
149 /* The OS Double Lock is locked */
150 if (drvdata->edprsr & EDPRSR_DLK)
156 static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
163 * Send request to power management controller and assert
164 * DBGPWRUPREQ signal; if power management controller has
165 * sane implementation, it should enable CPU power domain
166 * in case CPU is in low power state.
168 edprcr = readl_relaxed(drvdata->base + EDPRCR);
169 edprcr |= EDPRCR_COREPURQ;
170 writel_relaxed(edprcr, drvdata->base + EDPRCR);
172 /* Wait for CPU to be powered up (timeout~=32ms) */
173 if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR,
174 drvdata->edprsr, (drvdata->edprsr & EDPRSR_PU),
175 DEBUG_WAIT_SLEEP, DEBUG_WAIT_TIMEOUT)) {
177 * Unfortunately the CPU cannot be powered up, so return
178 * back and later has no permission to access other
179 * registers. For this case, should disable CPU low power
180 * states to ensure CPU power domain is enabled!
182 dev_err(drvdata->dev, "%s: power up request for CPU%d failed\n",
183 __func__, drvdata->cpu);
188 * At this point the CPU is powered up, so set the no powerdown
189 * request bit so we don't lose power and emulate power down.
191 edprcr = readl_relaxed(drvdata->base + EDPRCR);
192 edprcr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
193 writel_relaxed(edprcr, drvdata->base + EDPRCR);
195 drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR);
197 /* The core power domain got switched off on use, try again */
198 if (unlikely(!(drvdata->edprsr & EDPRSR_PU)))
202 static void debug_read_regs(struct debug_drvdata *drvdata)
206 CS_UNLOCK(drvdata->base);
209 debug_os_unlock(drvdata);
211 /* Save EDPRCR register */
212 save_edprcr = readl_relaxed(drvdata->base + EDPRCR);
215 * Ensure CPU power domain is enabled to let registers
218 debug_force_cpu_powered_up(drvdata);
220 if (!debug_access_permitted(drvdata))
223 drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR);
226 * As described in ARM DDI 0487A.k, if the processing
227 * element (PE) is in debug state, or sample-based
228 * profiling is prohibited, EDPCSR reads as 0xFFFFFFFF;
229 * EDCIDSR, EDVIDSR and EDPCSR_HI registers also become
230 * UNKNOWN state. So directly bail out for this case.
232 if (drvdata->edpcsr == EDPCSR_PROHIBITED)
236 * A read of the EDPCSR normally has the side-effect of
237 * indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI;
238 * at this point it's safe to read value from them.
240 if (IS_ENABLED(CONFIG_64BIT))
241 drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI);
243 if (drvdata->edcidsr_present)
244 drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR);
246 if (drvdata->edvidsr_present)
247 drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR);
250 /* Restore EDPRCR register */
251 writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
253 CS_LOCK(drvdata->base);
257 static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
259 return (unsigned long)drvdata->edpcsr_hi << 32 |
260 (unsigned long)drvdata->edpcsr;
263 static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
265 unsigned long arm_inst_offset = 0, thumb_inst_offset = 0;
268 pc = (unsigned long)drvdata->edpcsr;
270 if (drvdata->pc_has_offset) {
272 thumb_inst_offset = 4;
275 /* Handle thumb instruction */
276 if (pc & EDPCSR_THUMB) {
277 pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset;
282 * Handle arm instruction offset, if the arm instruction
283 * is not 4 byte alignment then it's possible the case
284 * for implementation defined; keep original value for this
285 * case and print info for notice.
288 dev_emerg(drvdata->dev,
289 "Instruction offset is implementation defined\n");
291 pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset;
297 static void debug_dump_regs(struct debug_drvdata *drvdata)
299 struct device *dev = drvdata->dev;
302 dev_emerg(dev, " EDPRSR: %08x (Power:%s DLK:%s)\n",
304 drvdata->edprsr & EDPRSR_PU ? "On" : "Off",
305 drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock");
307 if (!debug_access_permitted(drvdata)) {
308 dev_emerg(dev, "No permission to access debug registers!\n");
312 if (drvdata->edpcsr == EDPCSR_PROHIBITED) {
313 dev_emerg(dev, "CPU is in Debug state or profiling is prohibited!\n");
317 pc = debug_adjust_pc(drvdata);
318 dev_emerg(dev, " EDPCSR: [<%px>] %pS\n", (void *)pc, (void *)pc);
320 if (drvdata->edcidsr_present)
321 dev_emerg(dev, " EDCIDSR: %08x\n", drvdata->edcidsr);
323 if (drvdata->edvidsr_present)
324 dev_emerg(dev, " EDVIDSR: %08x (State:%s Mode:%s Width:%dbits VMID:%x)\n",
326 drvdata->edvidsr & EDVIDSR_NS ?
327 "Non-secure" : "Secure",
328 drvdata->edvidsr & EDVIDSR_E3 ? "EL3" :
329 (drvdata->edvidsr & EDVIDSR_E2 ?
331 drvdata->edvidsr & EDVIDSR_HV ? 64 : 32,
332 drvdata->edvidsr & (u32)EDVIDSR_VMID);
335 static void debug_init_arch_data(void *info)
337 struct debug_drvdata *drvdata = info;
338 u32 mode, pcsr_offset;
339 u32 eddevid, eddevid1;
341 CS_UNLOCK(drvdata->base);
343 /* Read device info */
344 eddevid = readl_relaxed(drvdata->base + EDDEVID);
345 eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
347 CS_LOCK(drvdata->base);
349 /* Parse implementation feature */
350 mode = eddevid & EDDEVID_PCSAMPLE_MODE;
351 pcsr_offset = eddevid1 & EDDEVID1_PCSR_OFFSET_MASK;
353 drvdata->edpcsr_present = false;
354 drvdata->edcidsr_present = false;
355 drvdata->edvidsr_present = false;
356 drvdata->pc_has_offset = false;
359 case EDDEVID_IMPL_FULL:
360 drvdata->edvidsr_present = true;
362 case EDDEVID_IMPL_EDPCSR_EDCIDSR:
363 drvdata->edcidsr_present = true;
365 case EDDEVID_IMPL_EDPCSR:
367 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to
368 * define if has the offset for PC sampling value; if read
369 * back EDDEVID1.PCSROffset == 0x2, then this means the debug
370 * module does not sample the instruction set state when
371 * armv8 CPU in AArch32 state.
373 drvdata->edpcsr_present =
374 ((IS_ENABLED(CONFIG_64BIT) && pcsr_offset != 0) ||
375 (pcsr_offset != EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32));
377 drvdata->pc_has_offset =
378 (pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET);
386 * Dump out information on panic.
388 static int debug_notifier_call(struct notifier_block *self,
389 unsigned long v, void *p)
392 struct debug_drvdata *drvdata;
394 /* Bail out if we can't acquire the mutex or the functionality is off */
395 if (!mutex_trylock(&debug_lock))
401 pr_emerg("ARM external debug module:\n");
403 for_each_possible_cpu(cpu) {
404 drvdata = per_cpu(debug_drvdata, cpu);
408 dev_emerg(drvdata->dev, "CPU[%d]:\n", drvdata->cpu);
410 debug_read_regs(drvdata);
411 debug_dump_regs(drvdata);
415 mutex_unlock(&debug_lock);
419 static struct notifier_block debug_notifier = {
420 .notifier_call = debug_notifier_call,
423 static int debug_enable_func(void)
425 struct debug_drvdata *drvdata;
430 * Use cpumask to track which debug power domains have
431 * been powered on and use it to handle failure case.
433 cpumask_clear(&mask);
435 for_each_possible_cpu(cpu) {
436 drvdata = per_cpu(debug_drvdata, cpu);
440 ret = pm_runtime_get_sync(drvdata->dev);
444 cpumask_set_cpu(cpu, &mask);
451 * If pm_runtime_get_sync() has failed, need rollback on
452 * all the other CPUs that have been enabled before that.
454 for_each_cpu(cpu, &mask) {
455 drvdata = per_cpu(debug_drvdata, cpu);
456 pm_runtime_put_noidle(drvdata->dev);
462 static int debug_disable_func(void)
464 struct debug_drvdata *drvdata;
465 int cpu, ret, err = 0;
468 * Disable debug power domains, records the error and keep
469 * circling through all other CPUs when an error has been
472 for_each_possible_cpu(cpu) {
473 drvdata = per_cpu(debug_drvdata, cpu);
477 ret = pm_runtime_put(drvdata->dev);
485 static ssize_t debug_func_knob_write(struct file *f,
486 const char __user *buf, size_t count, loff_t *ppos)
491 ret = kstrtou8_from_user(buf, count, 2, &val);
495 mutex_lock(&debug_lock);
497 if (val == debug_enable)
501 ret = debug_enable_func();
503 ret = debug_disable_func();
506 pr_err("%s: unable to %s debug function: %d\n",
507 __func__, val ? "enable" : "disable", ret);
515 mutex_unlock(&debug_lock);
519 static ssize_t debug_func_knob_read(struct file *f,
520 char __user *ubuf, size_t count, loff_t *ppos)
525 mutex_lock(&debug_lock);
526 snprintf(buf, sizeof(buf), "%d\n", debug_enable);
527 mutex_unlock(&debug_lock);
529 ret = simple_read_from_buffer(ubuf, count, ppos, buf, sizeof(buf));
533 static const struct file_operations debug_func_knob_fops = {
535 .read = debug_func_knob_read,
536 .write = debug_func_knob_write,
539 static int debug_func_init(void)
544 /* Create debugfs node */
545 debug_debugfs_dir = debugfs_create_dir("coresight_cpu_debug", NULL);
546 if (!debug_debugfs_dir) {
547 pr_err("%s: unable to create debugfs directory\n", __func__);
551 file = debugfs_create_file("enable", 0644, debug_debugfs_dir, NULL,
552 &debug_func_knob_fops);
554 pr_err("%s: unable to create enable knob file\n", __func__);
559 /* Register function to be called for panic */
560 ret = atomic_notifier_chain_register(&panic_notifier_list,
563 pr_err("%s: unable to register notifier: %d\n",
571 debugfs_remove_recursive(debug_debugfs_dir);
575 static void debug_func_exit(void)
577 atomic_notifier_chain_unregister(&panic_notifier_list,
579 debugfs_remove_recursive(debug_debugfs_dir);
582 static int debug_probe(struct amba_device *adev, const struct amba_id *id)
585 struct device *dev = &adev->dev;
586 struct debug_drvdata *drvdata;
587 struct resource *res = &adev->res;
588 struct device_node *np = adev->dev.of_node;
591 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
595 drvdata->cpu = np ? of_coresight_get_cpu(np) : 0;
596 if (per_cpu(debug_drvdata, drvdata->cpu)) {
597 dev_err(dev, "CPU%d drvdata has already been initialized\n",
602 drvdata->dev = &adev->dev;
603 amba_set_drvdata(adev, drvdata);
605 /* Validity for the resource is already checked by the AMBA core */
606 base = devm_ioremap_resource(dev, res);
608 return PTR_ERR(base);
610 drvdata->base = base;
613 per_cpu(debug_drvdata, drvdata->cpu) = drvdata;
614 ret = smp_call_function_single(drvdata->cpu, debug_init_arch_data,
619 dev_err(dev, "CPU%d debug arch init failed\n", drvdata->cpu);
623 if (!drvdata->edpcsr_present) {
624 dev_err(dev, "CPU%d sample-based profiling isn't implemented\n",
630 if (!debug_count++) {
631 ret = debug_func_init();
636 mutex_lock(&debug_lock);
637 /* Turn off debug power domain if debugging is disabled */
640 mutex_unlock(&debug_lock);
642 dev_info(dev, "Coresight debug-CPU%d initialized\n", drvdata->cpu);
648 per_cpu(debug_drvdata, drvdata->cpu) = NULL;
652 static int debug_remove(struct amba_device *adev)
654 struct device *dev = &adev->dev;
655 struct debug_drvdata *drvdata = amba_get_drvdata(adev);
657 per_cpu(debug_drvdata, drvdata->cpu) = NULL;
659 mutex_lock(&debug_lock);
660 /* Turn off debug power domain before rmmod the module */
663 mutex_unlock(&debug_lock);
671 static const struct amba_id debug_ids[] = {
672 { /* Debug for Cortex-A53 */
676 { /* Debug for Cortex-A57 */
680 { /* Debug for Cortex-A72 */
684 { /* Debug for Cortex-A73 */
691 static struct amba_driver debug_driver = {
693 .name = "coresight-cpu-debug",
694 .suppress_bind_attrs = true,
696 .probe = debug_probe,
697 .remove = debug_remove,
698 .id_table = debug_ids,
701 module_amba_driver(debug_driver);
703 MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
704 MODULE_DESCRIPTION("ARM Coresight CPU Debug Driver");
705 MODULE_LICENSE("GPL");