1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
5 #include <linux/device.h>
6 #include <linux/hwmon.h>
7 #include <linux/hwmon-sysfs.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
15 #include <linux/sysfs.h>
16 #include <linux/thermal.h>
18 /* NPCM7XX PWM registers */
19 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
21 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
22 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
23 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
26 #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \
27 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))
28 #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \
29 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))
30 #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)
31 #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)
33 #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)
34 #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)
35 #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)
36 #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)
38 #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)
39 #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)
40 #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)
41 #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)
43 #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)
44 #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)
45 #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)
46 #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)
48 /* Define the maximum PWM channel number */
49 #define NPCM7XX_PWM_MAX_CHN_NUM 12
50 #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
51 #define NPCM7XX_PWM_MAX_MODULES 3
53 /* Define the Counter Register, value = 100 for match 100% */
54 #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255
55 #define NPCM7XX_PWM_CMR_DEFAULT_NUM 255
56 #define NPCM7XX_PWM_CMR_MAX 255
58 /* default all PWM channels PRESCALE2 = 1 */
59 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4
60 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40
61 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400
62 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000
64 #define PWM_OUTPUT_FREQ_25KHZ 25000
65 #define PWN_CNT_DEFAULT 256
66 #define MIN_PRESCALE1 2
67 #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8
69 #define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \
70 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \
71 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \
72 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)
74 #define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
75 NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
76 NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
77 NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
79 /* NPCM7XX FAN Tacho registers */
80 #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
82 #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)
83 #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)
84 #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)
85 #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)
86 #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)
87 #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)
88 #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)
89 #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)
90 #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)
91 #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)
92 #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)
93 #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)
94 #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)
95 #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)
96 #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)
98 #define NPCM7XX_FAN_TCKC_CLKX_NONE 0
99 #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0)
100 #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3)
102 #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6)
103 #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5)
104 #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4)
105 #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3)
106 #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2)
108 #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)
109 #define NPCM7XX_FAN_TICLR_TFCLR BIT(5)
110 #define NPCM7XX_FAN_TICLR_TECLR BIT(4)
111 #define NPCM7XX_FAN_TICLR_TDCLR BIT(3)
112 #define NPCM7XX_FAN_TICLR_TCCLR BIT(2)
113 #define NPCM7XX_FAN_TICLR_TBCLR BIT(1)
114 #define NPCM7XX_FAN_TICLR_TACLR BIT(0)
116 #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)
117 #define NPCM7XX_FAN_TIEN_TFIEN BIT(5)
118 #define NPCM7XX_FAN_TIEN_TEIEN BIT(4)
119 #define NPCM7XX_FAN_TIEN_TDIEN BIT(3)
120 #define NPCM7XX_FAN_TIEN_TCIEN BIT(2)
121 #define NPCM7XX_FAN_TIEN_TBIEN BIT(1)
122 #define NPCM7XX_FAN_TIEN_TAIEN BIT(0)
124 #define NPCM7XX_FAN_TICTRL_TFPND BIT(5)
125 #define NPCM7XX_FAN_TICTRL_TEPND BIT(4)
126 #define NPCM7XX_FAN_TICTRL_TDPND BIT(3)
127 #define NPCM7XX_FAN_TICTRL_TCPND BIT(2)
128 #define NPCM7XX_FAN_TICTRL_TBPND BIT(1)
129 #define NPCM7XX_FAN_TICTRL_TAPND BIT(0)
131 #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7)
132 #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6)
133 #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5)
134 #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4)
135 #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3)
136 #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2)
137 #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1)
138 #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0)
140 /* FAN General Definition */
141 /* Define the maximum FAN channel number */
142 #define NPCM7XX_FAN_MAX_MODULE 8
143 #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2
144 #define NPCM7XX_FAN_MAX_CHN_NUM 16
147 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
148 * Timeout 94ms ~= 0x5000
149 * (The minimum FAN speed could to support ~640RPM/pulse 1,
150 * 320RPM/pulse 2, ...-- 10.6Hz)
152 #define NPCM7XX_FAN_TIMEOUT 0x5000
153 #define NPCM7XX_FAN_TCNT 0xFFFF
154 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
155 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
157 #define NPCM7XX_FAN_POLL_TIMER_200MS 200
158 #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2
159 #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0
160 #define NPCM7XX_FAN_CLK_PRESCALE 255
162 #define NPCM7XX_FAN_CMPA 0
163 #define NPCM7XX_FAN_CMPB 1
165 /* Obtain the fan number */
166 #define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp))
168 /* fan sample status */
169 #define FAN_DISABLE 0xFF
170 #define FAN_INIT 0x00
171 #define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01
172 #define FAN_ENOUGH_SAMPLE 0x02
174 struct npcm_hwmon_info {
178 struct npcm7xx_fan_dev {
185 struct npcm7xx_cooling_device {
186 char name[THERMAL_NAME_LENGTH];
187 struct npcm7xx_pwm_fan_data *data;
188 struct thermal_cooling_device *tcdev;
195 struct npcm7xx_pwm_fan_data {
196 void __iomem *pwm_base;
197 void __iomem *fan_base;
199 unsigned long pwm_clk_freq;
200 unsigned long fan_clk_freq;
203 struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES];
204 spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];
205 int fan_irq[NPCM7XX_FAN_MAX_MODULE];
206 bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];
207 bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];
209 struct timer_list fan_timer;
210 struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];
211 struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];
212 const struct npcm_hwmon_info *info;
216 static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
217 int channel, u16 val)
219 u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
220 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
221 u32 tmp_buf, ctrl_en_bit, env_bit;
224 * Config PWM Comparator register for setting duty cycle
226 mutex_lock(&data->pwm_lock[module]);
228 /* write new CMR value */
229 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
230 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
234 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
235 env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;
238 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
239 env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;
242 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
243 env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;
246 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
247 env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;
250 mutex_unlock(&data->pwm_lock[module]);
256 tmp_buf &= ~ctrl_en_bit;
260 tmp_buf |= ctrl_en_bit;
264 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
265 mutex_unlock(&data->pwm_lock[module]);
270 static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
278 fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
280 /* to check whether any fan tach is enable */
281 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
283 spin_lock_irqsave(&data->fan_lock[fan], flags);
285 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
286 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
289 * the interrupt enable bits do not need to be cleared before
290 * it sets, the interrupt enable bits are cleared only on reset.
291 * the clock unit control register is behaving in the same
292 * manner that the interrupt enable register behave.
294 if (cmp == NPCM7XX_FAN_CMPA) {
295 /* enable interrupt */
296 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |
297 NPCM7XX_FAN_TIEN_TEIEN),
298 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
300 reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
301 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
304 /* start to Capture */
305 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
308 /* enable interrupt */
309 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |
310 NPCM7XX_FAN_TIEN_TFIEN),
311 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
314 NPCM7XX_FAN_TCKC_CLK2_APB
315 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
318 /* start to Capture */
320 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
323 spin_unlock_irqrestore(&data->fan_lock[fan], flags);
328 * Enable a background timer to poll fan tach value, (200ms * 4)
331 static void npcm7xx_fan_polling(struct timer_list *t)
333 struct npcm7xx_pwm_fan_data *data;
336 data = from_timer(data, t, fan_timer);
339 * Polling two module per one round,
340 * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415
342 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
344 /* clear the flag and reset the counter (TCNT) */
345 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
346 NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
348 if (data->fan_present[i * 2]) {
349 iowrite16(NPCM7XX_FAN_TCNT,
350 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
351 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
353 if (data->fan_present[(i * 2) + 1]) {
354 iowrite16(NPCM7XX_FAN_TCNT,
355 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
356 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
361 data->fan_select &= 0x3;
363 /* reset the timer interval */
364 data->fan_timer.expires = jiffies +
365 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
366 add_timer(&data->fan_timer);
369 static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
370 u8 fan, u8 cmp, u8 fan_id, u8 flag_int,
371 u8 flag_mode, u8 flag_clear)
377 if (cmp == NPCM7XX_FAN_CMPA)
378 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
380 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
382 /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */
383 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
385 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
386 /* First capture, drop it */
387 data->fan_dev[fan_id].fan_st_flg =
388 FAN_PREPARE_TO_GET_FIRST_CAPTURE;
391 data->fan_dev[fan_id].fan_cnt_tmp = 0;
392 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
394 * collect the enough sample,
395 * (ex: 2 pulse fan need to get 2 sample)
397 data->fan_dev[fan_id].fan_cnt_tmp +=
398 (NPCM7XX_FAN_TCNT - fan_cap);
400 data->fan_dev[fan_id].fan_st_flg++;
402 /* get enough sample or fan disable */
403 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
404 data->fan_dev[fan_id].fan_cnt_tmp +=
405 (NPCM7XX_FAN_TCNT - fan_cap);
407 /* compute finial average cnt per pulse */
408 data->fan_dev[fan_id].fan_cnt =
409 data->fan_dev[fan_id].fan_cnt_tmp /
412 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
415 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
417 /* disable interrupt */
418 iowrite8((reg_int & ~flag_int),
419 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
420 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
423 iowrite8((reg_mode & ~flag_mode),
424 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
428 static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
429 u8 fan, u8 cmp, u8 flag)
440 fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
442 if (cmp == NPCM7XX_FAN_CMPA) {
443 flag_cap = NPCM7XX_FAN_TICTRL_TAPND;
444 flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;
445 flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;
446 flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;
447 flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;
449 flag_cap = NPCM7XX_FAN_TICTRL_TBPND;
450 flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;
451 flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;
452 flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;
453 flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;
456 if (flag & flag_timeout) {
457 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
459 /* disable interrupt */
460 iowrite8((reg_int & ~flag_int),
461 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
463 /* clear interrupt flag */
465 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
467 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
470 iowrite8((reg_mode & ~flag_mode),
471 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
474 * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't
475 * connect or speed is lower than 10.6Hz (320RPM/pulse2).
476 * In these situation, the RPM output should be zero.
478 data->fan_dev[fan_id].fan_cnt = 0;
480 /* input capture is occurred */
482 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
483 flag_mode, flag_clear);
487 static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)
489 struct npcm7xx_pwm_fan_data *data = dev_id;
494 module = irq - data->fan_irq[0];
495 spin_lock_irqsave(&data->fan_lock[module], flags);
497 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
499 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
500 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
501 spin_unlock_irqrestore(&data->fan_lock[module], flags);
505 spin_unlock_irqrestore(&data->fan_lock[module], flags);
510 static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
513 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
514 u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
515 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
518 case hwmon_pwm_input:
520 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
527 static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
530 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
534 case hwmon_pwm_input:
535 if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)
537 err = npcm7xx_pwm_config_set(data, channel, (u16)val);
547 static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
549 const struct npcm7xx_pwm_fan_data *data = _data;
551 if (!data->pwm_present[channel] || channel >= data->info->pwm_max_channel)
555 case hwmon_pwm_input:
562 static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,
565 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
568 case hwmon_fan_input:
570 if (data->fan_dev[channel].fan_cnt <= 0)
571 return data->fan_dev[channel].fan_cnt;
573 /* Convert the raw reading to RPM */
574 if (data->fan_dev[channel].fan_cnt > 0 &&
575 data->fan_dev[channel].fan_pls_per_rev > 0)
576 *val = ((data->input_clk_freq * 60) /
577 (data->fan_dev[channel].fan_cnt *
578 data->fan_dev[channel].fan_pls_per_rev));
585 static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)
587 const struct npcm7xx_pwm_fan_data *data = _data;
589 if (!data->fan_present[channel])
593 case hwmon_fan_input:
600 static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
601 u32 attr, int channel, long *val)
605 return npcm7xx_read_pwm(dev, attr, channel, val);
607 return npcm7xx_read_fan(dev, attr, channel, val);
613 static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
614 u32 attr, int channel, long val)
618 return npcm7xx_write_pwm(dev, attr, channel, val);
624 static umode_t npcm7xx_is_visible(const void *data,
625 enum hwmon_sensor_types type,
626 u32 attr, int channel)
630 return npcm7xx_pwm_is_visible(data, attr, channel);
632 return npcm7xx_fan_is_visible(data, attr, channel);
638 static const struct hwmon_channel_info * const npcm7xx_info[] = {
639 HWMON_CHANNEL_INFO(pwm,
652 HWMON_CHANNEL_INFO(fan,
672 static const struct hwmon_ops npcm7xx_hwmon_ops = {
673 .is_visible = npcm7xx_is_visible,
674 .read = npcm7xx_read,
675 .write = npcm7xx_write,
678 static const struct hwmon_chip_info npcm7xx_chip_info = {
679 .ops = &npcm7xx_hwmon_ops,
680 .info = npcm7xx_info,
683 static const struct npcm_hwmon_info npxm7xx_hwmon_info = {
684 .pwm_max_channel = 8,
687 static const struct npcm_hwmon_info npxm8xx_hwmon_info = {
688 .pwm_max_channel = 12,
691 static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
694 u32 prescale_val, output_freq;
696 data->pwm_clk_freq = clk_get_rate(data->pwm_clk);
698 /* Adjust NPCM7xx PWMs output frequency to ~25Khz */
699 output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT;
700 prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
702 /* If prescale_val = 0, then the prescale output clock is stopped */
703 if (prescale_val < MIN_PRESCALE1)
704 prescale_val = MIN_PRESCALE1;
706 * prescale_val need to decrement in one because in the PWM Prescale
707 * register the Prescale value increment by one
711 /* Setting PWM Prescale Register value register to both modules */
712 prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
714 for (m = 0; m < data->pwm_modules; m++) {
715 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
716 iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,
717 NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
718 iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,
719 NPCM7XX_PWM_REG_CR(data->pwm_base, m));
721 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {
722 iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,
723 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
727 return output_freq / ((prescale_val & 0xf) + 1);
730 static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
737 for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {
738 /* stop FAN0~7 clock */
739 iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,
740 NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
742 /* disable all interrupt */
743 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
745 /* clear all interrupt */
746 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
747 NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
749 /* set FAN0~7 clock prescaler */
750 iowrite8(NPCM7XX_FAN_CLK_PRESCALE,
751 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
753 /* set FAN0~7 mode (high-to-low transition) */
754 iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |
755 NPCM7XX_FAN_TMCTRL_TAEN),
756 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
758 /* set FAN0~7 Initial Count/Cap */
759 iowrite16(NPCM7XX_FAN_TCNT,
760 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
761 iowrite16(NPCM7XX_FAN_TCNT,
762 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
764 /* set FAN0~7 compare (equal to count) */
765 iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),
766 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
768 /* set FAN0~7 compare value */
769 iowrite16(NPCM7XX_FAN_TCPA,
770 NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
771 iowrite16(NPCM7XX_FAN_TCPB,
772 NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
774 /* set FAN0~7 fan input FANIN 0~15 */
775 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
776 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
777 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
778 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
780 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {
781 ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;
782 data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
783 data->fan_dev[ch].fan_pls_per_rev =
784 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;
785 data->fan_dev[ch].fan_cnt = 0;
789 apb_clk_freq = clk_get_rate(data->fan_clk);
791 /* Fan tach input clock = APB clock / prescalar, default is 255. */
792 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
796 npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
797 unsigned long *state)
799 struct npcm7xx_cooling_device *cdev = tcdev->devdata;
801 *state = cdev->max_state;
807 npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
808 unsigned long *state)
810 struct npcm7xx_cooling_device *cdev = tcdev->devdata;
812 *state = cdev->cur_state;
818 npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
821 struct npcm7xx_cooling_device *cdev = tcdev->devdata;
824 if (state > cdev->max_state)
827 cdev->cur_state = state;
828 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
829 cdev->cooling_levels[cdev->cur_state]);
834 static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {
835 .get_max_state = npcm7xx_pwm_cz_get_max_state,
836 .get_cur_state = npcm7xx_pwm_cz_get_cur_state,
837 .set_cur_state = npcm7xx_pwm_cz_set_cur_state,
840 static int npcm7xx_create_pwm_cooling(struct device *dev,
841 struct device_node *child,
842 struct npcm7xx_pwm_fan_data *data,
843 u32 pwm_port, u8 num_levels)
846 struct npcm7xx_cooling_device *cdev;
848 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
852 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
853 if (!cdev->cooling_levels)
856 cdev->max_state = num_levels - 1;
857 ret = of_property_read_u8_array(child, "cooling-levels",
858 cdev->cooling_levels,
861 dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
864 snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,
867 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
868 cdev->name, cdev, &npcm7xx_pwm_cool_ops);
869 if (IS_ERR(cdev->tcdev))
870 return PTR_ERR(cdev->tcdev);
873 cdev->pwm_port = pwm_port;
875 data->cdev[pwm_port] = cdev;
880 static int npcm7xx_en_pwm_fan(struct device *dev,
881 struct device_node *child,
882 struct npcm7xx_pwm_fan_data *data)
889 ret = of_property_read_u32(child, "reg", &pwm_port);
893 data->pwm_present[pwm_port] = true;
894 ret = npcm7xx_pwm_config_set(data, pwm_port,
895 NPCM7XX_PWM_CMR_DEFAULT_NUM);
899 ret = of_property_count_u8_elems(child, "cooling-levels");
901 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
907 fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");
911 fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);
915 ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);
919 for (ch = 0; ch < fan_cnt; ch++) {
921 data->fan_present[index] = true;
922 data->fan_dev[index].fan_st_flg = FAN_INIT;
928 static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)
930 struct device *dev = &pdev->dev;
931 struct device_node *np, *child;
932 struct npcm7xx_pwm_fan_data *data;
933 struct resource *res;
934 struct device *hwmon;
942 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
946 data->info = device_get_match_data(dev);
950 data->pwm_modules = data->info->pwm_max_channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE;
952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
954 dev_err(dev, "pwm resource not found\n");
958 data->pwm_base = devm_ioremap_resource(dev, res);
959 dev_dbg(dev, "pwm base resource is %pR\n", res);
960 if (IS_ERR(data->pwm_base))
961 return PTR_ERR(data->pwm_base);
963 data->pwm_clk = devm_clk_get(dev, "pwm");
964 if (IS_ERR(data->pwm_clk)) {
965 dev_err(dev, "couldn't get pwm clock\n");
966 return PTR_ERR(data->pwm_clk);
969 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");
971 dev_err(dev, "fan resource not found\n");
975 data->fan_base = devm_ioremap_resource(dev, res);
976 dev_dbg(dev, "fan base resource is %pR\n", res);
977 if (IS_ERR(data->fan_base))
978 return PTR_ERR(data->fan_base);
980 data->fan_clk = devm_clk_get(dev, "fan");
981 if (IS_ERR(data->fan_clk)) {
982 dev_err(dev, "couldn't get fan clock\n");
983 return PTR_ERR(data->fan_clk);
986 output_freq = npcm7xx_pwm_init(data);
987 npcm7xx_fan_init(data);
989 for (cnt = 0; cnt < data->pwm_modules; cnt++)
990 mutex_init(&data->pwm_lock[cnt]);
992 for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {
993 spin_lock_init(&data->fan_lock[i]);
995 data->fan_irq[i] = platform_get_irq(pdev, i);
996 if (data->fan_irq[i] < 0)
997 return data->fan_irq[i];
999 sprintf(name, "NPCM7XX-FAN-MD%d", i);
1000 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
1001 0, name, (void *)data);
1003 dev_err(dev, "register IRQ fan%d failed\n", i);
1008 for_each_child_of_node(np, child) {
1009 ret = npcm7xx_en_pwm_fan(dev, child, data);
1011 dev_err(dev, "enable pwm and fan failed\n");
1017 hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",
1018 data, &npcm7xx_chip_info,
1020 if (IS_ERR(hwmon)) {
1021 dev_err(dev, "unable to register hwmon device\n");
1022 return PTR_ERR(hwmon);
1025 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {
1026 if (data->fan_present[i]) {
1027 /* fan timer initialization */
1028 data->fan_timer.expires = jiffies +
1029 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
1030 timer_setup(&data->fan_timer,
1031 npcm7xx_fan_polling, 0);
1032 add_timer(&data->fan_timer);
1037 pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",
1038 output_freq, data->input_clk_freq);
1043 static const struct of_device_id of_pwm_fan_match_table[] = {
1044 { .compatible = "nuvoton,npcm750-pwm-fan", .data = &npxm7xx_hwmon_info},
1045 { .compatible = "nuvoton,npcm845-pwm-fan", .data = &npxm8xx_hwmon_info},
1048 MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);
1050 static struct platform_driver npcm7xx_pwm_fan_driver = {
1051 .probe = npcm7xx_pwm_fan_probe,
1053 .name = "npcm7xx_pwm_fan",
1054 .of_match_table = of_pwm_fan_match_table,
1058 module_platform_driver(npcm7xx_pwm_fan_driver);
1060 MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");
1061 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
1062 MODULE_LICENSE("GPL v2");