drivers/hwmon/aspeed-pwm-tacho.c

   1 /*
   2  * Copyright (c) 2016 Google, Inc
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 or later as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/errno.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/delay.h>
  13 #include <linux/hwmon.h>
  14 #include <linux/hwmon-sysfs.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/sysfs.h>
  22 #include <linux/regmap.h>
  23 #include <linux/thermal.h>
  24
  25 /* ASPEED PWM & FAN Tach Register Definition */
  26 #define ASPEED_PTCR_CTRL                0x00
  27 #define ASPEED_PTCR_CLK_CTRL            0x04
  28 #define ASPEED_PTCR_DUTY0_CTRL          0x08
  29 #define ASPEED_PTCR_DUTY1_CTRL          0x0c
  30 #define ASPEED_PTCR_TYPEM_CTRL          0x10
  31 #define ASPEED_PTCR_TYPEM_CTRL1         0x14
  32 #define ASPEED_PTCR_TYPEN_CTRL          0x18
  33 #define ASPEED_PTCR_TYPEN_CTRL1         0x1c
  34 #define ASPEED_PTCR_TACH_SOURCE         0x20
  35 #define ASPEED_PTCR_TRIGGER             0x28
  36 #define ASPEED_PTCR_RESULT              0x2c
  37 #define ASPEED_PTCR_INTR_CTRL           0x30
  38 #define ASPEED_PTCR_INTR_STS            0x34
  39 #define ASPEED_PTCR_TYPEM_LIMIT         0x38
  40 #define ASPEED_PTCR_TYPEN_LIMIT         0x3C
  41 #define ASPEED_PTCR_CTRL_EXT            0x40
  42 #define ASPEED_PTCR_CLK_CTRL_EXT        0x44
  43 #define ASPEED_PTCR_DUTY2_CTRL          0x48
  44 #define ASPEED_PTCR_DUTY3_CTRL          0x4c
  45 #define ASPEED_PTCR_TYPEO_CTRL          0x50
  46 #define ASPEED_PTCR_TYPEO_CTRL1         0x54
  47 #define ASPEED_PTCR_TACH_SOURCE_EXT     0x60
  48 #define ASPEED_PTCR_TYPEO_LIMIT         0x78
  49
  50 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
  51 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1    15
  52 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2    6
  53 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK     (BIT(7) | BIT(15))
  54
  55 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1    14
  56 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2    5
  57 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK     (BIT(6) | BIT(14))
  58
  59 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1    13
  60 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2    4
  61 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK     (BIT(5) | BIT(13))
  62
  63 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1    12
  64 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2    3
  65 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK     (BIT(4) | BIT(12))
  66
  67 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x)  BIT(16 + (x))
  68
  69 #define ASPEED_PTCR_CTRL_PWMD_EN        BIT(11)
  70 #define ASPEED_PTCR_CTRL_PWMC_EN        BIT(10)
  71 #define ASPEED_PTCR_CTRL_PWMB_EN        BIT(9)
  72 #define ASPEED_PTCR_CTRL_PWMA_EN        BIT(8)
  73
  74 #define ASPEED_PTCR_CTRL_CLK_SRC        BIT(1)
  75 #define ASPEED_PTCR_CTRL_CLK_EN         BIT(0)
  76
  77 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
  78 /* TYPE N */
  79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK         GENMASK(31, 16)
  80 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT         24
  81 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H            20
  82 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L            16
  83 /* TYPE M */
  84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK         GENMASK(15, 0)
  85 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT         8
  86 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H            4
  87 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L            0
  88
  89 /*
  90  * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
  91  * 0/1/2/3 register
  92  */
  93 #define DUTY_CTRL_PWM2_FALL_POINT       24
  94 #define DUTY_CTRL_PWM2_RISE_POINT       16
  95 #define DUTY_CTRL_PWM2_RISE_FALL_MASK   GENMASK(31, 16)
  96 #define DUTY_CTRL_PWM1_FALL_POINT       8
  97 #define DUTY_CTRL_PWM1_RISE_POINT       0
  98 #define DUTY_CTRL_PWM1_RISE_FALL_MASK   GENMASK(15, 0)
  99
 100 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
 101 #define TYPE_CTRL_FAN_MASK              (GENMASK(5, 1) | GENMASK(31, 16))
 102 #define TYPE_CTRL_FAN1_MASK             GENMASK(31, 0)
 103 #define TYPE_CTRL_FAN_PERIOD            16
 104 #define TYPE_CTRL_FAN_MODE              4
 105 #define TYPE_CTRL_FAN_DIVISION          1
 106 #define TYPE_CTRL_FAN_TYPE_EN           1
 107
 108 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
 109 /* bit [0,1] at 0x20, bit [2] at 0x60 */
 110 #define TACH_PWM_SOURCE_BIT01(x)        ((x) * 2)
 111 #define TACH_PWM_SOURCE_BIT2(x)         ((x) * 2)
 112 #define TACH_PWM_SOURCE_MASK_BIT01(x)   (0x3 << ((x) * 2))
 113 #define TACH_PWM_SOURCE_MASK_BIT2(x)    BIT((x) * 2)
 114
 115 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
 116 #define RESULT_STATUS_MASK              BIT(31)
 117 #define RESULT_VALUE_MASK               0xfffff
 118
 119 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
 120 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1    15
 121 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2    6
 122 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK     (BIT(7) | BIT(15))
 123
 124 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1    14
 125 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2    5
 126 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK     (BIT(6) | BIT(14))
 127
 128 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1    13
 129 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2    4
 130 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK     (BIT(5) | BIT(13))
 131
 132 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1    12
 133 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2    3
 134 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK     (BIT(4) | BIT(12))
 135
 136 #define ASPEED_PTCR_CTRL_PWMH_EN        BIT(11)
 137 #define ASPEED_PTCR_CTRL_PWMG_EN        BIT(10)
 138 #define ASPEED_PTCR_CTRL_PWMF_EN        BIT(9)
 139 #define ASPEED_PTCR_CTRL_PWME_EN        BIT(8)
 140
 141 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
 142 /* TYPE O */
 143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK         GENMASK(15, 0)
 144 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT         8
 145 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H            4
 146 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L            0
 147
 148 #define PWM_MAX 255
 149
 150 #define BOTH_EDGES 0x02 /* 10b */
 151
 152 #define M_PWM_DIV_H 0x00
 153 #define M_PWM_DIV_L 0x05
 154 #define M_PWM_PERIOD 0x5F
 155 #define M_TACH_CLK_DIV 0x00
 156 /*
 157  * 5:4 Type N fan tach mode selection bit:
 158  * 00: falling
 159  * 01: rising
 160  * 10: both
 161  * 11: reserved.
 162  */
 163 #define M_TACH_MODE 0x02 /* 10b */
 164 #define M_TACH_UNIT 0x00c0
 165 #define INIT_FAN_CTRL 0xFF
 166
 167 /* How long we sleep in us while waiting for an RPM result. */
 168 #define ASPEED_RPM_STATUS_SLEEP_USEC    500
 169
 170 #define MAX_CDEV_NAME_LEN 16
 171
 172 struct aspeed_cooling_device {
 173         char name[16];
 174         struct aspeed_pwm_tacho_data *priv;
 175         struct thermal_cooling_device *tcdev;
 176         int pwm_port;
 177         u8 *cooling_levels;
 178         u8 max_state;
 179         u8 cur_state;
 180 };
 181
 182 struct aspeed_pwm_tacho_data {
 183         struct regmap *regmap;
 184         unsigned long clk_freq;
 185         bool pwm_present[8];
 186         bool fan_tach_present[16];
 187         u8 type_pwm_clock_unit[3];
 188         u8 type_pwm_clock_division_h[3];
 189         u8 type_pwm_clock_division_l[3];
 190         u8 type_fan_tach_clock_division[3];
 191         u8 type_fan_tach_mode[3];
 192         u16 type_fan_tach_unit[3];
 193         u8 pwm_port_type[8];
 194         u8 pwm_port_fan_ctrl[8];
 195         u8 fan_tach_ch_source[16];
 196         struct aspeed_cooling_device *cdev[8];
 197         const struct attribute_group *groups[3];
 198 };
 199
 200 enum type { TYPEM, TYPEN, TYPEO };
 201
 202 struct type_params {
 203         u32 l_value;
 204         u32 h_value;
 205         u32 unit_value;
 206         u32 clk_ctrl_mask;
 207         u32 clk_ctrl_reg;
 208         u32 ctrl_reg;
 209         u32 ctrl_reg1;
 210 };
 211
 212 static const struct type_params type_params[] = {
 213         [TYPEM] = {
 214                 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
 215                 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
 216                 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
 217                 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
 218                 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
 219                 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
 220                 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
 221         },
 222         [TYPEN] = {
 223                 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
 224                 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
 225                 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
 226                 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
 227                 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
 228                 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
 229                 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
 230         },
 231         [TYPEO] = {
 232                 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
 233                 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
 234                 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
 235                 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
 236                 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
 237                 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
 238                 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
 239         }
 240 };
 241
 242 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
 243
 244 struct pwm_port_params {
 245         u32 pwm_en;
 246         u32 ctrl_reg;
 247         u32 type_part1;
 248         u32 type_part2;
 249         u32 type_mask;
 250         u32 duty_ctrl_rise_point;
 251         u32 duty_ctrl_fall_point;
 252         u32 duty_ctrl_reg;
 253         u32 duty_ctrl_rise_fall_mask;
 254 };
 255
 256 static const struct pwm_port_params pwm_port_params[] = {
 257         [PWMA] = {
 258                 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
 259                 .ctrl_reg = ASPEED_PTCR_CTRL,
 260                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
 261                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
 262                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
 263                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 264                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 265                 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
 266                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 267         },
 268         [PWMB] = {
 269                 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
 270                 .ctrl_reg = ASPEED_PTCR_CTRL,
 271                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
 272                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
 273                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
 274                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 275                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 276                 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
 277                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 278         },
 279         [PWMC] = {
 280                 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
 281                 .ctrl_reg = ASPEED_PTCR_CTRL,
 282                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
 283                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
 284                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
 285                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 286                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 287                 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
 288                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 289         },
 290         [PWMD] = {
 291                 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
 292                 .ctrl_reg = ASPEED_PTCR_CTRL,
 293                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
 294                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
 295                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
 296                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 297                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 298                 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
 299                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 300         },
 301         [PWME] = {
 302                 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
 303                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 304                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
 305                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
 306                 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
 307                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 308                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 309                 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
 310                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 311         },
 312         [PWMF] = {
 313                 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
 314                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 315                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
 316                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
 317                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
 318                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 319                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 320                 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
 321                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 322         },
 323         [PWMG] = {
 324                 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
 325                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 326                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
 327                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
 328                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
 329                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 330                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 331                 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
 332                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 333         },
 334         [PWMH] = {
 335                 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
 336                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 337                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
 338                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
 339                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
 340                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 341                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 342                 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
 343                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 344         }
 345 };
 346
 347 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
 348                                              unsigned int val)
 349 {
 350         void __iomem *regs = (void __iomem *)context;
 351
 352         writel(val, regs + reg);
 353         return 0;
 354 }
 355
 356 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
 357                                             unsigned int *val)
 358 {
 359         void __iomem *regs = (void __iomem *)context;
 360
 361         *val = readl(regs + reg);
 362         return 0;
 363 }
 364
 365 static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
 366         .reg_bits = 32,
 367         .val_bits = 32,
 368         .reg_stride = 4,
 369         .max_register = ASPEED_PTCR_TYPEO_LIMIT,
 370         .reg_write = regmap_aspeed_pwm_tacho_reg_write,
 371         .reg_read = regmap_aspeed_pwm_tacho_reg_read,
 372         .fast_io = true,
 373 };
 374
 375 static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
 376 {
 377         regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 378                            ASPEED_PTCR_CTRL_CLK_EN,
 379                            val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
 380 }
 381
 382 static void aspeed_set_clock_source(struct regmap *regmap, int val)
 383 {
 384         regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 385                            ASPEED_PTCR_CTRL_CLK_SRC,
 386                            val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
 387 }
 388
 389 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
 390                                         u8 div_high, u8 div_low, u8 unit)
 391 {
 392         u32 reg_value = ((div_high << type_params[type].h_value) |
 393                          (div_low << type_params[type].l_value) |
 394                          (unit << type_params[type].unit_value));
 395
 396         regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
 397                            type_params[type].clk_ctrl_mask, reg_value);
 398 }
 399
 400 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
 401                                        bool enable)
 402 {
 403         regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
 404                            pwm_port_params[pwm_port].pwm_en,
 405                            enable ? pwm_port_params[pwm_port].pwm_en : 0);
 406 }
 407
 408 static void aspeed_set_pwm_port_type(struct regmap *regmap,
 409                                      u8 pwm_port, u8 type)
 410 {
 411         u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
 412
 413         reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
 414
 415         regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
 416                            pwm_port_params[pwm_port].type_mask, reg_value);
 417 }
 418
 419 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
 420                                                     u8 pwm_port, u8 rising,
 421                                                     u8 falling)
 422 {
 423         u32 reg_value = (rising <<
 424                          pwm_port_params[pwm_port].duty_ctrl_rise_point);
 425         reg_value |= (falling <<
 426                       pwm_port_params[pwm_port].duty_ctrl_fall_point);
 427
 428         regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
 429                            pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
 430                            reg_value);
 431 }
 432
 433 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
 434                                          bool enable)
 435 {
 436         regmap_update_bits(regmap, type_params[type].ctrl_reg,
 437                            TYPE_CTRL_FAN_TYPE_EN,
 438                            enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
 439 }
 440
 441 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
 442                                          u8 mode, u16 unit, u8 division)
 443 {
 444         u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
 445                          (unit << TYPE_CTRL_FAN_PERIOD) |
 446                          (division << TYPE_CTRL_FAN_DIVISION));
 447
 448         regmap_update_bits(regmap, type_params[type].ctrl_reg,
 449                            TYPE_CTRL_FAN_MASK, reg_value);
 450         regmap_update_bits(regmap, type_params[type].ctrl_reg1,
 451                            TYPE_CTRL_FAN1_MASK, unit << 16);
 452 }
 453
 454 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
 455                                           bool enable)
 456 {
 457         regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 458                            ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
 459                            enable ?
 460                            ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
 461 }
 462
 463 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
 464                                           u8 fan_tach_ch_source)
 465 {
 466         u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
 467                           TACH_PWM_SOURCE_BIT01(fan_tach_ch));
 468         u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
 469                           TACH_PWM_SOURCE_BIT2(fan_tach_ch));
 470
 471         regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
 472                            TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
 473                            reg_value1);
 474
 475         regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
 476                            TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
 477                            reg_value2);
 478 }
 479
 480 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
 481                                          u8 index, u8 fan_ctrl)
 482 {
 483         u16 period, dc_time_on;
 484
 485         period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
 486         period += 1;
 487         dc_time_on = (fan_ctrl * period) / PWM_MAX;
 488
 489         if (dc_time_on == 0) {
 490                 aspeed_set_pwm_port_enable(priv->regmap, index, false);
 491         } else {
 492                 if (dc_time_on == period)
 493                         dc_time_on = 0;
 494
 495                 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
 496                                                         dc_time_on);
 497                 aspeed_set_pwm_port_enable(priv->regmap, index, true);
 498         }
 499 }
 500
 501 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
 502                                                  *priv, u8 type)
 503 {
 504         u32 clk;
 505         u16 tacho_unit;
 506         u8 clk_unit, div_h, div_l, tacho_div;
 507
 508         clk = priv->clk_freq;
 509         clk_unit = priv->type_pwm_clock_unit[type];
 510         div_h = priv->type_pwm_clock_division_h[type];
 511         div_h = 0x1 << div_h;
 512         div_l = priv->type_pwm_clock_division_l[type];
 513         if (div_l == 0)
 514                 div_l = 1;
 515         else
 516                 div_l = div_l * 2;
 517
 518         tacho_unit = priv->type_fan_tach_unit[type];
 519         tacho_div = priv->type_fan_tach_clock_division[type];
 520
 521         tacho_div = 0x4 << (tacho_div * 2);
 522         return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
 523 }
 524
 525 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
 526                                       u8 fan_tach_ch)
 527 {
 528         u32 raw_data, tach_div, clk_source, msec, usec, val;
 529         u8 fan_tach_ch_source, type, mode, both;
 530         int ret;
 531
 532         regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
 533         regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
 534
 535         fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
 536         type = priv->pwm_port_type[fan_tach_ch_source];
 537
 538         msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
 539         usec = msec * 1000;
 540
 541         ret = regmap_read_poll_timeout(
 542                 priv->regmap,
 543                 ASPEED_PTCR_RESULT,
 544                 val,
 545                 (val & RESULT_STATUS_MASK),
 546                 ASPEED_RPM_STATUS_SLEEP_USEC,
 547                 usec);
 548
 549         /* return -ETIMEDOUT if we didn't get an answer. */
 550         if (ret)
 551                 return ret;
 552
 553         raw_data = val & RESULT_VALUE_MASK;
 554         tach_div = priv->type_fan_tach_clock_division[type];
 555         /*
 556          * We need the mode to determine if the raw_data is double (from
 557          * counting both edges).
 558          */
 559         mode = priv->type_fan_tach_mode[type];
 560         both = (mode & BOTH_EDGES) ? 1 : 0;
 561
 562         tach_div = (0x4 << both) << (tach_div * 2);
 563         clk_source = priv->clk_freq;
 564
 565         if (raw_data == 0)
 566                 return 0;
 567
 568         return (clk_source * 60) / (2 * raw_data * tach_div);
 569 }
 570
 571 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
 572                        const char *buf, size_t count)
 573 {
 574         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 575         int index = sensor_attr->index;
 576         int ret;
 577         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 578         long fan_ctrl;
 579
 580         ret = kstrtol(buf, 10, &fan_ctrl);
 581         if (ret != 0)
 582                 return ret;
 583
 584         if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
 585                 return -EINVAL;
 586
 587         if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
 588                 return count;
 589
 590         priv->pwm_port_fan_ctrl[index] = fan_ctrl;
 591         aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
 592
 593         return count;
 594 }
 595
 596 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
 597                         char *buf)
 598 {
 599         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 600         int index = sensor_attr->index;
 601         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 602
 603         return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
 604 }
 605
 606 static ssize_t show_rpm(struct device *dev, struct device_attribute *attr,
 607                         char *buf)
 608 {
 609         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 610         int index = sensor_attr->index;
 611         int rpm;
 612         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 613
 614         rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
 615         if (rpm < 0)
 616                 return rpm;
 617
 618         return sprintf(buf, "%d\n", rpm);
 619 }
 620
 621 static umode_t pwm_is_visible(struct kobject *kobj,
 622                               struct attribute *a, int index)
 623 {
 624         struct device *dev = container_of(kobj, struct device, kobj);
 625         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 626
 627         if (!priv->pwm_present[index])
 628                 return 0;
 629         return a->mode;
 630 }
 631
 632 static umode_t fan_dev_is_visible(struct kobject *kobj,
 633                                   struct attribute *a, int index)
 634 {
 635         struct device *dev = container_of(kobj, struct device, kobj);
 636         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 637
 638         if (!priv->fan_tach_present[index])
 639                 return 0;
 640         return a->mode;
 641 }
 642
 643 static SENSOR_DEVICE_ATTR(pwm1, 0644,
 644                         show_pwm, set_pwm, 0);
 645 static SENSOR_DEVICE_ATTR(pwm2, 0644,
 646                         show_pwm, set_pwm, 1);
 647 static SENSOR_DEVICE_ATTR(pwm3, 0644,
 648                         show_pwm, set_pwm, 2);
 649 static SENSOR_DEVICE_ATTR(pwm4, 0644,
 650                         show_pwm, set_pwm, 3);
 651 static SENSOR_DEVICE_ATTR(pwm5, 0644,
 652                         show_pwm, set_pwm, 4);
 653 static SENSOR_DEVICE_ATTR(pwm6, 0644,
 654                         show_pwm, set_pwm, 5);
 655 static SENSOR_DEVICE_ATTR(pwm7, 0644,
 656                         show_pwm, set_pwm, 6);
 657 static SENSOR_DEVICE_ATTR(pwm8, 0644,
 658                         show_pwm, set_pwm, 7);
 659 static struct attribute *pwm_dev_attrs[] = {
 660         &sensor_dev_attr_pwm1.dev_attr.attr,
 661         &sensor_dev_attr_pwm2.dev_attr.attr,
 662         &sensor_dev_attr_pwm3.dev_attr.attr,
 663         &sensor_dev_attr_pwm4.dev_attr.attr,
 664         &sensor_dev_attr_pwm5.dev_attr.attr,
 665         &sensor_dev_attr_pwm6.dev_attr.attr,
 666         &sensor_dev_attr_pwm7.dev_attr.attr,
 667         &sensor_dev_attr_pwm8.dev_attr.attr,
 668         NULL,
 669 };
 670
 671 static const struct attribute_group pwm_dev_group = {
 672         .attrs = pwm_dev_attrs,
 673         .is_visible = pwm_is_visible,
 674 };
 675
 676 static SENSOR_DEVICE_ATTR(fan1_input, 0444,
 677                 show_rpm, NULL, 0);
 678 static SENSOR_DEVICE_ATTR(fan2_input, 0444,
 679                 show_rpm, NULL, 1);
 680 static SENSOR_DEVICE_ATTR(fan3_input, 0444,
 681                 show_rpm, NULL, 2);
 682 static SENSOR_DEVICE_ATTR(fan4_input, 0444,
 683                 show_rpm, NULL, 3);
 684 static SENSOR_DEVICE_ATTR(fan5_input, 0444,
 685                 show_rpm, NULL, 4);
 686 static SENSOR_DEVICE_ATTR(fan6_input, 0444,
 687                 show_rpm, NULL, 5);
 688 static SENSOR_DEVICE_ATTR(fan7_input, 0444,
 689                 show_rpm, NULL, 6);
 690 static SENSOR_DEVICE_ATTR(fan8_input, 0444,
 691                 show_rpm, NULL, 7);
 692 static SENSOR_DEVICE_ATTR(fan9_input, 0444,
 693                 show_rpm, NULL, 8);
 694 static SENSOR_DEVICE_ATTR(fan10_input, 0444,
 695                 show_rpm, NULL, 9);
 696 static SENSOR_DEVICE_ATTR(fan11_input, 0444,
 697                 show_rpm, NULL, 10);
 698 static SENSOR_DEVICE_ATTR(fan12_input, 0444,
 699                 show_rpm, NULL, 11);
 700 static SENSOR_DEVICE_ATTR(fan13_input, 0444,
 701                 show_rpm, NULL, 12);
 702 static SENSOR_DEVICE_ATTR(fan14_input, 0444,
 703                 show_rpm, NULL, 13);
 704 static SENSOR_DEVICE_ATTR(fan15_input, 0444,
 705                 show_rpm, NULL, 14);
 706 static SENSOR_DEVICE_ATTR(fan16_input, 0444,
 707                 show_rpm, NULL, 15);
 708 static struct attribute *fan_dev_attrs[] = {
 709         &sensor_dev_attr_fan1_input.dev_attr.attr,
 710         &sensor_dev_attr_fan2_input.dev_attr.attr,
 711         &sensor_dev_attr_fan3_input.dev_attr.attr,
 712         &sensor_dev_attr_fan4_input.dev_attr.attr,
 713         &sensor_dev_attr_fan5_input.dev_attr.attr,
 714         &sensor_dev_attr_fan6_input.dev_attr.attr,
 715         &sensor_dev_attr_fan7_input.dev_attr.attr,
 716         &sensor_dev_attr_fan8_input.dev_attr.attr,
 717         &sensor_dev_attr_fan9_input.dev_attr.attr,
 718         &sensor_dev_attr_fan10_input.dev_attr.attr,
 719         &sensor_dev_attr_fan11_input.dev_attr.attr,
 720         &sensor_dev_attr_fan12_input.dev_attr.attr,
 721         &sensor_dev_attr_fan13_input.dev_attr.attr,
 722         &sensor_dev_attr_fan14_input.dev_attr.attr,
 723         &sensor_dev_attr_fan15_input.dev_attr.attr,
 724         &sensor_dev_attr_fan16_input.dev_attr.attr,
 725         NULL
 726 };
 727
 728 static const struct attribute_group fan_dev_group = {
 729         .attrs = fan_dev_attrs,
 730         .is_visible = fan_dev_is_visible,
 731 };
 732
 733 /*
 734  * The clock type is type M :
 735  * The PWM frequency = 24MHz / (type M clock division L bit *
 736  * type M clock division H bit * (type M PWM period bit + 1))
 737  */
 738 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
 739 {
 740         priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
 741         priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
 742         priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
 743         aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
 744                                     M_PWM_DIV_L, M_PWM_PERIOD);
 745         aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
 746         priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
 747         priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
 748         priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
 749         aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
 750                                      M_TACH_UNIT, M_TACH_CLK_DIV);
 751 }
 752
 753 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
 754                                    u8 pwm_port)
 755 {
 756         aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
 757         priv->pwm_present[pwm_port] = true;
 758
 759         priv->pwm_port_type[pwm_port] = TYPEM;
 760         aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
 761
 762         priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
 763         aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
 764 }
 765
 766 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
 767                                            u8 *fan_tach_ch,
 768                                            int count,
 769                                            u8 pwm_source)
 770 {
 771         u8 val, index;
 772
 773         for (val = 0; val < count; val++) {
 774                 index = fan_tach_ch[val];
 775                 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
 776                 priv->fan_tach_present[index] = true;
 777                 priv->fan_tach_ch_source[index] = pwm_source;
 778                 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
 779         }
 780 }
 781
 782 static int
 783 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
 784                             unsigned long *state)
 785 {
 786         struct aspeed_cooling_device *cdev = tcdev->devdata;
 787
 788         *state = cdev->max_state;
 789
 790         return 0;
 791 }
 792
 793 static int
 794 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
 795                             unsigned long *state)
 796 {
 797         struct aspeed_cooling_device *cdev = tcdev->devdata;
 798
 799         *state = cdev->cur_state;
 800
 801         return 0;
 802 }
 803
 804 static int
 805 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
 806                             unsigned long state)
 807 {
 808         struct aspeed_cooling_device *cdev = tcdev->devdata;
 809
 810         if (state > cdev->max_state)
 811                 return -EINVAL;
 812
 813         cdev->cur_state = state;
 814         cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
 815                                         cdev->cooling_levels[cdev->cur_state];
 816         aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
 817                                      cdev->cooling_levels[cdev->cur_state]);
 818
 819         return 0;
 820 }
 821
 822 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
 823         .get_max_state = aspeed_pwm_cz_get_max_state,
 824         .get_cur_state = aspeed_pwm_cz_get_cur_state,
 825         .set_cur_state = aspeed_pwm_cz_set_cur_state,
 826 };
 827
 828 static int aspeed_create_pwm_cooling(struct device *dev,
 829                                      struct device_node *child,
 830                                      struct aspeed_pwm_tacho_data *priv,
 831                                      u32 pwm_port, u8 num_levels)
 832 {
 833         int ret;
 834         struct aspeed_cooling_device *cdev;
 835
 836         cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
 837
 838         if (!cdev)
 839                 return -ENOMEM;
 840
 841         cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
 842         if (!cdev->cooling_levels)
 843                 return -ENOMEM;
 844
 845         cdev->max_state = num_levels - 1;
 846         ret = of_property_read_u8_array(child, "cooling-levels",
 847                                         cdev->cooling_levels,
 848                                         num_levels);
 849         if (ret) {
 850                 dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
 851                 return ret;
 852         }
 853         snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%s%d", child->name, pwm_port);
 854
 855         cdev->tcdev = thermal_of_cooling_device_register(child,
 856                                                          cdev->name,
 857                                                          cdev,
 858                                                          &aspeed_pwm_cool_ops);
 859         if (IS_ERR(cdev->tcdev))
 860                 return PTR_ERR(cdev->tcdev);
 861
 862         cdev->priv = priv;
 863         cdev->pwm_port = pwm_port;
 864
 865         priv->cdev[pwm_port] = cdev;
 866
 867         return 0;
 868 }
 869
 870 static int aspeed_create_fan(struct device *dev,
 871                              struct device_node *child,
 872                              struct aspeed_pwm_tacho_data *priv)
 873 {
 874         u8 *fan_tach_ch;
 875         u32 pwm_port;
 876         int ret, count;
 877
 878         ret = of_property_read_u32(child, "reg", &pwm_port);
 879         if (ret)
 880                 return ret;
 881         if (pwm_port >= ARRAY_SIZE(pwm_port_params))
 882                 return -EINVAL;
 883         aspeed_create_pwm_port(priv, (u8)pwm_port);
 884
 885         ret = of_property_count_u8_elems(child, "cooling-levels");
 886
 887         if (ret > 0) {
 888                 ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
 889                                                 ret);
 890                 if (ret)
 891                         return ret;
 892         }
 893
 894         count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
 895         if (count < 1)
 896                 return -EINVAL;
 897         fan_tach_ch = devm_kzalloc(dev, sizeof(*fan_tach_ch) * count,
 898                                    GFP_KERNEL);
 899         if (!fan_tach_ch)
 900                 return -ENOMEM;
 901         ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
 902                                         fan_tach_ch, count);
 903         if (ret)
 904                 return ret;
 905         aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
 906
 907         return 0;
 908 }
 909
 910 static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
 911 {
 912         struct device *dev = &pdev->dev;
 913         struct device_node *np, *child;
 914         struct aspeed_pwm_tacho_data *priv;
 915         void __iomem *regs;
 916         struct resource *res;
 917         struct device *hwmon;
 918         struct clk *clk;
 919         int ret;
 920
 921         np = dev->of_node;
 922
 923         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 924         if (!res)
 925                 return -ENOENT;
 926         regs = devm_ioremap_resource(dev, res);
 927         if (IS_ERR(regs))
 928                 return PTR_ERR(regs);
 929         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 930         if (!priv)
 931                 return -ENOMEM;
 932         priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
 933                         &aspeed_pwm_tacho_regmap_config);
 934         if (IS_ERR(priv->regmap))
 935                 return PTR_ERR(priv->regmap);
 936         regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
 937         regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
 938
 939         clk = devm_clk_get(dev, NULL);
 940         if (IS_ERR(clk))
 941                 return -ENODEV;
 942         priv->clk_freq = clk_get_rate(clk);
 943         aspeed_set_clock_enable(priv->regmap, true);
 944         aspeed_set_clock_source(priv->regmap, 0);
 945
 946         aspeed_create_type(priv);
 947
 948         for_each_child_of_node(np, child) {
 949                 ret = aspeed_create_fan(dev, child, priv);
 950                 if (ret) {
 951                         of_node_put(child);
 952                         return ret;
 953                 }
 954         }
 955
 956         priv->groups[0] = &pwm_dev_group;
 957         priv->groups[1] = &fan_dev_group;
 958         priv->groups[2] = NULL;
 959         hwmon = devm_hwmon_device_register_with_groups(dev,
 960                                                        "aspeed_pwm_tacho",
 961                                                        priv, priv->groups);
 962         return PTR_ERR_OR_ZERO(hwmon);
 963 }
 964
 965 static const struct of_device_id of_pwm_tacho_match_table[] = {
 966         { .compatible = "aspeed,ast2400-pwm-tacho", },
 967         { .compatible = "aspeed,ast2500-pwm-tacho", },
 968         {},
 969 };
 970 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
 971
 972 static struct platform_driver aspeed_pwm_tacho_driver = {
 973         .probe          = aspeed_pwm_tacho_probe,
 974         .driver         = {
 975                 .name   = "aspeed_pwm_tacho",
 976                 .of_match_table = of_pwm_tacho_match_table,
 977         },
 978 };
 979
 980 module_platform_driver(aspeed_pwm_tacho_driver);
 981
 982 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
 983 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
 984 MODULE_LICENSE("GPL");