1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2016 Google, Inc
7 #include <linux/delay.h>
8 #include <linux/errno.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/hwmon.h>
11 #include <linux/hwmon-sysfs.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/sysfs.h>
20 #include <linux/thermal.h>
22 /* ASPEED PWM & FAN Tach Register Definition */
23 #define ASPEED_PTCR_CTRL 0x00
24 #define ASPEED_PTCR_CLK_CTRL 0x04
25 #define ASPEED_PTCR_DUTY0_CTRL 0x08
26 #define ASPEED_PTCR_DUTY1_CTRL 0x0c
27 #define ASPEED_PTCR_TYPEM_CTRL 0x10
28 #define ASPEED_PTCR_TYPEM_CTRL1 0x14
29 #define ASPEED_PTCR_TYPEN_CTRL 0x18
30 #define ASPEED_PTCR_TYPEN_CTRL1 0x1c
31 #define ASPEED_PTCR_TACH_SOURCE 0x20
32 #define ASPEED_PTCR_TRIGGER 0x28
33 #define ASPEED_PTCR_RESULT 0x2c
34 #define ASPEED_PTCR_INTR_CTRL 0x30
35 #define ASPEED_PTCR_INTR_STS 0x34
36 #define ASPEED_PTCR_TYPEM_LIMIT 0x38
37 #define ASPEED_PTCR_TYPEN_LIMIT 0x3C
38 #define ASPEED_PTCR_CTRL_EXT 0x40
39 #define ASPEED_PTCR_CLK_CTRL_EXT 0x44
40 #define ASPEED_PTCR_DUTY2_CTRL 0x48
41 #define ASPEED_PTCR_DUTY3_CTRL 0x4c
42 #define ASPEED_PTCR_TYPEO_CTRL 0x50
43 #define ASPEED_PTCR_TYPEO_CTRL1 0x54
44 #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60
45 #define ASPEED_PTCR_TYPEO_LIMIT 0x78
47 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
48 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15
49 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6
50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15))
52 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14
53 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5
54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14))
56 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13
57 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4
58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13))
60 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12
61 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3
62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12))
64 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x))
66 #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11)
67 #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10)
68 #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9)
69 #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8)
71 #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1)
72 #define ASPEED_PTCR_CTRL_CLK_EN BIT(0)
74 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
76 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16)
77 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24
78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20
79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16
81 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0)
82 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8
83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4
84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0
87 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
90 #define DUTY_CTRL_PWM2_FALL_POINT 24
91 #define DUTY_CTRL_PWM2_RISE_POINT 16
92 #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16)
93 #define DUTY_CTRL_PWM1_FALL_POINT 8
94 #define DUTY_CTRL_PWM1_RISE_POINT 0
95 #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0)
97 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
98 #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16))
99 #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0)
100 #define TYPE_CTRL_FAN_PERIOD 16
101 #define TYPE_CTRL_FAN_MODE 4
102 #define TYPE_CTRL_FAN_DIVISION 1
103 #define TYPE_CTRL_FAN_TYPE_EN 1
105 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
106 /* bit [0,1] at 0x20, bit [2] at 0x60 */
107 #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2)
108 #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2)
109 #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2))
110 #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2)
112 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
113 #define RESULT_STATUS_MASK BIT(31)
114 #define RESULT_VALUE_MASK 0xfffff
116 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
117 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15
118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6
119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15))
121 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14
122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5
123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14))
125 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13
126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4
127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13))
129 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12
130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3
131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12))
133 #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11)
134 #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10)
135 #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9)
136 #define ASPEED_PTCR_CTRL_PWME_EN BIT(8)
138 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
140 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0)
141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8
142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4
143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0
147 #define BOTH_EDGES 0x02 /* 10b */
149 #define M_PWM_DIV_H 0x00
150 #define M_PWM_DIV_L 0x05
151 #define M_PWM_PERIOD 0x5F
152 #define M_TACH_CLK_DIV 0x00
154 * 5:4 Type N fan tach mode selection bit:
160 #define M_TACH_MODE 0x02 /* 10b */
161 #define M_TACH_UNIT 0x0420
162 #define INIT_FAN_CTRL 0xFF
164 /* How long we sleep in us while waiting for an RPM result. */
165 #define ASPEED_RPM_STATUS_SLEEP_USEC 500
167 #define MAX_CDEV_NAME_LEN 16
169 struct aspeed_cooling_device {
171 struct aspeed_pwm_tacho_data *priv;
172 struct thermal_cooling_device *tcdev;
179 struct aspeed_pwm_tacho_data {
180 struct regmap *regmap;
181 struct reset_control *rst;
182 unsigned long clk_freq;
184 bool fan_tach_present[16];
185 u8 type_pwm_clock_unit[3];
186 u8 type_pwm_clock_division_h[3];
187 u8 type_pwm_clock_division_l[3];
188 u8 type_fan_tach_clock_division[3];
189 u8 type_fan_tach_mode[3];
190 u16 type_fan_tach_unit[3];
192 u8 pwm_port_fan_ctrl[8];
193 u8 fan_tach_ch_source[16];
194 struct aspeed_cooling_device *cdev[8];
195 const struct attribute_group *groups[3];
196 /* protects access to shared ASPEED_PTCR_RESULT */
197 struct mutex tach_lock;
200 enum type { TYPEM, TYPEN, TYPEO };
212 static const struct type_params type_params[] = {
214 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
215 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
216 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
217 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
218 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
219 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
220 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
223 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
224 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
225 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
226 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
227 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
228 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
229 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
232 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
233 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
234 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
235 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
236 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
237 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
238 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
242 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
244 struct pwm_port_params {
250 u32 duty_ctrl_rise_point;
251 u32 duty_ctrl_fall_point;
253 u32 duty_ctrl_rise_fall_mask;
256 static const struct pwm_port_params pwm_port_params[] = {
258 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
259 .ctrl_reg = ASPEED_PTCR_CTRL,
260 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
261 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
262 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
263 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
264 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
265 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
266 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
269 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
270 .ctrl_reg = ASPEED_PTCR_CTRL,
271 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
272 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
273 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
274 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
275 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
276 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
277 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
280 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
281 .ctrl_reg = ASPEED_PTCR_CTRL,
282 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
283 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
284 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
285 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
286 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
287 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
288 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
291 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
292 .ctrl_reg = ASPEED_PTCR_CTRL,
293 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
294 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
295 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
296 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
297 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
298 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
299 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
302 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
303 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
304 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
305 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
306 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
307 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
308 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
309 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
310 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
313 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
314 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
315 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
316 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
317 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
318 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
319 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
320 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
321 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
324 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
325 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
326 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
327 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
328 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
329 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
330 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
331 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
332 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
335 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
336 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
337 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
338 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
339 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
340 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
341 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
342 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
343 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
347 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
350 void __iomem *regs = (void __iomem *)context;
352 writel(val, regs + reg);
356 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
359 void __iomem *regs = (void __iomem *)context;
361 *val = readl(regs + reg);
365 static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
369 .max_register = ASPEED_PTCR_TYPEO_LIMIT,
370 .reg_write = regmap_aspeed_pwm_tacho_reg_write,
371 .reg_read = regmap_aspeed_pwm_tacho_reg_read,
375 static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
377 regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
378 ASPEED_PTCR_CTRL_CLK_EN,
379 val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
382 static void aspeed_set_clock_source(struct regmap *regmap, int val)
384 regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
385 ASPEED_PTCR_CTRL_CLK_SRC,
386 val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
389 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
390 u8 div_high, u8 div_low, u8 unit)
392 u32 reg_value = ((div_high << type_params[type].h_value) |
393 (div_low << type_params[type].l_value) |
394 (unit << type_params[type].unit_value));
396 regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
397 type_params[type].clk_ctrl_mask, reg_value);
400 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
403 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
404 pwm_port_params[pwm_port].pwm_en,
405 enable ? pwm_port_params[pwm_port].pwm_en : 0);
408 static void aspeed_set_pwm_port_type(struct regmap *regmap,
409 u8 pwm_port, u8 type)
411 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
413 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
415 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
416 pwm_port_params[pwm_port].type_mask, reg_value);
419 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
420 u8 pwm_port, u8 rising,
423 u32 reg_value = (rising <<
424 pwm_port_params[pwm_port].duty_ctrl_rise_point);
425 reg_value |= (falling <<
426 pwm_port_params[pwm_port].duty_ctrl_fall_point);
428 regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
429 pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
433 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
436 regmap_update_bits(regmap, type_params[type].ctrl_reg,
437 TYPE_CTRL_FAN_TYPE_EN,
438 enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
441 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
442 u8 mode, u16 unit, u8 division)
444 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
445 (unit << TYPE_CTRL_FAN_PERIOD) |
446 (division << TYPE_CTRL_FAN_DIVISION));
448 regmap_update_bits(regmap, type_params[type].ctrl_reg,
449 TYPE_CTRL_FAN_MASK, reg_value);
450 regmap_update_bits(regmap, type_params[type].ctrl_reg1,
451 TYPE_CTRL_FAN1_MASK, unit << 16);
454 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
457 regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
458 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
460 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
463 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
464 u8 fan_tach_ch_source)
466 u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
467 TACH_PWM_SOURCE_BIT01(fan_tach_ch));
468 u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
469 TACH_PWM_SOURCE_BIT2(fan_tach_ch));
471 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
472 TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
475 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
476 TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
480 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
481 u8 index, u8 fan_ctrl)
483 u16 period, dc_time_on;
485 period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
487 dc_time_on = (fan_ctrl * period) / PWM_MAX;
489 if (dc_time_on == 0) {
490 aspeed_set_pwm_port_enable(priv->regmap, index, false);
492 if (dc_time_on == period)
495 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
497 aspeed_set_pwm_port_enable(priv->regmap, index, true);
501 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
506 u8 clk_unit, div_h, div_l, tacho_div;
508 clk = priv->clk_freq;
509 clk_unit = priv->type_pwm_clock_unit[type];
510 div_h = priv->type_pwm_clock_division_h[type];
511 div_h = 0x1 << div_h;
512 div_l = priv->type_pwm_clock_division_l[type];
518 tacho_unit = priv->type_fan_tach_unit[type];
519 tacho_div = priv->type_fan_tach_clock_division[type];
521 tacho_div = 0x4 << (tacho_div * 2);
522 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
525 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
528 u32 raw_data, tach_div, clk_source, msec, usec, val;
529 u8 fan_tach_ch_source, type, mode, both;
532 mutex_lock(&priv->tach_lock);
534 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
535 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
537 fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
538 type = priv->pwm_port_type[fan_tach_ch_source];
540 msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
543 ret = regmap_read_poll_timeout(
547 (val & RESULT_STATUS_MASK),
548 ASPEED_RPM_STATUS_SLEEP_USEC,
551 mutex_unlock(&priv->tach_lock);
553 /* return -ETIMEDOUT if we didn't get an answer. */
557 raw_data = val & RESULT_VALUE_MASK;
558 tach_div = priv->type_fan_tach_clock_division[type];
560 * We need the mode to determine if the raw_data is double (from
561 * counting both edges).
563 mode = priv->type_fan_tach_mode[type];
564 both = (mode & BOTH_EDGES) ? 1 : 0;
566 tach_div = (0x4 << both) << (tach_div * 2);
567 clk_source = priv->clk_freq;
572 return (clk_source * 60) / (2 * raw_data * tach_div);
575 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
576 const char *buf, size_t count)
578 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
579 int index = sensor_attr->index;
581 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
584 ret = kstrtol(buf, 10, &fan_ctrl);
588 if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
591 if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
594 priv->pwm_port_fan_ctrl[index] = fan_ctrl;
595 aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
600 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
603 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
604 int index = sensor_attr->index;
605 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
607 return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
610 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr,
613 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
614 int index = sensor_attr->index;
616 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
618 rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
622 return sprintf(buf, "%d\n", rpm);
625 static umode_t pwm_is_visible(struct kobject *kobj,
626 struct attribute *a, int index)
628 struct device *dev = kobj_to_dev(kobj);
629 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
631 if (!priv->pwm_present[index])
636 static umode_t fan_dev_is_visible(struct kobject *kobj,
637 struct attribute *a, int index)
639 struct device *dev = kobj_to_dev(kobj);
640 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
642 if (!priv->fan_tach_present[index])
647 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
648 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
649 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
650 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
651 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4);
652 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5);
653 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6);
654 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7);
655 static struct attribute *pwm_dev_attrs[] = {
656 &sensor_dev_attr_pwm1.dev_attr.attr,
657 &sensor_dev_attr_pwm2.dev_attr.attr,
658 &sensor_dev_attr_pwm3.dev_attr.attr,
659 &sensor_dev_attr_pwm4.dev_attr.attr,
660 &sensor_dev_attr_pwm5.dev_attr.attr,
661 &sensor_dev_attr_pwm6.dev_attr.attr,
662 &sensor_dev_attr_pwm7.dev_attr.attr,
663 &sensor_dev_attr_pwm8.dev_attr.attr,
667 static const struct attribute_group pwm_dev_group = {
668 .attrs = pwm_dev_attrs,
669 .is_visible = pwm_is_visible,
672 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
673 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1);
674 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2);
675 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3);
676 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4);
677 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5);
678 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6);
679 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7);
680 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8);
681 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9);
682 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10);
683 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11);
684 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12);
685 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13);
686 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14);
687 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15);
688 static struct attribute *fan_dev_attrs[] = {
689 &sensor_dev_attr_fan1_input.dev_attr.attr,
690 &sensor_dev_attr_fan2_input.dev_attr.attr,
691 &sensor_dev_attr_fan3_input.dev_attr.attr,
692 &sensor_dev_attr_fan4_input.dev_attr.attr,
693 &sensor_dev_attr_fan5_input.dev_attr.attr,
694 &sensor_dev_attr_fan6_input.dev_attr.attr,
695 &sensor_dev_attr_fan7_input.dev_attr.attr,
696 &sensor_dev_attr_fan8_input.dev_attr.attr,
697 &sensor_dev_attr_fan9_input.dev_attr.attr,
698 &sensor_dev_attr_fan10_input.dev_attr.attr,
699 &sensor_dev_attr_fan11_input.dev_attr.attr,
700 &sensor_dev_attr_fan12_input.dev_attr.attr,
701 &sensor_dev_attr_fan13_input.dev_attr.attr,
702 &sensor_dev_attr_fan14_input.dev_attr.attr,
703 &sensor_dev_attr_fan15_input.dev_attr.attr,
704 &sensor_dev_attr_fan16_input.dev_attr.attr,
708 static const struct attribute_group fan_dev_group = {
709 .attrs = fan_dev_attrs,
710 .is_visible = fan_dev_is_visible,
714 * The clock type is type M :
715 * The PWM frequency = 24MHz / (type M clock division L bit *
716 * type M clock division H bit * (type M PWM period bit + 1))
718 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
720 priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
721 priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
722 priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
723 aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
724 M_PWM_DIV_L, M_PWM_PERIOD);
725 aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
726 priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
727 priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
728 priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
729 aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
730 M_TACH_UNIT, M_TACH_CLK_DIV);
733 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
736 aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
737 priv->pwm_present[pwm_port] = true;
739 priv->pwm_port_type[pwm_port] = TYPEM;
740 aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
742 priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
743 aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
746 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
753 for (val = 0; val < count; val++) {
754 index = fan_tach_ch[val];
755 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
756 priv->fan_tach_present[index] = true;
757 priv->fan_tach_ch_source[index] = pwm_source;
758 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
763 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
764 unsigned long *state)
766 struct aspeed_cooling_device *cdev = tcdev->devdata;
768 *state = cdev->max_state;
774 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
775 unsigned long *state)
777 struct aspeed_cooling_device *cdev = tcdev->devdata;
779 *state = cdev->cur_state;
785 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
788 struct aspeed_cooling_device *cdev = tcdev->devdata;
790 if (state > cdev->max_state)
793 cdev->cur_state = state;
794 cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
795 cdev->cooling_levels[cdev->cur_state];
796 aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
797 cdev->cooling_levels[cdev->cur_state]);
802 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
803 .get_max_state = aspeed_pwm_cz_get_max_state,
804 .get_cur_state = aspeed_pwm_cz_get_cur_state,
805 .set_cur_state = aspeed_pwm_cz_set_cur_state,
808 static int aspeed_create_pwm_cooling(struct device *dev,
809 struct device_node *child,
810 struct aspeed_pwm_tacho_data *priv,
811 u32 pwm_port, u8 num_levels)
814 struct aspeed_cooling_device *cdev;
816 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
821 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
822 if (!cdev->cooling_levels)
825 cdev->max_state = num_levels - 1;
826 ret = of_property_read_u8_array(child, "cooling-levels",
827 cdev->cooling_levels,
830 dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
833 snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
835 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
836 cdev->name, cdev, &aspeed_pwm_cool_ops);
837 if (IS_ERR(cdev->tcdev))
838 return PTR_ERR(cdev->tcdev);
841 cdev->pwm_port = pwm_port;
843 priv->cdev[pwm_port] = cdev;
848 static int aspeed_create_fan(struct device *dev,
849 struct device_node *child,
850 struct aspeed_pwm_tacho_data *priv)
856 ret = of_property_read_u32(child, "reg", &pwm_port);
859 if (pwm_port >= ARRAY_SIZE(pwm_port_params))
861 aspeed_create_pwm_port(priv, (u8)pwm_port);
863 ret = of_property_count_u8_elems(child, "cooling-levels");
866 ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
872 count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
875 fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch),
879 ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
883 aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
888 static void aspeed_pwm_tacho_remove(void *data)
890 struct aspeed_pwm_tacho_data *priv = data;
892 reset_control_assert(priv->rst);
895 static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
897 struct device *dev = &pdev->dev;
898 struct device_node *np, *child;
899 struct aspeed_pwm_tacho_data *priv;
901 struct device *hwmon;
906 regs = devm_platform_ioremap_resource(pdev, 0);
908 return PTR_ERR(regs);
909 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
912 mutex_init(&priv->tach_lock);
913 priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
914 &aspeed_pwm_tacho_regmap_config);
915 if (IS_ERR(priv->regmap))
916 return PTR_ERR(priv->regmap);
918 priv->rst = devm_reset_control_get_exclusive(dev, NULL);
919 if (IS_ERR(priv->rst)) {
921 "missing or invalid reset controller device tree entry");
922 return PTR_ERR(priv->rst);
924 reset_control_deassert(priv->rst);
926 ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv);
930 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
931 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
933 clk = devm_clk_get(dev, NULL);
936 priv->clk_freq = clk_get_rate(clk);
937 aspeed_set_clock_enable(priv->regmap, true);
938 aspeed_set_clock_source(priv->regmap, 0);
940 aspeed_create_type(priv);
942 for_each_child_of_node(np, child) {
943 ret = aspeed_create_fan(dev, child, priv);
950 priv->groups[0] = &pwm_dev_group;
951 priv->groups[1] = &fan_dev_group;
952 priv->groups[2] = NULL;
953 hwmon = devm_hwmon_device_register_with_groups(dev,
956 return PTR_ERR_OR_ZERO(hwmon);
959 static const struct of_device_id of_pwm_tacho_match_table[] = {
960 { .compatible = "aspeed,ast2400-pwm-tacho", },
961 { .compatible = "aspeed,ast2500-pwm-tacho", },
964 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
966 static struct platform_driver aspeed_pwm_tacho_driver = {
967 .probe = aspeed_pwm_tacho_probe,
969 .name = "aspeed_pwm_tacho",
970 .of_match_table = of_pwm_tacho_match_table,
974 module_platform_driver(aspeed_pwm_tacho_driver);
976 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
977 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
978 MODULE_LICENSE("GPL");