drivers/hwmon/aspeed-pwm-tacho.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2016 Google, Inc
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/errno.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/hwmon.h>
  11 #include <linux/hwmon-sysfs.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/reset.h>
  20 #include <linux/sysfs.h>
  21 #include <linux/thermal.h>
  22
  23 /* ASPEED PWM & FAN Tach Register Definition */
  24 #define ASPEED_PTCR_CTRL                0x00
  25 #define ASPEED_PTCR_CLK_CTRL            0x04
  26 #define ASPEED_PTCR_DUTY0_CTRL          0x08
  27 #define ASPEED_PTCR_DUTY1_CTRL          0x0c
  28 #define ASPEED_PTCR_TYPEM_CTRL          0x10
  29 #define ASPEED_PTCR_TYPEM_CTRL1         0x14
  30 #define ASPEED_PTCR_TYPEN_CTRL          0x18
  31 #define ASPEED_PTCR_TYPEN_CTRL1         0x1c
  32 #define ASPEED_PTCR_TACH_SOURCE         0x20
  33 #define ASPEED_PTCR_TRIGGER             0x28
  34 #define ASPEED_PTCR_RESULT              0x2c
  35 #define ASPEED_PTCR_INTR_CTRL           0x30
  36 #define ASPEED_PTCR_INTR_STS            0x34
  37 #define ASPEED_PTCR_TYPEM_LIMIT         0x38
  38 #define ASPEED_PTCR_TYPEN_LIMIT         0x3C
  39 #define ASPEED_PTCR_CTRL_EXT            0x40
  40 #define ASPEED_PTCR_CLK_CTRL_EXT        0x44
  41 #define ASPEED_PTCR_DUTY2_CTRL          0x48
  42 #define ASPEED_PTCR_DUTY3_CTRL          0x4c
  43 #define ASPEED_PTCR_TYPEO_CTRL          0x50
  44 #define ASPEED_PTCR_TYPEO_CTRL1         0x54
  45 #define ASPEED_PTCR_TACH_SOURCE_EXT     0x60
  46 #define ASPEED_PTCR_TYPEO_LIMIT         0x78
  47
  48 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
  49 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1    15
  50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2    6
  51 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK     (BIT(7) | BIT(15))
  52
  53 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1    14
  54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2    5
  55 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK     (BIT(6) | BIT(14))
  56
  57 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1    13
  58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2    4
  59 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK     (BIT(5) | BIT(13))
  60
  61 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1    12
  62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2    3
  63 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK     (BIT(4) | BIT(12))
  64
  65 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x)  BIT(16 + (x))
  66
  67 #define ASPEED_PTCR_CTRL_PWMD_EN        BIT(11)
  68 #define ASPEED_PTCR_CTRL_PWMC_EN        BIT(10)
  69 #define ASPEED_PTCR_CTRL_PWMB_EN        BIT(9)
  70 #define ASPEED_PTCR_CTRL_PWMA_EN        BIT(8)
  71
  72 #define ASPEED_PTCR_CTRL_CLK_SRC        BIT(1)
  73 #define ASPEED_PTCR_CTRL_CLK_EN         BIT(0)
  74
  75 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
  76 /* TYPE N */
  77 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK         GENMASK(31, 16)
  78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT         24
  79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H            20
  80 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L            16
  81 /* TYPE M */
  82 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK         GENMASK(15, 0)
  83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT         8
  84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H            4
  85 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L            0
  86
  87 /*
  88  * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
  89  * 0/1/2/3 register
  90  */
  91 #define DUTY_CTRL_PWM2_FALL_POINT       24
  92 #define DUTY_CTRL_PWM2_RISE_POINT       16
  93 #define DUTY_CTRL_PWM2_RISE_FALL_MASK   GENMASK(31, 16)
  94 #define DUTY_CTRL_PWM1_FALL_POINT       8
  95 #define DUTY_CTRL_PWM1_RISE_POINT       0
  96 #define DUTY_CTRL_PWM1_RISE_FALL_MASK   GENMASK(15, 0)
  97
  98 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
  99 #define TYPE_CTRL_FAN_MASK              (GENMASK(5, 1) | GENMASK(31, 16))
 100 #define TYPE_CTRL_FAN1_MASK             GENMASK(31, 0)
 101 #define TYPE_CTRL_FAN_PERIOD            16
 102 #define TYPE_CTRL_FAN_MODE              4
 103 #define TYPE_CTRL_FAN_DIVISION          1
 104 #define TYPE_CTRL_FAN_TYPE_EN           1
 105
 106 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
 107 /* bit [0,1] at 0x20, bit [2] at 0x60 */
 108 #define TACH_PWM_SOURCE_BIT01(x)        ((x) * 2)
 109 #define TACH_PWM_SOURCE_BIT2(x)         ((x) * 2)
 110 #define TACH_PWM_SOURCE_MASK_BIT01(x)   (0x3 << ((x) * 2))
 111 #define TACH_PWM_SOURCE_MASK_BIT2(x)    BIT((x) * 2)
 112
 113 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
 114 #define RESULT_STATUS_MASK              BIT(31)
 115 #define RESULT_VALUE_MASK               0xfffff
 116
 117 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
 118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1    15
 119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2    6
 120 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK     (BIT(7) | BIT(15))
 121
 122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1    14
 123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2    5
 124 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK     (BIT(6) | BIT(14))
 125
 126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1    13
 127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2    4
 128 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK     (BIT(5) | BIT(13))
 129
 130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1    12
 131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2    3
 132 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK     (BIT(4) | BIT(12))
 133
 134 #define ASPEED_PTCR_CTRL_PWMH_EN        BIT(11)
 135 #define ASPEED_PTCR_CTRL_PWMG_EN        BIT(10)
 136 #define ASPEED_PTCR_CTRL_PWMF_EN        BIT(9)
 137 #define ASPEED_PTCR_CTRL_PWME_EN        BIT(8)
 138
 139 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
 140 /* TYPE O */
 141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK         GENMASK(15, 0)
 142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT         8
 143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H            4
 144 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L            0
 145
 146 #define PWM_MAX 255
 147
 148 #define BOTH_EDGES 0x02 /* 10b */
 149
 150 #define M_PWM_DIV_H 0x00
 151 #define M_PWM_DIV_L 0x05
 152 #define M_PWM_PERIOD 0x5F
 153 #define M_TACH_CLK_DIV 0x00
 154 /*
 155  * 5:4 Type N fan tach mode selection bit:
 156  * 00: falling
 157  * 01: rising
 158  * 10: both
 159  * 11: reserved.
 160  */
 161 #define M_TACH_MODE 0x02 /* 10b */
 162 #define M_TACH_UNIT 0x0210
 163 #define INIT_FAN_CTRL 0xFF
 164
 165 /* How long we sleep in us while waiting for an RPM result. */
 166 #define ASPEED_RPM_STATUS_SLEEP_USEC    500
 167
 168 #define MAX_CDEV_NAME_LEN 16
 169
 170 struct aspeed_cooling_device {
 171         char name[16];
 172         struct aspeed_pwm_tacho_data *priv;
 173         struct thermal_cooling_device *tcdev;
 174         int pwm_port;
 175         u8 *cooling_levels;
 176         u8 max_state;
 177         u8 cur_state;
 178 };
 179
 180 struct aspeed_pwm_tacho_data {
 181         struct regmap *regmap;
 182         struct reset_control *rst;
 183         unsigned long clk_freq;
 184         bool pwm_present[8];
 185         bool fan_tach_present[16];
 186         u8 type_pwm_clock_unit[3];
 187         u8 type_pwm_clock_division_h[3];
 188         u8 type_pwm_clock_division_l[3];
 189         u8 type_fan_tach_clock_division[3];
 190         u8 type_fan_tach_mode[3];
 191         u16 type_fan_tach_unit[3];
 192         u8 pwm_port_type[8];
 193         u8 pwm_port_fan_ctrl[8];
 194         u8 fan_tach_ch_source[16];
 195         struct aspeed_cooling_device *cdev[8];
 196         const struct attribute_group *groups[3];
 197         /* protects access to shared ASPEED_PTCR_RESULT */
 198         struct mutex tach_lock;
 199 };
 200
 201 enum type { TYPEM, TYPEN, TYPEO };
 202
 203 struct type_params {
 204         u32 l_value;
 205         u32 h_value;
 206         u32 unit_value;
 207         u32 clk_ctrl_mask;
 208         u32 clk_ctrl_reg;
 209         u32 ctrl_reg;
 210         u32 ctrl_reg1;
 211 };
 212
 213 static const struct type_params type_params[] = {
 214         [TYPEM] = {
 215                 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
 216                 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
 217                 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
 218                 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
 219                 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
 220                 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
 221                 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
 222         },
 223         [TYPEN] = {
 224                 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
 225                 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
 226                 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
 227                 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
 228                 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
 229                 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
 230                 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
 231         },
 232         [TYPEO] = {
 233                 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
 234                 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
 235                 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
 236                 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
 237                 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
 238                 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
 239                 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
 240         }
 241 };
 242
 243 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
 244
 245 struct pwm_port_params {
 246         u32 pwm_en;
 247         u32 ctrl_reg;
 248         u32 type_part1;
 249         u32 type_part2;
 250         u32 type_mask;
 251         u32 duty_ctrl_rise_point;
 252         u32 duty_ctrl_fall_point;
 253         u32 duty_ctrl_reg;
 254         u32 duty_ctrl_rise_fall_mask;
 255 };
 256
 257 static const struct pwm_port_params pwm_port_params[] = {
 258         [PWMA] = {
 259                 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
 260                 .ctrl_reg = ASPEED_PTCR_CTRL,
 261                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
 262                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
 263                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
 264                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 265                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 266                 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
 267                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 268         },
 269         [PWMB] = {
 270                 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
 271                 .ctrl_reg = ASPEED_PTCR_CTRL,
 272                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
 273                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
 274                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
 275                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 276                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 277                 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
 278                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 279         },
 280         [PWMC] = {
 281                 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
 282                 .ctrl_reg = ASPEED_PTCR_CTRL,
 283                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
 284                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
 285                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
 286                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 287                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 288                 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
 289                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 290         },
 291         [PWMD] = {
 292                 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
 293                 .ctrl_reg = ASPEED_PTCR_CTRL,
 294                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
 295                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
 296                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
 297                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 298                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 299                 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
 300                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 301         },
 302         [PWME] = {
 303                 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
 304                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 305                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
 306                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
 307                 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
 308                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 309                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 310                 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
 311                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 312         },
 313         [PWMF] = {
 314                 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
 315                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 316                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
 317                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
 318                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
 319                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 320                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 321                 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
 322                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 323         },
 324         [PWMG] = {
 325                 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
 326                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 327                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
 328                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
 329                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
 330                 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 331                 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 332                 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
 333                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 334         },
 335         [PWMH] = {
 336                 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
 337                 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 338                 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
 339                 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
 340                 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
 341                 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 342                 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 343                 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
 344                 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 345         }
 346 };
 347
 348 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
 349                                              unsigned int val)
 350 {
 351         void __iomem *regs = (void __iomem *)context;
 352
 353         writel(val, regs + reg);
 354         return 0;
 355 }
 356
 357 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
 358                                             unsigned int *val)
 359 {
 360         void __iomem *regs = (void __iomem *)context;
 361
 362         *val = readl(regs + reg);
 363         return 0;
 364 }
 365
 366 static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
 367         .reg_bits = 32,
 368         .val_bits = 32,
 369         .reg_stride = 4,
 370         .max_register = ASPEED_PTCR_TYPEO_LIMIT,
 371         .reg_write = regmap_aspeed_pwm_tacho_reg_write,
 372         .reg_read = regmap_aspeed_pwm_tacho_reg_read,
 373         .fast_io = true,
 374 };
 375
 376 static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
 377 {
 378         regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 379                            ASPEED_PTCR_CTRL_CLK_EN,
 380                            val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
 381 }
 382
 383 static void aspeed_set_clock_source(struct regmap *regmap, int val)
 384 {
 385         regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 386                            ASPEED_PTCR_CTRL_CLK_SRC,
 387                            val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
 388 }
 389
 390 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
 391                                         u8 div_high, u8 div_low, u8 unit)
 392 {
 393         u32 reg_value = ((div_high << type_params[type].h_value) |
 394                          (div_low << type_params[type].l_value) |
 395                          (unit << type_params[type].unit_value));
 396
 397         regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
 398                            type_params[type].clk_ctrl_mask, reg_value);
 399 }
 400
 401 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
 402                                        bool enable)
 403 {
 404         regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
 405                            pwm_port_params[pwm_port].pwm_en,
 406                            enable ? pwm_port_params[pwm_port].pwm_en : 0);
 407 }
 408
 409 static void aspeed_set_pwm_port_type(struct regmap *regmap,
 410                                      u8 pwm_port, u8 type)
 411 {
 412         u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
 413
 414         reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
 415
 416         regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
 417                            pwm_port_params[pwm_port].type_mask, reg_value);
 418 }
 419
 420 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
 421                                                     u8 pwm_port, u8 rising,
 422                                                     u8 falling)
 423 {
 424         u32 reg_value = (rising <<
 425                          pwm_port_params[pwm_port].duty_ctrl_rise_point);
 426         reg_value |= (falling <<
 427                       pwm_port_params[pwm_port].duty_ctrl_fall_point);
 428
 429         regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
 430                            pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
 431                            reg_value);
 432 }
 433
 434 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
 435                                          bool enable)
 436 {
 437         regmap_update_bits(regmap, type_params[type].ctrl_reg,
 438                            TYPE_CTRL_FAN_TYPE_EN,
 439                            enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
 440 }
 441
 442 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
 443                                          u8 mode, u16 unit, u8 division)
 444 {
 445         u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
 446                          (unit << TYPE_CTRL_FAN_PERIOD) |
 447                          (division << TYPE_CTRL_FAN_DIVISION));
 448
 449         regmap_update_bits(regmap, type_params[type].ctrl_reg,
 450                            TYPE_CTRL_FAN_MASK, reg_value);
 451         regmap_update_bits(regmap, type_params[type].ctrl_reg1,
 452                            TYPE_CTRL_FAN1_MASK, unit << 16);
 453 }
 454
 455 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
 456                                           bool enable)
 457 {
 458         regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 459                            ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
 460                            enable ?
 461                            ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
 462 }
 463
 464 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
 465                                           u8 fan_tach_ch_source)
 466 {
 467         u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
 468                           TACH_PWM_SOURCE_BIT01(fan_tach_ch));
 469         u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
 470                           TACH_PWM_SOURCE_BIT2(fan_tach_ch));
 471
 472         regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
 473                            TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
 474                            reg_value1);
 475
 476         regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
 477                            TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
 478                            reg_value2);
 479 }
 480
 481 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
 482                                          u8 index, u8 fan_ctrl)
 483 {
 484         u16 period, dc_time_on;
 485
 486         period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
 487         period += 1;
 488         dc_time_on = (fan_ctrl * period) / PWM_MAX;
 489
 490         if (dc_time_on == 0) {
 491                 aspeed_set_pwm_port_enable(priv->regmap, index, false);
 492         } else {
 493                 if (dc_time_on == period)
 494                         dc_time_on = 0;
 495
 496                 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
 497                                                         dc_time_on);
 498                 aspeed_set_pwm_port_enable(priv->regmap, index, true);
 499         }
 500 }
 501
 502 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
 503                                                  *priv, u8 type)
 504 {
 505         u32 clk;
 506         u16 tacho_unit;
 507         u8 clk_unit, div_h, div_l, tacho_div;
 508
 509         clk = priv->clk_freq;
 510         clk_unit = priv->type_pwm_clock_unit[type];
 511         div_h = priv->type_pwm_clock_division_h[type];
 512         div_h = 0x1 << div_h;
 513         div_l = priv->type_pwm_clock_division_l[type];
 514         if (div_l == 0)
 515                 div_l = 1;
 516         else
 517                 div_l = div_l * 2;
 518
 519         tacho_unit = priv->type_fan_tach_unit[type];
 520         tacho_div = priv->type_fan_tach_clock_division[type];
 521
 522         tacho_div = 0x4 << (tacho_div * 2);
 523         return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
 524 }
 525
 526 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
 527                                       u8 fan_tach_ch)
 528 {
 529         u32 raw_data, tach_div, clk_source, msec, usec, val;
 530         u8 fan_tach_ch_source, type, mode, both;
 531         int ret;
 532
 533         mutex_lock(&priv->tach_lock);
 534
 535         regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
 536         regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
 537
 538         fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
 539         type = priv->pwm_port_type[fan_tach_ch_source];
 540
 541         msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
 542         usec = msec * 1000;
 543
 544         ret = regmap_read_poll_timeout(
 545                 priv->regmap,
 546                 ASPEED_PTCR_RESULT,
 547                 val,
 548                 (val & RESULT_STATUS_MASK),
 549                 ASPEED_RPM_STATUS_SLEEP_USEC,
 550                 usec);
 551
 552         mutex_unlock(&priv->tach_lock);
 553
 554         /* return -ETIMEDOUT if we didn't get an answer. */
 555         if (ret)
 556                 return ret;
 557
 558         raw_data = val & RESULT_VALUE_MASK;
 559         tach_div = priv->type_fan_tach_clock_division[type];
 560         /*
 561          * We need the mode to determine if the raw_data is double (from
 562          * counting both edges).
 563          */
 564         mode = priv->type_fan_tach_mode[type];
 565         both = (mode & BOTH_EDGES) ? 1 : 0;
 566
 567         tach_div = (0x4 << both) << (tach_div * 2);
 568         clk_source = priv->clk_freq;
 569
 570         if (raw_data == 0)
 571                 return 0;
 572
 573         return (clk_source * 60) / (2 * raw_data * tach_div);
 574 }
 575
 576 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
 577                          const char *buf, size_t count)
 578 {
 579         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 580         int index = sensor_attr->index;
 581         int ret;
 582         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 583         long fan_ctrl;
 584
 585         ret = kstrtol(buf, 10, &fan_ctrl);
 586         if (ret != 0)
 587                 return ret;
 588
 589         if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
 590                 return -EINVAL;
 591
 592         if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
 593                 return count;
 594
 595         priv->pwm_port_fan_ctrl[index] = fan_ctrl;
 596         aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
 597
 598         return count;
 599 }
 600
 601 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
 602                         char *buf)
 603 {
 604         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 605         int index = sensor_attr->index;
 606         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 607
 608         return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
 609 }
 610
 611 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr,
 612                         char *buf)
 613 {
 614         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 615         int index = sensor_attr->index;
 616         int rpm;
 617         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 618
 619         rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
 620         if (rpm < 0)
 621                 return rpm;
 622
 623         return sprintf(buf, "%d\n", rpm);
 624 }
 625
 626 static umode_t pwm_is_visible(struct kobject *kobj,
 627                               struct attribute *a, int index)
 628 {
 629         struct device *dev = container_of(kobj, struct device, kobj);
 630         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 631
 632         if (!priv->pwm_present[index])
 633                 return 0;
 634         return a->mode;
 635 }
 636
 637 static umode_t fan_dev_is_visible(struct kobject *kobj,
 638                                   struct attribute *a, int index)
 639 {
 640         struct device *dev = container_of(kobj, struct device, kobj);
 641         struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 642
 643         if (!priv->fan_tach_present[index])
 644                 return 0;
 645         return a->mode;
 646 }
 647
 648 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
 649 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
 650 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
 651 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
 652 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4);
 653 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5);
 654 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6);
 655 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7);
 656 static struct attribute *pwm_dev_attrs[] = {
 657         &sensor_dev_attr_pwm1.dev_attr.attr,
 658         &sensor_dev_attr_pwm2.dev_attr.attr,
 659         &sensor_dev_attr_pwm3.dev_attr.attr,
 660         &sensor_dev_attr_pwm4.dev_attr.attr,
 661         &sensor_dev_attr_pwm5.dev_attr.attr,
 662         &sensor_dev_attr_pwm6.dev_attr.attr,
 663         &sensor_dev_attr_pwm7.dev_attr.attr,
 664         &sensor_dev_attr_pwm8.dev_attr.attr,
 665         NULL,
 666 };
 667
 668 static const struct attribute_group pwm_dev_group = {
 669         .attrs = pwm_dev_attrs,
 670         .is_visible = pwm_is_visible,
 671 };
 672
 673 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
 674 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1);
 675 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2);
 676 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3);
 677 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4);
 678 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5);
 679 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6);
 680 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7);
 681 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8);
 682 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9);
 683 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10);
 684 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11);
 685 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12);
 686 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13);
 687 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14);
 688 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15);
 689 static struct attribute *fan_dev_attrs[] = {
 690         &sensor_dev_attr_fan1_input.dev_attr.attr,
 691         &sensor_dev_attr_fan2_input.dev_attr.attr,
 692         &sensor_dev_attr_fan3_input.dev_attr.attr,
 693         &sensor_dev_attr_fan4_input.dev_attr.attr,
 694         &sensor_dev_attr_fan5_input.dev_attr.attr,
 695         &sensor_dev_attr_fan6_input.dev_attr.attr,
 696         &sensor_dev_attr_fan7_input.dev_attr.attr,
 697         &sensor_dev_attr_fan8_input.dev_attr.attr,
 698         &sensor_dev_attr_fan9_input.dev_attr.attr,
 699         &sensor_dev_attr_fan10_input.dev_attr.attr,
 700         &sensor_dev_attr_fan11_input.dev_attr.attr,
 701         &sensor_dev_attr_fan12_input.dev_attr.attr,
 702         &sensor_dev_attr_fan13_input.dev_attr.attr,
 703         &sensor_dev_attr_fan14_input.dev_attr.attr,
 704         &sensor_dev_attr_fan15_input.dev_attr.attr,
 705         &sensor_dev_attr_fan16_input.dev_attr.attr,
 706         NULL
 707 };
 708
 709 static const struct attribute_group fan_dev_group = {
 710         .attrs = fan_dev_attrs,
 711         .is_visible = fan_dev_is_visible,
 712 };
 713
 714 /*
 715  * The clock type is type M :
 716  * The PWM frequency = 24MHz / (type M clock division L bit *
 717  * type M clock division H bit * (type M PWM period bit + 1))
 718  */
 719 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
 720 {
 721         priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
 722         priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
 723         priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
 724         aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
 725                                     M_PWM_DIV_L, M_PWM_PERIOD);
 726         aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
 727         priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
 728         priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
 729         priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
 730         aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
 731                                      M_TACH_UNIT, M_TACH_CLK_DIV);
 732 }
 733
 734 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
 735                                    u8 pwm_port)
 736 {
 737         aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
 738         priv->pwm_present[pwm_port] = true;
 739
 740         priv->pwm_port_type[pwm_port] = TYPEM;
 741         aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
 742
 743         priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
 744         aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
 745 }
 746
 747 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
 748                                            u8 *fan_tach_ch,
 749                                            int count,
 750                                            u8 pwm_source)
 751 {
 752         u8 val, index;
 753
 754         for (val = 0; val < count; val++) {
 755                 index = fan_tach_ch[val];
 756                 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
 757                 priv->fan_tach_present[index] = true;
 758                 priv->fan_tach_ch_source[index] = pwm_source;
 759                 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
 760         }
 761 }
 762
 763 static int
 764 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
 765                             unsigned long *state)
 766 {
 767         struct aspeed_cooling_device *cdev = tcdev->devdata;
 768
 769         *state = cdev->max_state;
 770
 771         return 0;
 772 }
 773
 774 static int
 775 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
 776                             unsigned long *state)
 777 {
 778         struct aspeed_cooling_device *cdev = tcdev->devdata;
 779
 780         *state = cdev->cur_state;
 781
 782         return 0;
 783 }
 784
 785 static int
 786 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
 787                             unsigned long state)
 788 {
 789         struct aspeed_cooling_device *cdev = tcdev->devdata;
 790
 791         if (state > cdev->max_state)
 792                 return -EINVAL;
 793
 794         cdev->cur_state = state;
 795         cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
 796                                         cdev->cooling_levels[cdev->cur_state];
 797         aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
 798                                      cdev->cooling_levels[cdev->cur_state]);
 799
 800         return 0;
 801 }
 802
 803 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
 804         .get_max_state = aspeed_pwm_cz_get_max_state,
 805         .get_cur_state = aspeed_pwm_cz_get_cur_state,
 806         .set_cur_state = aspeed_pwm_cz_set_cur_state,
 807 };
 808
 809 static int aspeed_create_pwm_cooling(struct device *dev,
 810                                      struct device_node *child,
 811                                      struct aspeed_pwm_tacho_data *priv,
 812                                      u32 pwm_port, u8 num_levels)
 813 {
 814         int ret;
 815         struct aspeed_cooling_device *cdev;
 816
 817         cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
 818
 819         if (!cdev)
 820                 return -ENOMEM;
 821
 822         cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
 823         if (!cdev->cooling_levels)
 824                 return -ENOMEM;
 825
 826         cdev->max_state = num_levels - 1;
 827         ret = of_property_read_u8_array(child, "cooling-levels",
 828                                         cdev->cooling_levels,
 829                                         num_levels);
 830         if (ret) {
 831                 dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
 832                 return ret;
 833         }
 834         snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
 835
 836         cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
 837                                         cdev->name, cdev, &aspeed_pwm_cool_ops);
 838         if (IS_ERR(cdev->tcdev))
 839                 return PTR_ERR(cdev->tcdev);
 840
 841         cdev->priv = priv;
 842         cdev->pwm_port = pwm_port;
 843
 844         priv->cdev[pwm_port] = cdev;
 845
 846         return 0;
 847 }
 848
 849 static int aspeed_create_fan(struct device *dev,
 850                              struct device_node *child,
 851                              struct aspeed_pwm_tacho_data *priv)
 852 {
 853         u8 *fan_tach_ch;
 854         u32 pwm_port;
 855         int ret, count;
 856
 857         ret = of_property_read_u32(child, "reg", &pwm_port);
 858         if (ret)
 859                 return ret;
 860         if (pwm_port >= ARRAY_SIZE(pwm_port_params))
 861                 return -EINVAL;
 862         aspeed_create_pwm_port(priv, (u8)pwm_port);
 863
 864         ret = of_property_count_u8_elems(child, "cooling-levels");
 865
 866         if (ret > 0) {
 867                 ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
 868                                                 ret);
 869                 if (ret)
 870                         return ret;
 871         }
 872
 873         count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
 874         if (count < 1)
 875                 return -EINVAL;
 876         fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch),
 877                                    GFP_KERNEL);
 878         if (!fan_tach_ch)
 879                 return -ENOMEM;
 880         ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
 881                                         fan_tach_ch, count);
 882         if (ret)
 883                 return ret;
 884         aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
 885
 886         return 0;
 887 }
 888
 889 static void aspeed_pwm_tacho_remove(void *data)
 890 {
 891         struct aspeed_pwm_tacho_data *priv = data;
 892
 893         reset_control_assert(priv->rst);
 894 }
 895
 896 static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
 897 {
 898         struct device *dev = &pdev->dev;
 899         struct device_node *np, *child;
 900         struct aspeed_pwm_tacho_data *priv;
 901         void __iomem *regs;
 902         struct device *hwmon;
 903         struct clk *clk;
 904         int ret;
 905
 906         np = dev->of_node;
 907         regs = devm_platform_ioremap_resource(pdev, 0);
 908         if (IS_ERR(regs))
 909                 return PTR_ERR(regs);
 910         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 911         if (!priv)
 912                 return -ENOMEM;
 913         mutex_init(&priv->tach_lock);
 914         priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
 915                         &aspeed_pwm_tacho_regmap_config);
 916         if (IS_ERR(priv->regmap))
 917                 return PTR_ERR(priv->regmap);
 918
 919         priv->rst = devm_reset_control_get_exclusive(dev, NULL);
 920         if (IS_ERR(priv->rst)) {
 921                 dev_err(dev,
 922                         "missing or invalid reset controller device tree entry");
 923                 return PTR_ERR(priv->rst);
 924         }
 925         reset_control_deassert(priv->rst);
 926
 927         ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv);
 928         if (ret)
 929                 return ret;
 930
 931         regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
 932         regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
 933
 934         clk = devm_clk_get(dev, NULL);
 935         if (IS_ERR(clk))
 936                 return -ENODEV;
 937         priv->clk_freq = clk_get_rate(clk);
 938         aspeed_set_clock_enable(priv->regmap, true);
 939         aspeed_set_clock_source(priv->regmap, 0);
 940
 941         aspeed_create_type(priv);
 942
 943         for_each_child_of_node(np, child) {
 944                 ret = aspeed_create_fan(dev, child, priv);
 945                 if (ret) {
 946                         of_node_put(child);
 947                         return ret;
 948                 }
 949         }
 950
 951         priv->groups[0] = &pwm_dev_group;
 952         priv->groups[1] = &fan_dev_group;
 953         priv->groups[2] = NULL;
 954         hwmon = devm_hwmon_device_register_with_groups(dev,
 955                                                        "aspeed_pwm_tacho",
 956                                                        priv, priv->groups);
 957         return PTR_ERR_OR_ZERO(hwmon);
 958 }
 959
 960 static const struct of_device_id of_pwm_tacho_match_table[] = {
 961         { .compatible = "aspeed,ast2400-pwm-tacho", },
 962         { .compatible = "aspeed,ast2500-pwm-tacho", },
 963         {},
 964 };
 965 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
 966
 967 static struct platform_driver aspeed_pwm_tacho_driver = {
 968         .probe          = aspeed_pwm_tacho_probe,
 969         .driver         = {
 970                 .name   = "aspeed_pwm_tacho",
 971                 .of_match_table = of_pwm_tacho_match_table,
 972         },
 973 };
 974
 975 module_platform_driver(aspeed_pwm_tacho_driver);
 976
 977 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
 978 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
 979 MODULE_LICENSE("GPL");