2 * H/W layer of ISHTP provider device (ISH)
4 * Copyright (c) 2014-2016, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/sched.h>
17 #include <linux/spinlock.h>
18 #include <linux/delay.h>
19 #include <linux/jiffies.h>
25 /* For FW reset flow */
26 static struct work_struct fw_reset_work;
27 static struct ishtp_device *ishtp_dev;
30 * ish_reg_read() - Read register
31 * @dev: ISHTP device pointer
32 * @offset: Register offset
34 * Read 32 bit register at a given offset
36 * Return: Read register value
38 static inline uint32_t ish_reg_read(const struct ishtp_device *dev,
41 struct ish_hw *hw = to_ish_hw(dev);
43 return readl(hw->mem_addr + offset);
47 * ish_reg_write() - Write register
48 * @dev: ISHTP device pointer
49 * @offset: Register offset
50 * @value: Value to write
52 * Writes 32 bit register at a give offset
54 static inline void ish_reg_write(struct ishtp_device *dev,
58 struct ish_hw *hw = to_ish_hw(dev);
60 writel(value, hw->mem_addr + offset);
64 * _ish_read_fw_sts_reg() - Read FW status register
65 * @dev: ISHTP device pointer
67 * Read FW status register
69 * Return: Read register value
71 static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev)
73 return ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
77 * check_generated_interrupt() - Check if ISH interrupt
78 * @dev: ISHTP device pointer
80 * Check if an interrupt was generated for ISH
82 * Return: Read true or false
84 static bool check_generated_interrupt(struct ishtp_device *dev)
86 bool interrupt_generated = true;
87 uint32_t pisr_val = 0;
89 if (dev->pdev->device == CHV_DEVICE_ID) {
90 pisr_val = ish_reg_read(dev, IPC_REG_PISR_CHV_AB);
92 IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val);
94 pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT);
95 interrupt_generated = !!pisr_val;
96 /* only busy-clear bit is RW, others are RO */
98 ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val);
101 return interrupt_generated;
105 * ish_is_input_ready() - Check if FW ready for RX
106 * @dev: ISHTP device pointer
108 * Check if ISH FW is ready for receiving data
110 * Return: Read true or false
112 static bool ish_is_input_ready(struct ishtp_device *dev)
114 uint32_t doorbell_val;
116 doorbell_val = ish_reg_read(dev, IPC_REG_HOST2ISH_DRBL);
117 return !IPC_IS_BUSY(doorbell_val);
121 * set_host_ready() - Indicate host ready
122 * @dev: ISHTP device pointer
124 * Set host ready indication to FW
126 static void set_host_ready(struct ishtp_device *dev)
128 if (dev->pdev->device == CHV_DEVICE_ID) {
129 if (dev->pdev->revision == REVISION_ID_CHT_A0 ||
130 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
131 REVISION_ID_CHT_Ax_SI)
132 ish_reg_write(dev, IPC_REG_HOST_COMM, 0x81);
133 else if (dev->pdev->revision == REVISION_ID_CHT_B0 ||
134 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
135 REVISION_ID_CHT_Bx_SI ||
136 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
137 REVISION_ID_CHT_Kx_SI ||
138 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
139 REVISION_ID_CHT_Dx_SI) {
140 uint32_t host_comm_val;
142 host_comm_val = ish_reg_read(dev, IPC_REG_HOST_COMM);
143 host_comm_val |= IPC_HOSTCOMM_INT_EN_BIT_CHV_AB | 0x81;
144 ish_reg_write(dev, IPC_REG_HOST_COMM, host_comm_val);
147 uint32_t host_pimr_val;
149 host_pimr_val = ish_reg_read(dev, IPC_REG_PIMR_BXT);
150 host_pimr_val |= IPC_PIMR_INT_EN_BIT_BXT;
152 * disable interrupt generated instead of
155 host_pimr_val &= ~IPC_HOST2ISH_BUSYCLEAR_MASK_BIT;
157 ish_reg_write(dev, IPC_REG_PIMR_BXT, host_pimr_val);
162 * ishtp_fw_is_ready() - Check if FW ready
163 * @dev: ISHTP device pointer
165 * Check if ISH FW is ready
167 * Return: Read true or false
169 static bool ishtp_fw_is_ready(struct ishtp_device *dev)
171 uint32_t ish_status = _ish_read_fw_sts_reg(dev);
173 return IPC_IS_ISH_ILUP(ish_status) &&
174 IPC_IS_ISH_ISHTP_READY(ish_status);
178 * ish_set_host_rdy() - Indicate host ready
179 * @dev: ISHTP device pointer
181 * Set host ready indication to FW
183 static void ish_set_host_rdy(struct ishtp_device *dev)
185 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
187 IPC_SET_HOST_READY(host_status);
188 ish_reg_write(dev, IPC_REG_HOST_COMM, host_status);
192 * ish_clr_host_rdy() - Indicate host not ready
193 * @dev: ISHTP device pointer
195 * Send host not ready indication to FW
197 static void ish_clr_host_rdy(struct ishtp_device *dev)
199 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
201 IPC_CLEAR_HOST_READY(host_status);
202 ish_reg_write(dev, IPC_REG_HOST_COMM, host_status);
206 * _ishtp_read_hdr() - Read message header
207 * @dev: ISHTP device pointer
209 * Read header of 32bit length
211 * Return: Read register value
213 static uint32_t _ishtp_read_hdr(const struct ishtp_device *dev)
215 return ish_reg_read(dev, IPC_REG_ISH2HOST_MSG);
219 * _ishtp_read - Read message
220 * @dev: ISHTP device pointer
221 * @buffer: message buffer
222 * @buffer_length: length of message buffer
224 * Read message from FW
228 static int _ishtp_read(struct ishtp_device *dev, unsigned char *buffer,
229 unsigned long buffer_length)
232 uint32_t *r_buf = (uint32_t *)buffer;
235 msg_offs = IPC_REG_ISH2HOST_MSG + sizeof(struct ishtp_msg_hdr);
236 for (i = 0; i < buffer_length; i += sizeof(uint32_t))
237 *r_buf++ = ish_reg_read(dev, msg_offs + i);
243 * write_ipc_from_queue() - try to write ipc msg from Tx queue to device
244 * @dev: ishtp device pointer
246 * Check if DRBL is cleared. if it is - write the first IPC msg, then call
247 * the callback function (unless it's NULL)
249 * Return: 0 for success else failure code
251 static int write_ipc_from_queue(struct ishtp_device *dev)
253 struct wr_msg_ctl_info *ipc_link;
254 unsigned long length;
257 uint32_t doorbell_val;
261 void (*ipc_send_compl)(void *);
262 void *ipc_send_compl_prm;
263 static int out_ipc_locked;
264 unsigned long out_ipc_flags;
266 if (dev->dev_state == ISHTP_DEV_DISABLED)
269 spin_lock_irqsave(&dev->out_ipc_spinlock, out_ipc_flags);
270 if (out_ipc_locked) {
271 spin_unlock_irqrestore(&dev->out_ipc_spinlock, out_ipc_flags);
275 if (!ish_is_input_ready(dev)) {
277 spin_unlock_irqrestore(&dev->out_ipc_spinlock, out_ipc_flags);
280 spin_unlock_irqrestore(&dev->out_ipc_spinlock, out_ipc_flags);
282 spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
284 * if tx send list is empty - return 0;
285 * may happen, as RX_COMPLETE handler doesn't check list emptiness.
287 if (list_empty(&dev->wr_processing_list_head.link)) {
288 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
293 ipc_link = list_entry(dev->wr_processing_list_head.link.next,
294 struct wr_msg_ctl_info, link);
295 /* first 4 bytes of the data is the doorbell value (IPC header) */
296 length = ipc_link->length - sizeof(uint32_t);
297 doorbell_val = *(uint32_t *)ipc_link->inline_data;
298 r_buf = (uint32_t *)(ipc_link->inline_data + sizeof(uint32_t));
300 /* If sending MNG_SYNC_FW_CLOCK, update clock again */
301 if (IPC_HEADER_GET_PROTOCOL(doorbell_val) == IPC_PROTOCOL_MNG &&
302 IPC_HEADER_GET_MNG_CMD(doorbell_val) == MNG_SYNC_FW_CLOCK) {
303 struct timespec ts_system;
304 struct timeval tv_utc;
305 uint64_t usec_system, usec_utc;
306 struct ipc_time_update_msg time_update;
307 struct time_sync_format ts_format;
309 get_monotonic_boottime(&ts_system);
310 do_gettimeofday(&tv_utc);
311 usec_system = (timespec_to_ns(&ts_system)) / NSEC_PER_USEC;
312 usec_utc = (uint64_t)tv_utc.tv_sec * 1000000 +
313 ((uint32_t)tv_utc.tv_usec);
314 ts_format.ts1_source = HOST_SYSTEM_TIME_USEC;
315 ts_format.ts2_source = HOST_UTC_TIME_USEC;
317 time_update.primary_host_time = usec_system;
318 time_update.secondary_host_time = usec_utc;
319 time_update.sync_info = ts_format;
321 memcpy(r_buf, &time_update,
322 sizeof(struct ipc_time_update_msg));
325 for (i = 0, reg_addr = IPC_REG_HOST2ISH_MSG; i < length >> 2; i++,
327 ish_reg_write(dev, reg_addr, r_buf[i]);
333 memcpy(®, &r_buf[length >> 2], rem);
334 ish_reg_write(dev, reg_addr, reg);
336 /* Flush writes to msg registers and doorbell */
337 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
339 /* Update IPC counters */
341 dev->ipc_tx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val);
343 ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, doorbell_val);
346 ipc_send_compl = ipc_link->ipc_send_compl;
347 ipc_send_compl_prm = ipc_link->ipc_send_compl_prm;
348 list_del_init(&ipc_link->link);
349 list_add_tail(&ipc_link->link, &dev->wr_free_list_head.link);
350 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
353 * callback will be called out of spinlock,
354 * after ipc_link returned to free list
357 ipc_send_compl(ipc_send_compl_prm);
363 * write_ipc_to_queue() - write ipc msg to Tx queue
364 * @dev: ishtp device instance
365 * @ipc_send_compl: Send complete callback
366 * @ipc_send_compl_prm: Parameter to send in complete callback
367 * @msg: Pointer to message
368 * @length: Length of message
370 * Recived msg with IPC (and upper protocol) header and add it to the device
371 * Tx-to-write list then try to send the first IPC waiting msg
372 * (if DRBL is cleared)
373 * This function returns negative value for failure (means free list
374 * is empty, or msg too long) and 0 for success.
376 * Return: 0 for success else failure code
378 static int write_ipc_to_queue(struct ishtp_device *dev,
379 void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
380 unsigned char *msg, int length)
382 struct wr_msg_ctl_info *ipc_link;
385 if (length > IPC_FULL_MSG_SIZE)
388 spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
389 if (list_empty(&dev->wr_free_list_head.link)) {
390 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
393 ipc_link = list_entry(dev->wr_free_list_head.link.next,
394 struct wr_msg_ctl_info, link);
395 list_del_init(&ipc_link->link);
397 ipc_link->ipc_send_compl = ipc_send_compl;
398 ipc_link->ipc_send_compl_prm = ipc_send_compl_prm;
399 ipc_link->length = length;
400 memcpy(ipc_link->inline_data, msg, length);
402 list_add_tail(&ipc_link->link, &dev->wr_processing_list_head.link);
403 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
405 write_ipc_from_queue(dev);
411 * ipc_send_mng_msg() - Send management message
412 * @dev: ishtp device instance
413 * @msg_code: Message code
414 * @msg: Pointer to message
415 * @size: Length of message
417 * Send management message to FW
419 * Return: 0 for success else failure code
421 static int ipc_send_mng_msg(struct ishtp_device *dev, uint32_t msg_code,
422 void *msg, size_t size)
424 unsigned char ipc_msg[IPC_FULL_MSG_SIZE];
425 uint32_t drbl_val = IPC_BUILD_MNG_MSG(msg_code, size);
427 memcpy(ipc_msg, &drbl_val, sizeof(uint32_t));
428 memcpy(ipc_msg + sizeof(uint32_t), msg, size);
429 return write_ipc_to_queue(dev, NULL, NULL, ipc_msg,
430 sizeof(uint32_t) + size);
434 * ish_fw_reset_handler() - FW reset handler
435 * @dev: ishtp device pointer
439 * Return: 0 for success else failure code
441 static int ish_fw_reset_handler(struct ishtp_device *dev)
445 struct wr_msg_ctl_info *processing, *next;
448 reset_id = ish_reg_read(dev, IPC_REG_ISH2HOST_MSG) & 0xFFFF;
450 /* Clear IPC output queue */
451 spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
452 list_for_each_entry_safe(processing, next,
453 &dev->wr_processing_list_head.link, link) {
454 list_move_tail(&processing->link, &dev->wr_free_list_head.link);
456 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
458 /* ISHTP notification in IPC_RESET */
459 ishtp_reset_handler(dev);
461 if (!ish_is_input_ready(dev))
462 timed_wait_for_timeout(WAIT_FOR_SEND_SLICE,
463 ish_is_input_ready(dev), (2 * HZ));
466 if (!ish_is_input_ready(dev))
469 * Set HOST2ISH.ILUP. Apparently we need this BEFORE sending
470 * RESET_NOTIFY_ACK - FW will be checking for it
472 ish_set_host_rdy(dev);
473 /* Send RESET_NOTIFY_ACK (with reset_id) */
474 ipc_send_mng_msg(dev, MNG_RESET_NOTIFY_ACK, &reset_id,
477 /* Wait for ISH FW'es ILUP and ISHTP_READY */
478 timed_wait_for_timeout(WAIT_FOR_SEND_SLICE, ishtp_fw_is_ready(dev),
480 if (!ishtp_fw_is_ready(dev)) {
484 ish_status = _ish_read_fw_sts_reg(dev);
486 "[ishtp-ish]: completed reset, ISH is dead (FWSTS = %08X)\n",
494 * ish_fw_reset_work_fn() - FW reset worker function
497 * Call ish_fw_reset_handler to complete FW reset
499 static void fw_reset_work_fn(struct work_struct *unused)
503 rv = ish_fw_reset_handler(ishtp_dev);
505 /* ISH is ILUP & ISHTP-ready. Restart ISHTP */
506 schedule_timeout(HZ / 3);
507 ishtp_dev->recvd_hw_ready = 1;
508 wake_up_interruptible(&ishtp_dev->wait_hw_ready);
510 /* ISHTP notification in IPC_RESET sequence completion */
511 ishtp_reset_compl_handler(ishtp_dev);
513 dev_err(ishtp_dev->devc, "[ishtp-ish]: FW reset failed (%d)\n",
518 * _ish_sync_fw_clock() -Sync FW clock with the OS clock
519 * @dev: ishtp device pointer
521 * Sync FW and OS time
523 static void _ish_sync_fw_clock(struct ishtp_device *dev)
525 static unsigned long prev_sync;
529 if (prev_sync && jiffies - prev_sync < 20 * HZ)
533 get_monotonic_boottime(&ts);
534 usec = (timespec_to_ns(&ts)) / NSEC_PER_USEC;
535 ipc_send_mng_msg(dev, MNG_SYNC_FW_CLOCK, &usec, sizeof(uint64_t));
539 * recv_ipc() - Receive and process IPC management messages
540 * @dev: ishtp device instance
541 * @doorbell_val: doorbell value
543 * This function runs in ISR context.
544 * NOTE: Any other mng command than reset_notify and reset_notify_ack
545 * won't wake BH handler
547 static void recv_ipc(struct ishtp_device *dev, uint32_t doorbell_val)
551 mng_cmd = IPC_HEADER_GET_MNG_CMD(doorbell_val);
557 case MNG_RX_CMPL_INDICATION:
558 if (dev->suspend_flag) {
559 dev->suspend_flag = 0;
560 wake_up_interruptible(&dev->suspend_wait);
562 if (dev->resume_flag) {
563 dev->resume_flag = 0;
564 wake_up_interruptible(&dev->resume_wait);
567 write_ipc_from_queue(dev);
570 case MNG_RESET_NOTIFY:
573 INIT_WORK(&fw_reset_work, fw_reset_work_fn);
575 schedule_work(&fw_reset_work);
578 case MNG_RESET_NOTIFY_ACK:
579 dev->recvd_hw_ready = 1;
580 wake_up_interruptible(&dev->wait_hw_ready);
586 * ish_irq_handler() - ISH IRQ handler
588 * @dev_id: ishtp device pointer
590 * ISH IRQ handler. If interrupt is generated and is for ISH it will process
593 irqreturn_t ish_irq_handler(int irq, void *dev_id)
595 struct ishtp_device *dev = dev_id;
596 uint32_t doorbell_val;
597 bool interrupt_generated;
599 /* Check that it's interrupt from ISH (may be shared) */
600 interrupt_generated = check_generated_interrupt(dev);
602 if (!interrupt_generated)
605 doorbell_val = ish_reg_read(dev, IPC_REG_ISH2HOST_DRBL);
606 if (!IPC_IS_BUSY(doorbell_val))
609 if (dev->dev_state == ISHTP_DEV_DISABLED)
612 /* Sanity check: IPC dgram length in header */
613 if (IPC_HEADER_GET_LENGTH(doorbell_val) > IPC_PAYLOAD_SIZE) {
615 "IPC hdr - bad length: %u; dropped\n",
616 (unsigned int)IPC_HEADER_GET_LENGTH(doorbell_val));
620 switch (IPC_HEADER_GET_PROTOCOL(doorbell_val)) {
623 case IPC_PROTOCOL_MNG:
624 recv_ipc(dev, doorbell_val);
626 case IPC_PROTOCOL_ISHTP:
632 /* Update IPC counters */
634 dev->ipc_rx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val);
636 ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0);
637 /* Flush write to doorbell */
638 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
644 * ish_disable_dma() - disable dma communication between host and ISHFW
645 * @dev: ishtp device pointer
647 * Clear the dma enable bit and wait for dma inactive.
649 * Return: 0 for success else error code.
651 static int ish_disable_dma(struct ishtp_device *dev)
653 unsigned int dma_delay;
655 /* Clear the dma enable bit */
656 ish_reg_write(dev, IPC_REG_ISH_RMP2, 0);
658 /* wait for dma inactive */
659 for (dma_delay = 0; dma_delay < MAX_DMA_DELAY &&
660 _ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA);
664 if (dma_delay >= MAX_DMA_DELAY) {
666 "Wait for DMA inactive timeout\n");
674 * ish_wakeup() - wakeup ishfw from waiting-for-host state
675 * @dev: ishtp device pointer
677 * Set the dma enable bit and send a void message to FW,
678 * it wil wakeup FW from waiting-for-host state.
680 static void ish_wakeup(struct ishtp_device *dev)
682 /* Set dma enable bit */
683 ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED);
686 * Send 0 IPC message so that ISH FW wakes up if it was already
689 ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT);
691 /* Flush writes to doorbell and REMAP2 */
692 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
696 * _ish_hw_reset() - HW reset
697 * @dev: ishtp device pointer
699 * Reset ISH HW to recover if any error
701 * Return: 0 for success else error fault code
703 static int _ish_hw_reset(struct ishtp_device *dev)
705 struct pci_dev *pdev = dev->pdev;
712 rv = pci_reset_function(pdev);
714 dev->dev_state = ISHTP_DEV_RESETTING;
717 dev_err(&pdev->dev, "Can't reset - no PM caps\n");
721 /* Disable dma communication between FW and host */
722 if (ish_disable_dma(dev)) {
724 "Can't reset - stuck with DMA in-progress\n");
728 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &csr);
730 csr &= ~PCI_PM_CTRL_STATE_MASK;
732 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
734 mdelay(pdev->d3_delay);
736 csr &= ~PCI_PM_CTRL_STATE_MASK;
738 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
740 /* Now we can enable ISH DMA operation and wakeup ISHFW */
747 * _ish_ipc_reset() - IPC reset
748 * @dev: ishtp device pointer
750 * Resets host and fw IPC and upper layers
752 * Return: 0 for success else error fault code
754 static int _ish_ipc_reset(struct ishtp_device *dev)
756 struct ipc_rst_payload_type ipc_mng_msg;
759 ipc_mng_msg.reset_id = 1;
760 ipc_mng_msg.reserved = 0;
764 /* Clear the incoming doorbell */
765 ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0);
766 /* Flush write to doorbell */
767 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
769 dev->recvd_hw_ready = 0;
772 rv = ipc_send_mng_msg(dev, MNG_RESET_NOTIFY, &ipc_mng_msg,
773 sizeof(struct ipc_rst_payload_type));
775 dev_err(dev->devc, "Failed to send IPC MNG_RESET_NOTIFY\n");
779 wait_event_interruptible_timeout(dev->wait_hw_ready,
780 dev->recvd_hw_ready, 2 * HZ);
781 if (!dev->recvd_hw_ready) {
782 dev_err(dev->devc, "Timed out waiting for HW ready\n");
790 * ish_hw_start() -Start ISH HW
791 * @dev: ishtp device pointer
793 * Set host to ready state and wait for FW reset
795 * Return: 0 for success else error fault code
797 int ish_hw_start(struct ishtp_device *dev)
799 ish_set_host_rdy(dev);
803 /* After that we can enable ISH DMA operation and wakeup ISHFW */
806 /* wait for FW-initiated reset flow */
807 if (!dev->recvd_hw_ready)
808 wait_event_interruptible_timeout(dev->wait_hw_ready,
812 if (!dev->recvd_hw_ready) {
814 "[ishtp-ish]: Timed out waiting for FW-initiated reset\n");
822 * ish_ipc_get_header() -Get doorbell value
823 * @dev: ishtp device pointer
824 * @length: length of message
827 * Get door bell value from message header
829 * Return: door bell value
831 static uint32_t ish_ipc_get_header(struct ishtp_device *dev, int length,
836 drbl_val = IPC_BUILD_HEADER(length, IPC_PROTOCOL_ISHTP, busy);
841 static const struct ishtp_hw_ops ish_hw_ops = {
842 .hw_reset = _ish_hw_reset,
843 .ipc_reset = _ish_ipc_reset,
844 .ipc_get_header = ish_ipc_get_header,
845 .ishtp_read = _ishtp_read,
846 .write = write_ipc_to_queue,
847 .get_fw_status = _ish_read_fw_sts_reg,
848 .sync_fw_clock = _ish_sync_fw_clock,
849 .ishtp_read_hdr = _ishtp_read_hdr
853 * ish_dev_init() -Initialize ISH devoce
856 * Allocate ISHTP device and initialize IPC processing
858 * Return: ISHTP device instance on success else NULL
860 struct ishtp_device *ish_dev_init(struct pci_dev *pdev)
862 struct ishtp_device *dev;
865 dev = kzalloc(sizeof(struct ishtp_device) + sizeof(struct ish_hw),
870 ishtp_device_init(dev);
872 init_waitqueue_head(&dev->wait_hw_ready);
874 spin_lock_init(&dev->wr_processing_spinlock);
875 spin_lock_init(&dev->out_ipc_spinlock);
877 /* Init IPC processing and free lists */
878 INIT_LIST_HEAD(&dev->wr_processing_list_head.link);
879 INIT_LIST_HEAD(&dev->wr_free_list_head.link);
880 for (i = 0; i < IPC_TX_FIFO_SIZE; ++i) {
881 struct wr_msg_ctl_info *tx_buf;
883 tx_buf = kzalloc(sizeof(struct wr_msg_ctl_info), GFP_KERNEL);
886 * IPC buffers may be limited or not available
887 * at all - although this shouldn't happen
890 "[ishtp-ish]: failure in Tx FIFO allocations (%d)\n",
894 list_add_tail(&tx_buf->link, &dev->wr_free_list_head.link);
897 dev->ops = &ish_hw_ops;
898 dev->devc = &pdev->dev;
899 dev->mtu = IPC_PAYLOAD_SIZE - sizeof(struct ishtp_msg_hdr);
904 * ish_device_disable() - Disable ISH device
905 * @dev: ISHTP device pointer
907 * Disable ISH by clearing host ready to inform firmware.
909 void ish_device_disable(struct ishtp_device *dev)
911 struct pci_dev *pdev = dev->pdev;
916 /* Disable dma communication between FW and host */
917 if (ish_disable_dma(dev)) {
919 "Can't reset - stuck with DMA in-progress\n");
923 /* Put ISH to D3hot state for power saving */
924 pci_set_power_state(pdev, PCI_D3hot);
926 dev->dev_state = ISHTP_DEV_DISABLED;
927 ish_clr_host_rdy(dev);