drivers/gpu/ipu-v3/ipu-prg.c

   1 /*
   2  * Copyright (c) 2016-2017 Lucas Stach, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  */
  13
  14 #include <drm/drm_fourcc.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <video/imx-ipu-v3.h>
  25
  26 #include "ipu-prv.h"
  27
  28 #define IPU_PRG_CTL                             0x00
  29 #define  IPU_PRG_CTL_BYPASS(i)                  (1 << (0 + i))
  30 #define  IPU_PRG_CTL_SOFT_ARID_MASK             0x3
  31 #define  IPU_PRG_CTL_SOFT_ARID_SHIFT(i)         (8 + i * 2)
  32 #define  IPU_PRG_CTL_SOFT_ARID(i, v)            ((v & 0x3) << (8 + 2 * i))
  33 #define  IPU_PRG_CTL_SO(i)                      (1 << (16 + i))
  34 #define  IPU_PRG_CTL_VFLIP(i)                   (1 << (19 + i))
  35 #define  IPU_PRG_CTL_BLOCK_MODE(i)              (1 << (22 + i))
  36 #define  IPU_PRG_CTL_CNT_LOAD_EN(i)             (1 << (25 + i))
  37 #define  IPU_PRG_CTL_SOFTRST                    (1 << 30)
  38 #define  IPU_PRG_CTL_SHADOW_EN                  (1 << 31)
  39
  40 #define IPU_PRG_STATUS                          0x04
  41 #define  IPU_PRG_STATUS_BUFFER0_READY(i)        (1 << (0 + i * 2))
  42 #define  IPU_PRG_STATUS_BUFFER1_READY(i)        (1 << (1 + i * 2))
  43
  44 #define IPU_PRG_QOS                             0x08
  45 #define  IPU_PRG_QOS_ARID_MASK                  0xf
  46 #define  IPU_PRG_QOS_ARID_SHIFT(i)              (0 + i * 4)
  47
  48 #define IPU_PRG_REG_UPDATE                      0x0c
  49 #define  IPU_PRG_REG_UPDATE_REG_UPDATE          (1 << 0)
  50
  51 #define IPU_PRG_STRIDE(i)                       (0x10 + i * 0x4)
  52 #define  IPU_PRG_STRIDE_STRIDE_MASK             0x3fff
  53
  54 #define IPU_PRG_CROP_LINE                       0x1c
  55
  56 #define IPU_PRG_THD                             0x20
  57
  58 #define IPU_PRG_BADDR(i)                        (0x24 + i * 0x4)
  59
  60 #define IPU_PRG_OFFSET(i)                       (0x30 + i * 0x4)
  61
  62 #define IPU_PRG_ILO(i)                          (0x3c + i * 0x4)
  63
  64 #define IPU_PRG_HEIGHT(i)                       (0x48 + i * 0x4)
  65 #define  IPU_PRG_HEIGHT_PRE_HEIGHT_MASK         0xfff
  66 #define  IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT        0
  67 #define  IPU_PRG_HEIGHT_IPU_HEIGHT_MASK         0xfff
  68 #define  IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT        16
  69
  70 struct ipu_prg_channel {
  71         bool                    enabled;
  72         int                     used_pre;
  73 };
  74
  75 struct ipu_prg {
  76         struct list_head        list;
  77         struct device           *dev;
  78         int                     id;
  79
  80         void __iomem            *regs;
  81         struct clk              *clk_ipg, *clk_axi;
  82         struct regmap           *iomuxc_gpr;
  83         struct ipu_pre          *pres[3];
  84
  85         struct ipu_prg_channel  chan[3];
  86 };
  87
  88 static DEFINE_MUTEX(ipu_prg_list_mutex);
  89 static LIST_HEAD(ipu_prg_list);
  90
  91 struct ipu_prg *
  92 ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
  93 {
  94         struct device_node *prg_node = of_parse_phandle(dev->of_node,
  95                                                         name, 0);
  96         struct ipu_prg *prg;
  97
  98         mutex_lock(&ipu_prg_list_mutex);
  99         list_for_each_entry(prg, &ipu_prg_list, list) {
 100                 if (prg_node == prg->dev->of_node) {
 101                         mutex_unlock(&ipu_prg_list_mutex);
 102                         device_link_add(dev, prg->dev, DL_FLAG_AUTOREMOVE);
 103                         prg->id = ipu_id;
 104                         of_node_put(prg_node);
 105                         return prg;
 106                 }
 107         }
 108         mutex_unlock(&ipu_prg_list_mutex);
 109
 110         of_node_put(prg_node);
 111
 112         return NULL;
 113 }
 114
 115 int ipu_prg_max_active_channels(void)
 116 {
 117         return ipu_pre_get_available_count();
 118 }
 119 EXPORT_SYMBOL_GPL(ipu_prg_max_active_channels);
 120
 121 bool ipu_prg_present(struct ipu_soc *ipu)
 122 {
 123         if (ipu->prg_priv)
 124                 return true;
 125
 126         return false;
 127 }
 128 EXPORT_SYMBOL_GPL(ipu_prg_present);
 129
 130 bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
 131                               uint64_t modifier)
 132 {
 133         const struct drm_format_info *info = drm_format_info(format);
 134
 135         if (info->num_planes != 1)
 136                 return false;
 137
 138         return true;
 139 }
 140 EXPORT_SYMBOL_GPL(ipu_prg_format_supported);
 141
 142 int ipu_prg_enable(struct ipu_soc *ipu)
 143 {
 144         struct ipu_prg *prg = ipu->prg_priv;
 145         int ret;
 146
 147         if (!prg)
 148                 return 0;
 149
 150         ret = clk_prepare_enable(prg->clk_axi);
 151         if (ret)
 152                 goto fail_disable_ipg;
 153
 154         return 0;
 155
 156 fail_disable_ipg:
 157         clk_disable_unprepare(prg->clk_ipg);
 158
 159         return ret;
 160 }
 161 EXPORT_SYMBOL_GPL(ipu_prg_enable);
 162
 163 void ipu_prg_disable(struct ipu_soc *ipu)
 164 {
 165         struct ipu_prg *prg = ipu->prg_priv;
 166
 167         if (!prg)
 168                 return;
 169
 170         clk_disable_unprepare(prg->clk_axi);
 171 }
 172 EXPORT_SYMBOL_GPL(ipu_prg_disable);
 173
 174 /*
 175  * The channel configuartion functions below are not thread safe, as they
 176  * must be only called from the atomic commit path in the DRM driver, which
 177  * is properly serialized.
 178  */
 179 static int ipu_prg_ipu_to_prg_chan(int ipu_chan)
 180 {
 181         /*
 182          * This isn't clearly documented in the RM, but IPU to PRG channel
 183          * assignment is fixed, as only with this mapping the control signals
 184          * match up.
 185          */
 186         switch (ipu_chan) {
 187         case IPUV3_CHANNEL_MEM_BG_SYNC:
 188                 return 0;
 189         case IPUV3_CHANNEL_MEM_FG_SYNC:
 190                 return 1;
 191         case IPUV3_CHANNEL_MEM_DC_SYNC:
 192                 return 2;
 193         default:
 194                 return -EINVAL;
 195         }
 196 }
 197
 198 static int ipu_prg_get_pre(struct ipu_prg *prg, int prg_chan)
 199 {
 200         int i, ret;
 201
 202         /* channel 0 is special as it is hardwired to one of the PREs */
 203         if (prg_chan == 0) {
 204                 ret = ipu_pre_get(prg->pres[0]);
 205                 if (ret)
 206                         goto fail;
 207                 prg->chan[prg_chan].used_pre = 0;
 208                 return 0;
 209         }
 210
 211         for (i = 1; i < 3; i++) {
 212                 ret = ipu_pre_get(prg->pres[i]);
 213                 if (!ret) {
 214                         u32 val, mux;
 215                         int shift;
 216
 217                         prg->chan[prg_chan].used_pre = i;
 218
 219                         /* configure the PRE to PRG channel mux */
 220                         shift = (i == 1) ? 12 : 14;
 221                         mux = (prg->id << 1) | (prg_chan - 1);
 222                         regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
 223                                            0x3 << shift, mux << shift);
 224
 225                         /* check other mux, must not point to same channel */
 226                         shift = (i == 1) ? 14 : 12;
 227                         regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val);
 228                         if (((val >> shift) & 0x3) == mux) {
 229                                 regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
 230                                                    0x3 << shift,
 231                                                    (mux ^ 0x1) << shift);
 232                         }
 233
 234                         return 0;
 235                 }
 236         }
 237
 238 fail:
 239         dev_err(prg->dev, "could not get PRE for PRG chan %d", prg_chan);
 240         return ret;
 241 }
 242
 243 static void ipu_prg_put_pre(struct ipu_prg *prg, int prg_chan)
 244 {
 245         struct ipu_prg_channel *chan = &prg->chan[prg_chan];
 246
 247         ipu_pre_put(prg->pres[chan->used_pre]);
 248         chan->used_pre = -1;
 249 }
 250
 251 void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
 252 {
 253         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
 254         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
 255         struct ipu_prg_channel *chan;
 256         u32 val;
 257
 258         if (prg_chan < 0)
 259                 return;
 260
 261         chan = &prg->chan[prg_chan];
 262         if (!chan->enabled)
 263                 return;
 264
 265         clk_prepare_enable(prg->clk_ipg);
 266
 267         val = readl(prg->regs + IPU_PRG_CTL);
 268         val |= IPU_PRG_CTL_BYPASS(prg_chan);
 269         writel(val, prg->regs + IPU_PRG_CTL);
 270
 271         val = IPU_PRG_REG_UPDATE_REG_UPDATE;
 272         writel(val, prg->regs + IPU_PRG_REG_UPDATE);
 273
 274         clk_disable_unprepare(prg->clk_ipg);
 275
 276         ipu_prg_put_pre(prg, prg_chan);
 277
 278         chan->enabled = false;
 279 }
 280 EXPORT_SYMBOL_GPL(ipu_prg_channel_disable);
 281
 282 int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
 283                               unsigned int axi_id, unsigned int width,
 284                               unsigned int height, unsigned int stride,
 285                               u32 format, unsigned long *eba)
 286 {
 287         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
 288         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
 289         struct ipu_prg_channel *chan;
 290         u32 val;
 291         int ret;
 292
 293         if (prg_chan < 0)
 294                 return prg_chan;
 295
 296         chan = &prg->chan[prg_chan];
 297
 298         if (chan->enabled) {
 299                 ipu_pre_update(prg->pres[chan->used_pre], *eba);
 300                 return 0;
 301         }
 302
 303         ret = ipu_prg_get_pre(prg, prg_chan);
 304         if (ret)
 305                 return ret;
 306
 307         ipu_pre_configure(prg->pres[chan->used_pre],
 308                           width, height, stride, format, *eba);
 309
 310
 311         ret = clk_prepare_enable(prg->clk_ipg);
 312         if (ret) {
 313                 ipu_prg_put_pre(prg, prg_chan);
 314                 return ret;
 315         }
 316
 317         val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK;
 318         writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
 319
 320         val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) <<
 321                IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT) |
 322               ((height & IPU_PRG_HEIGHT_IPU_HEIGHT_MASK) <<
 323                IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT);
 324         writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
 325
 326         val = ipu_pre_get_baddr(prg->pres[chan->used_pre]);
 327         *eba = val;
 328         writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
 329
 330         val = readl(prg->regs + IPU_PRG_CTL);
 331         /* config AXI ID */
 332         val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
 333                  IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
 334         val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id);
 335         /* enable channel */
 336         val &= ~IPU_PRG_CTL_BYPASS(prg_chan);
 337         writel(val, prg->regs + IPU_PRG_CTL);
 338
 339         val = IPU_PRG_REG_UPDATE_REG_UPDATE;
 340         writel(val, prg->regs + IPU_PRG_REG_UPDATE);
 341
 342         /* wait for both double buffers to be filled */
 343         readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
 344                            (val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
 345                            (val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
 346                            5, 1000);
 347
 348         clk_disable_unprepare(prg->clk_ipg);
 349
 350         chan->enabled = true;
 351         return 0;
 352 }
 353 EXPORT_SYMBOL_GPL(ipu_prg_channel_configure);
 354
 355 static int ipu_prg_probe(struct platform_device *pdev)
 356 {
 357         struct device *dev = &pdev->dev;
 358         struct resource *res;
 359         struct ipu_prg *prg;
 360         u32 val;
 361         int i, ret;
 362
 363         prg = devm_kzalloc(dev, sizeof(*prg), GFP_KERNEL);
 364         if (!prg)
 365                 return -ENOMEM;
 366
 367         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 368         prg->regs = devm_ioremap_resource(&pdev->dev, res);
 369         if (IS_ERR(prg->regs))
 370                 return PTR_ERR(prg->regs);
 371
 372
 373         prg->clk_ipg = devm_clk_get(dev, "ipg");
 374         if (IS_ERR(prg->clk_ipg))
 375                 return PTR_ERR(prg->clk_ipg);
 376
 377         prg->clk_axi = devm_clk_get(dev, "axi");
 378         if (IS_ERR(prg->clk_axi))
 379                 return PTR_ERR(prg->clk_axi);
 380
 381         prg->iomuxc_gpr =
 382                 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 383         if (IS_ERR(prg->iomuxc_gpr))
 384                 return PTR_ERR(prg->iomuxc_gpr);
 385
 386         for (i = 0; i < 3; i++) {
 387                 prg->pres[i] = ipu_pre_lookup_by_phandle(dev, "fsl,pres", i);
 388                 if (!prg->pres[i])
 389                         return -EPROBE_DEFER;
 390         }
 391
 392         ret = clk_prepare_enable(prg->clk_ipg);
 393         if (ret)
 394                 return ret;
 395
 396         /* init to free running mode */
 397         val = readl(prg->regs + IPU_PRG_CTL);
 398         val |= IPU_PRG_CTL_SHADOW_EN;
 399         writel(val, prg->regs + IPU_PRG_CTL);
 400
 401         /* disable address threshold */
 402         writel(0xffffffff, prg->regs + IPU_PRG_THD);
 403
 404         clk_disable_unprepare(prg->clk_ipg);
 405
 406         prg->dev = dev;
 407         platform_set_drvdata(pdev, prg);
 408         mutex_lock(&ipu_prg_list_mutex);
 409         list_add(&prg->list, &ipu_prg_list);
 410         mutex_unlock(&ipu_prg_list_mutex);
 411
 412         return 0;
 413 }
 414
 415 static int ipu_prg_remove(struct platform_device *pdev)
 416 {
 417         struct ipu_prg *prg = platform_get_drvdata(pdev);
 418
 419         mutex_lock(&ipu_prg_list_mutex);
 420         list_del(&prg->list);
 421         mutex_unlock(&ipu_prg_list_mutex);
 422
 423         return 0;
 424 }
 425
 426 static const struct of_device_id ipu_prg_dt_ids[] = {
 427         { .compatible = "fsl,imx6qp-prg", },
 428         { /* sentinel */ },
 429 };
 430
 431 struct platform_driver ipu_prg_drv = {
 432         .probe          = ipu_prg_probe,
 433         .remove         = ipu_prg_remove,
 434         .driver         = {
 435                 .name   = "imx-ipu-prg",
 436                 .of_match_table = ipu_prg_dt_ids,
 437         },
 438 };