drivers/gpu/ipu-v3/ipu-pre.c

   1 /*
   2  * Copyright (c) 2017 Lucas Stach, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  */
  13
  14 #include <drm/drm_fourcc.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/genalloc.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <video/imx-ipu-v3.h>
  22
  23 #include "ipu-prv.h"
  24
  25 #define IPU_PRE_MAX_WIDTH       2048
  26 #define IPU_PRE_NUM_SCANLINES   8
  27
  28 #define IPU_PRE_CTRL                                    0x000
  29 #define IPU_PRE_CTRL_SET                                0x004
  30 #define  IPU_PRE_CTRL_ENABLE                            (1 << 0)
  31 #define  IPU_PRE_CTRL_BLOCK_EN                          (1 << 1)
  32 #define  IPU_PRE_CTRL_BLOCK_16                          (1 << 2)
  33 #define  IPU_PRE_CTRL_SDW_UPDATE                        (1 << 4)
  34 #define  IPU_PRE_CTRL_VFLIP                             (1 << 5)
  35 #define  IPU_PRE_CTRL_SO                                (1 << 6)
  36 #define  IPU_PRE_CTRL_INTERLACED_FIELD                  (1 << 7)
  37 #define  IPU_PRE_CTRL_HANDSHAKE_EN                      (1 << 8)
  38 #define  IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v)             ((v & 0x3) << 9)
  39 #define  IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN           (1 << 11)
  40 #define  IPU_PRE_CTRL_EN_REPEAT                         (1 << 28)
  41 #define  IPU_PRE_CTRL_TPR_REST_SEL                      (1 << 29)
  42 #define  IPU_PRE_CTRL_CLKGATE                           (1 << 30)
  43 #define  IPU_PRE_CTRL_SFTRST                            (1 << 31)
  44
  45 #define IPU_PRE_CUR_BUF                                 0x030
  46
  47 #define IPU_PRE_NEXT_BUF                                0x040
  48
  49 #define IPU_PRE_TPR_CTRL                                0x070
  50 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT(v)                ((v & 0xff) << 0)
  51 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK              0xff
  52
  53 #define IPU_PRE_PREFETCH_ENG_CTRL                       0x080
  54 #define  IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN              (1 << 0)
  55 #define  IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v)          ((v & 0x7) << 1)
  56 #define  IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v)      ((v & 0x3) << 4)
  57 #define  IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v)    ((v & 0x7) << 8)
  58 #define  IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS             (1 << 11)
  59 #define  IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE            (1 << 12)
  60 #define  IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP          (1 << 14)
  61 #define  IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN       (1 << 15)
  62
  63 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE                 0x0a0
  64 #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v)       ((v & 0xffff) << 0)
  65 #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v)      ((v & 0xffff) << 16)
  66
  67 #define IPU_PRE_PREFETCH_ENG_PITCH                      0x0d0
  68 #define  IPU_PRE_PREFETCH_ENG_PITCH_Y(v)                ((v & 0xffff) << 0)
  69 #define  IPU_PRE_PREFETCH_ENG_PITCH_UV(v)               ((v & 0xffff) << 16)
  70
  71 #define IPU_PRE_STORE_ENG_CTRL                          0x110
  72 #define  IPU_PRE_STORE_ENG_CTRL_STORE_EN                (1 << 0)
  73 #define  IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v)         ((v & 0x7) << 1)
  74 #define  IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v)    ((v & 0x3) << 4)
  75
  76 #define IPU_PRE_STORE_ENG_STATUS                        0x120
  77 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK    0xffff
  78 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT   0
  79 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK    0x3fff
  80 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT   16
  81 #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL       (1 << 30)
  82 #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIELD           (1 << 31)
  83
  84 #define IPU_PRE_STORE_ENG_SIZE                          0x130
  85 #define  IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v)          ((v & 0xffff) << 0)
  86 #define  IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v)         ((v & 0xffff) << 16)
  87
  88 #define IPU_PRE_STORE_ENG_PITCH                         0x140
  89 #define  IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v)           ((v & 0xffff) << 0)
  90
  91 #define IPU_PRE_STORE_ENG_ADDR                          0x150
  92
  93 struct ipu_pre {
  94         struct list_head        list;
  95         struct device           *dev;
  96
  97         void __iomem            *regs;
  98         struct clk              *clk_axi;
  99         struct gen_pool         *iram;
 100
 101         dma_addr_t              buffer_paddr;
 102         void                    *buffer_virt;
 103         bool                    in_use;
 104         unsigned int            safe_window_end;
 105         unsigned int            last_bufaddr;
 106 };
 107
 108 static DEFINE_MUTEX(ipu_pre_list_mutex);
 109 static LIST_HEAD(ipu_pre_list);
 110 static int available_pres;
 111
 112 int ipu_pre_get_available_count(void)
 113 {
 114         return available_pres;
 115 }
 116
 117 struct ipu_pre *
 118 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
 119 {
 120         struct device_node *pre_node = of_parse_phandle(dev->of_node,
 121                                                         name, index);
 122         struct ipu_pre *pre;
 123
 124         mutex_lock(&ipu_pre_list_mutex);
 125         list_for_each_entry(pre, &ipu_pre_list, list) {
 126                 if (pre_node == pre->dev->of_node) {
 127                         mutex_unlock(&ipu_pre_list_mutex);
 128                         device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE);
 129                         of_node_put(pre_node);
 130                         return pre;
 131                 }
 132         }
 133         mutex_unlock(&ipu_pre_list_mutex);
 134
 135         of_node_put(pre_node);
 136
 137         return NULL;
 138 }
 139
 140 int ipu_pre_get(struct ipu_pre *pre)
 141 {
 142         u32 val;
 143
 144         if (pre->in_use)
 145                 return -EBUSY;
 146
 147         /* first get the engine out of reset and remove clock gating */
 148         writel(0, pre->regs + IPU_PRE_CTRL);
 149
 150         /* init defaults that should be applied to all streams */
 151         val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
 152               IPU_PRE_CTRL_HANDSHAKE_EN |
 153               IPU_PRE_CTRL_TPR_REST_SEL |
 154               IPU_PRE_CTRL_BLOCK_16 | IPU_PRE_CTRL_SDW_UPDATE;
 155         writel(val, pre->regs + IPU_PRE_CTRL);
 156
 157         pre->in_use = true;
 158         return 0;
 159 }
 160
 161 void ipu_pre_put(struct ipu_pre *pre)
 162 {
 163         writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
 164
 165         pre->in_use = false;
 166 }
 167
 168 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
 169                        unsigned int height, unsigned int stride, u32 format,
 170                        unsigned int bufaddr)
 171 {
 172         const struct drm_format_info *info = drm_format_info(format);
 173         u32 active_bpp = info->cpp[0] >> 1;
 174         u32 val;
 175
 176         /* calculate safe window for ctrl register updates */
 177         pre->safe_window_end = height - 2;
 178
 179         writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
 180         writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
 181         pre->last_bufaddr = bufaddr;
 182
 183         val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
 184               IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
 185               IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
 186               IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
 187               IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
 188         writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
 189
 190         val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
 191               IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
 192         writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
 193
 194         val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
 195         writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
 196
 197         val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
 198               IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
 199               IPU_PRE_STORE_ENG_CTRL_STORE_EN;
 200         writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
 201
 202         val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
 203               IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
 204         writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
 205
 206         val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
 207         writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
 208
 209         writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
 210
 211         val = readl(pre->regs + IPU_PRE_CTRL);
 212         val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
 213                IPU_PRE_CTRL_SDW_UPDATE;
 214         writel(val, pre->regs + IPU_PRE_CTRL);
 215 }
 216
 217 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
 218 {
 219         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 220         unsigned short current_yblock;
 221         u32 val;
 222
 223         if (bufaddr == pre->last_bufaddr)
 224                 return;
 225
 226         writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
 227         pre->last_bufaddr = bufaddr;
 228
 229         do {
 230                 if (time_after(jiffies, timeout)) {
 231                         dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
 232                         return;
 233                 }
 234
 235                 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
 236                 current_yblock =
 237                         (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
 238                         IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
 239         } while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
 240
 241         writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
 242 }
 243
 244 u32 ipu_pre_get_baddr(struct ipu_pre *pre)
 245 {
 246         return (u32)pre->buffer_paddr;
 247 }
 248
 249 static int ipu_pre_probe(struct platform_device *pdev)
 250 {
 251         struct device *dev = &pdev->dev;
 252         struct resource *res;
 253         struct ipu_pre *pre;
 254
 255         pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
 256         if (!pre)
 257                 return -ENOMEM;
 258
 259         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 260         pre->regs = devm_ioremap_resource(&pdev->dev, res);
 261         if (IS_ERR(pre->regs))
 262                 return PTR_ERR(pre->regs);
 263
 264         pre->clk_axi = devm_clk_get(dev, "axi");
 265         if (IS_ERR(pre->clk_axi))
 266                 return PTR_ERR(pre->clk_axi);
 267
 268         pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
 269         if (!pre->iram)
 270                 return -EPROBE_DEFER;
 271
 272         /*
 273          * Allocate IRAM buffer with maximum size. This could be made dynamic,
 274          * but as there is no other user of this IRAM region and we can fit all
 275          * max sized buffers into it, there is no need yet.
 276          */
 277         pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
 278                                               IPU_PRE_NUM_SCANLINES * 4,
 279                                               &pre->buffer_paddr);
 280         if (!pre->buffer_virt)
 281                 return -ENOMEM;
 282
 283         clk_prepare_enable(pre->clk_axi);
 284
 285         pre->dev = dev;
 286         platform_set_drvdata(pdev, pre);
 287         mutex_lock(&ipu_pre_list_mutex);
 288         list_add(&pre->list, &ipu_pre_list);
 289         available_pres++;
 290         mutex_unlock(&ipu_pre_list_mutex);
 291
 292         return 0;
 293 }
 294
 295 static int ipu_pre_remove(struct platform_device *pdev)
 296 {
 297         struct ipu_pre *pre = platform_get_drvdata(pdev);
 298
 299         mutex_lock(&ipu_pre_list_mutex);
 300         list_del(&pre->list);
 301         available_pres--;
 302         mutex_unlock(&ipu_pre_list_mutex);
 303
 304         clk_disable_unprepare(pre->clk_axi);
 305
 306         if (pre->buffer_virt)
 307                 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
 308                               IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
 309         return 0;
 310 }
 311
 312 static const struct of_device_id ipu_pre_dt_ids[] = {
 313         { .compatible = "fsl,imx6qp-pre", },
 314         { /* sentinel */ },
 315 };
 316
 317 struct platform_driver ipu_pre_drv = {
 318         .probe          = ipu_pre_probe,
 319         .remove         = ipu_pre_remove,
 320         .driver         = {
 321                 .name   = "imx-ipu-pre",
 322                 .of_match_table = ipu_pre_dt_ids,
 323         },
 324 };