drivers/gpu/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/reset.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/list.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/irqdomain.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_graph.h>
  32
  33 #include <drm/drm_fourcc.h>
  34
  35 #include <video/imx-ipu-v3.h>
  36 #include "ipu-prv.h"
  37
  38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  39 {
  40         return readl(ipu->cm_reg + offset);
  41 }
  42
  43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  44 {
  45         writel(value, ipu->cm_reg + offset);
  46 }
  47
  48 int ipu_get_num(struct ipu_soc *ipu)
  49 {
  50         return ipu->id;
  51 }
  52 EXPORT_SYMBOL_GPL(ipu_get_num);
  53
  54 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  55 {
  56         u32 val;
  57
  58         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  59         val |= 0x8;
  60         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  61 }
  62 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  63
  64 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  65 {
  66         switch (drm_fourcc) {
  67         case DRM_FORMAT_ARGB1555:
  68         case DRM_FORMAT_ABGR1555:
  69         case DRM_FORMAT_RGBA5551:
  70         case DRM_FORMAT_BGRA5551:
  71         case DRM_FORMAT_RGB565:
  72         case DRM_FORMAT_BGR565:
  73         case DRM_FORMAT_RGB888:
  74         case DRM_FORMAT_BGR888:
  75         case DRM_FORMAT_ARGB4444:
  76         case DRM_FORMAT_XRGB8888:
  77         case DRM_FORMAT_XBGR8888:
  78         case DRM_FORMAT_RGBX8888:
  79         case DRM_FORMAT_BGRX8888:
  80         case DRM_FORMAT_ARGB8888:
  81         case DRM_FORMAT_ABGR8888:
  82         case DRM_FORMAT_RGBA8888:
  83         case DRM_FORMAT_BGRA8888:
  84                 return IPUV3_COLORSPACE_RGB;
  85         case DRM_FORMAT_YUYV:
  86         case DRM_FORMAT_UYVY:
  87         case DRM_FORMAT_YUV420:
  88         case DRM_FORMAT_YVU420:
  89         case DRM_FORMAT_YUV422:
  90         case DRM_FORMAT_YVU422:
  91         case DRM_FORMAT_NV12:
  92         case DRM_FORMAT_NV21:
  93         case DRM_FORMAT_NV16:
  94         case DRM_FORMAT_NV61:
  95                 return IPUV3_COLORSPACE_YUV;
  96         default:
  97                 return IPUV3_COLORSPACE_UNKNOWN;
  98         }
  99 }
 100 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
 101
 102 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 103 {
 104         switch (pixelformat) {
 105         case V4L2_PIX_FMT_YUV420:
 106         case V4L2_PIX_FMT_YVU420:
 107         case V4L2_PIX_FMT_YUV422P:
 108         case V4L2_PIX_FMT_UYVY:
 109         case V4L2_PIX_FMT_YUYV:
 110         case V4L2_PIX_FMT_NV12:
 111         case V4L2_PIX_FMT_NV21:
 112         case V4L2_PIX_FMT_NV16:
 113         case V4L2_PIX_FMT_NV61:
 114                 return IPUV3_COLORSPACE_YUV;
 115         case V4L2_PIX_FMT_RGB32:
 116         case V4L2_PIX_FMT_BGR32:
 117         case V4L2_PIX_FMT_RGB24:
 118         case V4L2_PIX_FMT_BGR24:
 119         case V4L2_PIX_FMT_RGB565:
 120                 return IPUV3_COLORSPACE_RGB;
 121         default:
 122                 return IPUV3_COLORSPACE_UNKNOWN;
 123         }
 124 }
 125 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 126
 127 bool ipu_pixelformat_is_planar(u32 pixelformat)
 128 {
 129         switch (pixelformat) {
 130         case V4L2_PIX_FMT_YUV420:
 131         case V4L2_PIX_FMT_YVU420:
 132         case V4L2_PIX_FMT_YUV422P:
 133         case V4L2_PIX_FMT_NV12:
 134         case V4L2_PIX_FMT_NV21:
 135         case V4L2_PIX_FMT_NV16:
 136         case V4L2_PIX_FMT_NV61:
 137                 return true;
 138         }
 139
 140         return false;
 141 }
 142 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
 143
 144 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
 145 {
 146         switch (mbus_code & 0xf000) {
 147         case 0x1000:
 148                 return IPUV3_COLORSPACE_RGB;
 149         case 0x2000:
 150                 return IPUV3_COLORSPACE_YUV;
 151         default:
 152                 return IPUV3_COLORSPACE_UNKNOWN;
 153         }
 154 }
 155 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
 156
 157 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
 158 {
 159         switch (pixelformat) {
 160         case V4L2_PIX_FMT_YUV420:
 161         case V4L2_PIX_FMT_YVU420:
 162         case V4L2_PIX_FMT_YUV422P:
 163         case V4L2_PIX_FMT_NV12:
 164         case V4L2_PIX_FMT_NV21:
 165         case V4L2_PIX_FMT_NV16:
 166         case V4L2_PIX_FMT_NV61:
 167                 /*
 168                  * for the planar YUV formats, the stride passed to
 169                  * cpmem must be the stride in bytes of the Y plane.
 170                  * And all the planar YUV formats have an 8-bit
 171                  * Y component.
 172                  */
 173                 return (8 * pixel_stride) >> 3;
 174         case V4L2_PIX_FMT_RGB565:
 175         case V4L2_PIX_FMT_YUYV:
 176         case V4L2_PIX_FMT_UYVY:
 177                 return (16 * pixel_stride) >> 3;
 178         case V4L2_PIX_FMT_BGR24:
 179         case V4L2_PIX_FMT_RGB24:
 180                 return (24 * pixel_stride) >> 3;
 181         case V4L2_PIX_FMT_BGR32:
 182         case V4L2_PIX_FMT_RGB32:
 183                 return (32 * pixel_stride) >> 3;
 184         default:
 185                 break;
 186         }
 187
 188         return -EINVAL;
 189 }
 190 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
 191
 192 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 193                             bool hflip, bool vflip)
 194 {
 195         u32 r90, vf, hf;
 196
 197         switch (degrees) {
 198         case 0:
 199                 vf = hf = r90 = 0;
 200                 break;
 201         case 90:
 202                 vf = hf = 0;
 203                 r90 = 1;
 204                 break;
 205         case 180:
 206                 vf = hf = 1;
 207                 r90 = 0;
 208                 break;
 209         case 270:
 210                 vf = hf = r90 = 1;
 211                 break;
 212         default:
 213                 return -EINVAL;
 214         }
 215
 216         hf ^= (u32)hflip;
 217         vf ^= (u32)vflip;
 218
 219         *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
 220         return 0;
 221 }
 222 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
 223
 224 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 225                             bool hflip, bool vflip)
 226 {
 227         u32 r90, vf, hf;
 228
 229         r90 = ((u32)mode >> 2) & 0x1;
 230         hf = ((u32)mode >> 1) & 0x1;
 231         vf = ((u32)mode >> 0) & 0x1;
 232         hf ^= (u32)hflip;
 233         vf ^= (u32)vflip;
 234
 235         switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
 236         case IPU_ROTATE_NONE:
 237                 *degrees = 0;
 238                 break;
 239         case IPU_ROTATE_90_RIGHT:
 240                 *degrees = 90;
 241                 break;
 242         case IPU_ROTATE_180:
 243                 *degrees = 180;
 244                 break;
 245         case IPU_ROTATE_90_LEFT:
 246                 *degrees = 270;
 247                 break;
 248         default:
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
 255
 256 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 257 {
 258         struct ipuv3_channel *channel;
 259
 260         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 261
 262         if (num > 63)
 263                 return ERR_PTR(-ENODEV);
 264
 265         mutex_lock(&ipu->channel_lock);
 266
 267         channel = &ipu->channel[num];
 268
 269         if (channel->busy) {
 270                 channel = ERR_PTR(-EBUSY);
 271                 goto out;
 272         }
 273
 274         channel->busy = true;
 275         channel->num = num;
 276
 277 out:
 278         mutex_unlock(&ipu->channel_lock);
 279
 280         return channel;
 281 }
 282 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 283
 284 void ipu_idmac_put(struct ipuv3_channel *channel)
 285 {
 286         struct ipu_soc *ipu = channel->ipu;
 287
 288         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 289
 290         mutex_lock(&ipu->channel_lock);
 291
 292         channel->busy = false;
 293
 294         mutex_unlock(&ipu->channel_lock);
 295 }
 296 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 297
 298 #define idma_mask(ch)                   (1 << ((ch) & 0x1f))
 299
 300 /*
 301  * This is an undocumented feature, a write one to a channel bit in
 302  * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
 303  * internal current buffer pointer so that transfers start from buffer
 304  * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
 305  * only says these are read-only registers). This operation is required
 306  * for channel linking to work correctly, for instance video capture
 307  * pipelines that carry out image rotations will fail after the first
 308  * streaming unless this function is called for each channel before
 309  * re-enabling the channels.
 310  */
 311 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
 312 {
 313         struct ipu_soc *ipu = channel->ipu;
 314         unsigned int chno = channel->num;
 315
 316         ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
 317 }
 318
 319 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 320                 bool doublebuffer)
 321 {
 322         struct ipu_soc *ipu = channel->ipu;
 323         unsigned long flags;
 324         u32 reg;
 325
 326         spin_lock_irqsave(&ipu->lock, flags);
 327
 328         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 329         if (doublebuffer)
 330                 reg |= idma_mask(channel->num);
 331         else
 332                 reg &= ~idma_mask(channel->num);
 333         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 334
 335         __ipu_idmac_reset_current_buffer(channel);
 336
 337         spin_unlock_irqrestore(&ipu->lock, flags);
 338 }
 339 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 340
 341 static const struct {
 342         int chnum;
 343         u32 reg;
 344         int shift;
 345 } idmac_lock_en_info[] = {
 346         { .chnum =  5, .reg = IDMAC_CH_LOCK_EN_1, .shift =  0, },
 347         { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift =  2, },
 348         { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift =  4, },
 349         { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift =  6, },
 350         { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift =  8, },
 351         { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
 352         { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
 353         { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
 354         { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
 355         { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
 356         { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
 357         { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift =  0, },
 358         { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift =  2, },
 359         { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift =  4, },
 360         { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift =  6, },
 361         { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift =  8, },
 362         { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
 363 };
 364
 365 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
 366 {
 367         struct ipu_soc *ipu = channel->ipu;
 368         unsigned long flags;
 369         u32 bursts, regval;
 370         int i;
 371
 372         switch (num_bursts) {
 373         case 0:
 374         case 1:
 375                 bursts = 0x00; /* locking disabled */
 376                 break;
 377         case 2:
 378                 bursts = 0x01;
 379                 break;
 380         case 4:
 381                 bursts = 0x02;
 382                 break;
 383         case 8:
 384                 bursts = 0x03;
 385                 break;
 386         default:
 387                 return -EINVAL;
 388         }
 389
 390         for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
 391                 if (channel->num == idmac_lock_en_info[i].chnum)
 392                         break;
 393         }
 394         if (i >= ARRAY_SIZE(idmac_lock_en_info))
 395                 return -EINVAL;
 396
 397         spin_lock_irqsave(&ipu->lock, flags);
 398
 399         regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
 400         regval &= ~(0x03 << idmac_lock_en_info[i].shift);
 401         regval |= (bursts << idmac_lock_en_info[i].shift);
 402         ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
 403
 404         spin_unlock_irqrestore(&ipu->lock, flags);
 405
 406         return 0;
 407 }
 408 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
 409
 410 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 411 {
 412         unsigned long lock_flags;
 413         u32 val;
 414
 415         spin_lock_irqsave(&ipu->lock, lock_flags);
 416
 417         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 418
 419         if (mask & IPU_CONF_DI0_EN)
 420                 val |= IPU_DI0_COUNTER_RELEASE;
 421         if (mask & IPU_CONF_DI1_EN)
 422                 val |= IPU_DI1_COUNTER_RELEASE;
 423
 424         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 425
 426         val = ipu_cm_read(ipu, IPU_CONF);
 427         val |= mask;
 428         ipu_cm_write(ipu, val, IPU_CONF);
 429
 430         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 431
 432         return 0;
 433 }
 434 EXPORT_SYMBOL_GPL(ipu_module_enable);
 435
 436 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 437 {
 438         unsigned long lock_flags;
 439         u32 val;
 440
 441         spin_lock_irqsave(&ipu->lock, lock_flags);
 442
 443         val = ipu_cm_read(ipu, IPU_CONF);
 444         val &= ~mask;
 445         ipu_cm_write(ipu, val, IPU_CONF);
 446
 447         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 448
 449         if (mask & IPU_CONF_DI0_EN)
 450                 val &= ~IPU_DI0_COUNTER_RELEASE;
 451         if (mask & IPU_CONF_DI1_EN)
 452                 val &= ~IPU_DI1_COUNTER_RELEASE;
 453
 454         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 455
 456         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 457
 458         return 0;
 459 }
 460 EXPORT_SYMBOL_GPL(ipu_module_disable);
 461
 462 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 463 {
 464         struct ipu_soc *ipu = channel->ipu;
 465         unsigned int chno = channel->num;
 466
 467         return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
 468 }
 469 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 470
 471 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
 472 {
 473         struct ipu_soc *ipu = channel->ipu;
 474         unsigned long flags;
 475         u32 reg = 0;
 476
 477         spin_lock_irqsave(&ipu->lock, flags);
 478         switch (buf_num) {
 479         case 0:
 480                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
 481                 break;
 482         case 1:
 483                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
 484                 break;
 485         case 2:
 486                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
 487                 break;
 488         }
 489         spin_unlock_irqrestore(&ipu->lock, flags);
 490
 491         return ((reg & idma_mask(channel->num)) != 0);
 492 }
 493 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
 494
 495 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 496 {
 497         struct ipu_soc *ipu = channel->ipu;
 498         unsigned int chno = channel->num;
 499         unsigned long flags;
 500
 501         spin_lock_irqsave(&ipu->lock, flags);
 502
 503         /* Mark buffer as ready. */
 504         if (buf_num == 0)
 505                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 506         else
 507                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 508
 509         spin_unlock_irqrestore(&ipu->lock, flags);
 510 }
 511 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 512
 513 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
 514 {
 515         struct ipu_soc *ipu = channel->ipu;
 516         unsigned int chno = channel->num;
 517         unsigned long flags;
 518
 519         spin_lock_irqsave(&ipu->lock, flags);
 520
 521         ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
 522         switch (buf_num) {
 523         case 0:
 524                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 525                 break;
 526         case 1:
 527                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 528                 break;
 529         case 2:
 530                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
 531                 break;
 532         default:
 533                 break;
 534         }
 535         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 536
 537         spin_unlock_irqrestore(&ipu->lock, flags);
 538 }
 539 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
 540
 541 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 542 {
 543         struct ipu_soc *ipu = channel->ipu;
 544         u32 val;
 545         unsigned long flags;
 546
 547         spin_lock_irqsave(&ipu->lock, flags);
 548
 549         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 550         val |= idma_mask(channel->num);
 551         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 552
 553         spin_unlock_irqrestore(&ipu->lock, flags);
 554
 555         return 0;
 556 }
 557 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 558
 559 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
 560 {
 561         return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
 562 }
 563 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
 564
 565 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 566 {
 567         struct ipu_soc *ipu = channel->ipu;
 568         unsigned long timeout;
 569
 570         timeout = jiffies + msecs_to_jiffies(ms);
 571         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 572                         idma_mask(channel->num)) {
 573                 if (time_after(jiffies, timeout))
 574                         return -ETIMEDOUT;
 575                 cpu_relax();
 576         }
 577
 578         return 0;
 579 }
 580 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 581
 582 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 583 {
 584         unsigned long timeout;
 585
 586         timeout = jiffies + msecs_to_jiffies(ms);
 587         ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
 588         while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 589                 if (time_after(jiffies, timeout))
 590                         return -ETIMEDOUT;
 591                 cpu_relax();
 592         }
 593
 594         return 0;
 595 }
 596 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
 597
 598 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 599 {
 600         struct ipu_soc *ipu = channel->ipu;
 601         u32 val;
 602         unsigned long flags;
 603
 604         spin_lock_irqsave(&ipu->lock, flags);
 605
 606         /* Disable DMA channel(s) */
 607         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 608         val &= ~idma_mask(channel->num);
 609         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 610
 611         __ipu_idmac_reset_current_buffer(channel);
 612
 613         /* Set channel buffers NOT to be ready */
 614         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 615
 616         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 617                         idma_mask(channel->num)) {
 618                 ipu_cm_write(ipu, idma_mask(channel->num),
 619                              IPU_CHA_BUF0_RDY(channel->num));
 620         }
 621
 622         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 623                         idma_mask(channel->num)) {
 624                 ipu_cm_write(ipu, idma_mask(channel->num),
 625                              IPU_CHA_BUF1_RDY(channel->num));
 626         }
 627
 628         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 629
 630         /* Reset the double buffer */
 631         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 632         val &= ~idma_mask(channel->num);
 633         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 634
 635         spin_unlock_irqrestore(&ipu->lock, flags);
 636
 637         return 0;
 638 }
 639 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 640
 641 /*
 642  * The imx6 rev. D TRM says that enabling the WM feature will increase
 643  * a channel's priority. Refer to Table 36-8 Calculated priority value.
 644  * The sub-module that is the sink or source for the channel must enable
 645  * watermark signal for this to take effect (SMFC_WM for instance).
 646  */
 647 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
 648 {
 649         struct ipu_soc *ipu = channel->ipu;
 650         unsigned long flags;
 651         u32 val;
 652
 653         spin_lock_irqsave(&ipu->lock, flags);
 654
 655         val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
 656         if (enable)
 657                 val |= 1 << (channel->num % 32);
 658         else
 659                 val &= ~(1 << (channel->num % 32));
 660         ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
 661
 662         spin_unlock_irqrestore(&ipu->lock, flags);
 663 }
 664 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
 665
 666 static int ipu_memory_reset(struct ipu_soc *ipu)
 667 {
 668         unsigned long timeout;
 669
 670         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 671
 672         timeout = jiffies + msecs_to_jiffies(1000);
 673         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 674                 if (time_after(jiffies, timeout))
 675                         return -ETIME;
 676                 cpu_relax();
 677         }
 678
 679         return 0;
 680 }
 681
 682 /*
 683  * Set the source mux for the given CSI. Selects either parallel or
 684  * MIPI CSI2 sources.
 685  */
 686 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
 687 {
 688         unsigned long flags;
 689         u32 val, mask;
 690
 691         mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
 692                 IPU_CONF_CSI0_DATA_SOURCE;
 693
 694         spin_lock_irqsave(&ipu->lock, flags);
 695
 696         val = ipu_cm_read(ipu, IPU_CONF);
 697         if (mipi_csi2)
 698                 val |= mask;
 699         else
 700                 val &= ~mask;
 701         ipu_cm_write(ipu, val, IPU_CONF);
 702
 703         spin_unlock_irqrestore(&ipu->lock, flags);
 704 }
 705 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
 706
 707 /*
 708  * Set the source mux for the IC. Selects either CSI[01] or the VDI.
 709  */
 710 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 711 {
 712         unsigned long flags;
 713         u32 val;
 714
 715         spin_lock_irqsave(&ipu->lock, flags);
 716
 717         val = ipu_cm_read(ipu, IPU_CONF);
 718         if (vdi) {
 719                 val |= IPU_CONF_IC_INPUT;
 720         } else {
 721                 val &= ~IPU_CONF_IC_INPUT;
 722                 if (csi_id == 1)
 723                         val |= IPU_CONF_CSI_SEL;
 724                 else
 725                         val &= ~IPU_CONF_CSI_SEL;
 726         }
 727         ipu_cm_write(ipu, val, IPU_CONF);
 728
 729         spin_unlock_irqrestore(&ipu->lock, flags);
 730 }
 731 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 732
 733
 734 /* Frame Synchronization Unit Channel Linking */
 735
 736 struct fsu_link_reg_info {
 737         int chno;
 738         u32 reg;
 739         u32 mask;
 740         u32 val;
 741 };
 742
 743 struct fsu_link_info {
 744         struct fsu_link_reg_info src;
 745         struct fsu_link_reg_info sink;
 746 };
 747
 748 static const struct fsu_link_info fsu_link_info[] = {
 749         {
 750                 .src  = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
 751                           FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
 752                 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
 753                           FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
 754         }, {
 755                 .src =  { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
 756                           FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
 757                 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
 758                           FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
 759         }, {
 760                 .src =  { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
 761                           FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
 762                 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
 763                           FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
 764         }, {
 765                 .src =  { IPUV3_CHANNEL_CSI_DIRECT, 0 },
 766                 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
 767                           FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
 768         },
 769 };
 770
 771 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
 772 {
 773         int i;
 774
 775         for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
 776                 if (src == fsu_link_info[i].src.chno &&
 777                     sink == fsu_link_info[i].sink.chno)
 778                         return &fsu_link_info[i];
 779         }
 780
 781         return NULL;
 782 }
 783
 784 /*
 785  * Links a source channel to a sink channel in the FSU.
 786  */
 787 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
 788 {
 789         const struct fsu_link_info *link;
 790         u32 src_reg, sink_reg;
 791         unsigned long flags;
 792
 793         link = find_fsu_link_info(src_ch, sink_ch);
 794         if (!link)
 795                 return -EINVAL;
 796
 797         spin_lock_irqsave(&ipu->lock, flags);
 798
 799         if (link->src.mask) {
 800                 src_reg = ipu_cm_read(ipu, link->src.reg);
 801                 src_reg &= ~link->src.mask;
 802                 src_reg |= link->src.val;
 803                 ipu_cm_write(ipu, src_reg, link->src.reg);
 804         }
 805
 806         if (link->sink.mask) {
 807                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 808                 sink_reg &= ~link->sink.mask;
 809                 sink_reg |= link->sink.val;
 810                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 811         }
 812
 813         spin_unlock_irqrestore(&ipu->lock, flags);
 814         return 0;
 815 }
 816 EXPORT_SYMBOL_GPL(ipu_fsu_link);
 817
 818 /*
 819  * Unlinks source and sink channels in the FSU.
 820  */
 821 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
 822 {
 823         const struct fsu_link_info *link;
 824         u32 src_reg, sink_reg;
 825         unsigned long flags;
 826
 827         link = find_fsu_link_info(src_ch, sink_ch);
 828         if (!link)
 829                 return -EINVAL;
 830
 831         spin_lock_irqsave(&ipu->lock, flags);
 832
 833         if (link->src.mask) {
 834                 src_reg = ipu_cm_read(ipu, link->src.reg);
 835                 src_reg &= ~link->src.mask;
 836                 ipu_cm_write(ipu, src_reg, link->src.reg);
 837         }
 838
 839         if (link->sink.mask) {
 840                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 841                 sink_reg &= ~link->sink.mask;
 842                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 843         }
 844
 845         spin_unlock_irqrestore(&ipu->lock, flags);
 846         return 0;
 847 }
 848 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
 849
 850 /* Link IDMAC channels in the FSU */
 851 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 852 {
 853         return ipu_fsu_link(src->ipu, src->num, sink->num);
 854 }
 855 EXPORT_SYMBOL_GPL(ipu_idmac_link);
 856
 857 /* Unlink IDMAC channels in the FSU */
 858 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 859 {
 860         return ipu_fsu_unlink(src->ipu, src->num, sink->num);
 861 }
 862 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
 863
 864 struct ipu_devtype {
 865         const char *name;
 866         unsigned long cm_ofs;
 867         unsigned long cpmem_ofs;
 868         unsigned long srm_ofs;
 869         unsigned long tpm_ofs;
 870         unsigned long csi0_ofs;
 871         unsigned long csi1_ofs;
 872         unsigned long ic_ofs;
 873         unsigned long disp0_ofs;
 874         unsigned long disp1_ofs;
 875         unsigned long dc_tmpl_ofs;
 876         unsigned long vdi_ofs;
 877         enum ipuv3_type type;
 878 };
 879
 880 static struct ipu_devtype ipu_type_imx51 = {
 881         .name = "IPUv3EX",
 882         .cm_ofs = 0x1e000000,
 883         .cpmem_ofs = 0x1f000000,
 884         .srm_ofs = 0x1f040000,
 885         .tpm_ofs = 0x1f060000,
 886         .csi0_ofs = 0x1f030000,
 887         .csi1_ofs = 0x1f038000,
 888         .ic_ofs = 0x1e020000,
 889         .disp0_ofs = 0x1e040000,
 890         .disp1_ofs = 0x1e048000,
 891         .dc_tmpl_ofs = 0x1f080000,
 892         .vdi_ofs = 0x1e068000,
 893         .type = IPUV3EX,
 894 };
 895
 896 static struct ipu_devtype ipu_type_imx53 = {
 897         .name = "IPUv3M",
 898         .cm_ofs = 0x06000000,
 899         .cpmem_ofs = 0x07000000,
 900         .srm_ofs = 0x07040000,
 901         .tpm_ofs = 0x07060000,
 902         .csi0_ofs = 0x07030000,
 903         .csi1_ofs = 0x07038000,
 904         .ic_ofs = 0x06020000,
 905         .disp0_ofs = 0x06040000,
 906         .disp1_ofs = 0x06048000,
 907         .dc_tmpl_ofs = 0x07080000,
 908         .vdi_ofs = 0x06068000,
 909         .type = IPUV3M,
 910 };
 911
 912 static struct ipu_devtype ipu_type_imx6q = {
 913         .name = "IPUv3H",
 914         .cm_ofs = 0x00200000,
 915         .cpmem_ofs = 0x00300000,
 916         .srm_ofs = 0x00340000,
 917         .tpm_ofs = 0x00360000,
 918         .csi0_ofs = 0x00230000,
 919         .csi1_ofs = 0x00238000,
 920         .ic_ofs = 0x00220000,
 921         .disp0_ofs = 0x00240000,
 922         .disp1_ofs = 0x00248000,
 923         .dc_tmpl_ofs = 0x00380000,
 924         .vdi_ofs = 0x00268000,
 925         .type = IPUV3H,
 926 };
 927
 928 static const struct of_device_id imx_ipu_dt_ids[] = {
 929         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 930         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 931         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 932         { /* sentinel */ }
 933 };
 934 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 935
 936 static int ipu_submodules_init(struct ipu_soc *ipu,
 937                 struct platform_device *pdev, unsigned long ipu_base,
 938                 struct clk *ipu_clk)
 939 {
 940         char *unit;
 941         int ret;
 942         struct device *dev = &pdev->dev;
 943         const struct ipu_devtype *devtype = ipu->devtype;
 944
 945         ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
 946         if (ret) {
 947                 unit = "cpmem";
 948                 goto err_cpmem;
 949         }
 950
 951         ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
 952                            IPU_CONF_CSI0_EN, ipu_clk);
 953         if (ret) {
 954                 unit = "csi0";
 955                 goto err_csi_0;
 956         }
 957
 958         ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
 959                            IPU_CONF_CSI1_EN, ipu_clk);
 960         if (ret) {
 961                 unit = "csi1";
 962                 goto err_csi_1;
 963         }
 964
 965         ret = ipu_ic_init(ipu, dev,
 966                           ipu_base + devtype->ic_ofs,
 967                           ipu_base + devtype->tpm_ofs);
 968         if (ret) {
 969                 unit = "ic";
 970                 goto err_ic;
 971         }
 972
 973         ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
 974                            IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
 975                            IPU_CONF_IC_INPUT);
 976         if (ret) {
 977                 unit = "vdi";
 978                 goto err_vdi;
 979         }
 980
 981         ret = ipu_image_convert_init(ipu, dev);
 982         if (ret) {
 983                 unit = "image_convert";
 984                 goto err_image_convert;
 985         }
 986
 987         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 988                           IPU_CONF_DI0_EN, ipu_clk);
 989         if (ret) {
 990                 unit = "di0";
 991                 goto err_di_0;
 992         }
 993
 994         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 995                         IPU_CONF_DI1_EN, ipu_clk);
 996         if (ret) {
 997                 unit = "di1";
 998                 goto err_di_1;
 999         }
1000
1001         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1002                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1003         if (ret) {
1004                 unit = "dc_template";
1005                 goto err_dc;
1006         }
1007
1008         ret = ipu_dmfc_init(ipu, dev, ipu_base +
1009                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1010         if (ret) {
1011                 unit = "dmfc";
1012                 goto err_dmfc;
1013         }
1014
1015         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1016         if (ret) {
1017                 unit = "dp";
1018                 goto err_dp;
1019         }
1020
1021         ret = ipu_smfc_init(ipu, dev, ipu_base +
1022                         devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1023         if (ret) {
1024                 unit = "smfc";
1025                 goto err_smfc;
1026         }
1027
1028         return 0;
1029
1030 err_smfc:
1031         ipu_dp_exit(ipu);
1032 err_dp:
1033         ipu_dmfc_exit(ipu);
1034 err_dmfc:
1035         ipu_dc_exit(ipu);
1036 err_dc:
1037         ipu_di_exit(ipu, 1);
1038 err_di_1:
1039         ipu_di_exit(ipu, 0);
1040 err_di_0:
1041         ipu_image_convert_exit(ipu);
1042 err_image_convert:
1043         ipu_vdi_exit(ipu);
1044 err_vdi:
1045         ipu_ic_exit(ipu);
1046 err_ic:
1047         ipu_csi_exit(ipu, 1);
1048 err_csi_1:
1049         ipu_csi_exit(ipu, 0);
1050 err_csi_0:
1051         ipu_cpmem_exit(ipu);
1052 err_cpmem:
1053         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1054         return ret;
1055 }
1056
1057 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1058 {
1059         unsigned long status;
1060         int i, bit, irq;
1061
1062         for (i = 0; i < num_regs; i++) {
1063
1064                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1065                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1066
1067                 for_each_set_bit(bit, &status, 32) {
1068                         irq = irq_linear_revmap(ipu->domain,
1069                                                 regs[i] * 32 + bit);
1070                         if (irq)
1071                                 generic_handle_irq(irq);
1072                 }
1073         }
1074 }
1075
1076 static void ipu_irq_handler(struct irq_desc *desc)
1077 {
1078         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1079         struct irq_chip *chip = irq_desc_get_chip(desc);
1080         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1081
1082         chained_irq_enter(chip, desc);
1083
1084         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1085
1086         chained_irq_exit(chip, desc);
1087 }
1088
1089 static void ipu_err_irq_handler(struct irq_desc *desc)
1090 {
1091         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1092         struct irq_chip *chip = irq_desc_get_chip(desc);
1093         const int int_reg[] = { 4, 5, 8, 9};
1094
1095         chained_irq_enter(chip, desc);
1096
1097         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1098
1099         chained_irq_exit(chip, desc);
1100 }
1101
1102 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1103 {
1104         int virq;
1105
1106         virq = irq_linear_revmap(ipu->domain, irq);
1107         if (!virq)
1108                 virq = irq_create_mapping(ipu->domain, irq);
1109
1110         return virq;
1111 }
1112 EXPORT_SYMBOL_GPL(ipu_map_irq);
1113
1114 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1115                 enum ipu_channel_irq irq_type)
1116 {
1117         return ipu_map_irq(ipu, irq_type + channel->num);
1118 }
1119 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1120
1121 static void ipu_submodules_exit(struct ipu_soc *ipu)
1122 {
1123         ipu_smfc_exit(ipu);
1124         ipu_dp_exit(ipu);
1125         ipu_dmfc_exit(ipu);
1126         ipu_dc_exit(ipu);
1127         ipu_di_exit(ipu, 1);
1128         ipu_di_exit(ipu, 0);
1129         ipu_image_convert_exit(ipu);
1130         ipu_vdi_exit(ipu);
1131         ipu_ic_exit(ipu);
1132         ipu_csi_exit(ipu, 1);
1133         ipu_csi_exit(ipu, 0);
1134         ipu_cpmem_exit(ipu);
1135 }
1136
1137 static int platform_remove_devices_fn(struct device *dev, void *unused)
1138 {
1139         struct platform_device *pdev = to_platform_device(dev);
1140
1141         platform_device_unregister(pdev);
1142
1143         return 0;
1144 }
1145
1146 static void platform_device_unregister_children(struct platform_device *pdev)
1147 {
1148         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1149 }
1150
1151 struct ipu_platform_reg {
1152         struct ipu_client_platformdata pdata;
1153         const char *name;
1154 };
1155
1156 /* These must be in the order of the corresponding device tree port nodes */
1157 static struct ipu_platform_reg client_reg[] = {
1158         {
1159                 .pdata = {
1160                         .csi = 0,
1161                         .dma[0] = IPUV3_CHANNEL_CSI0,
1162                         .dma[1] = -EINVAL,
1163                 },
1164                 .name = "imx-ipuv3-csi",
1165         }, {
1166                 .pdata = {
1167                         .csi = 1,
1168                         .dma[0] = IPUV3_CHANNEL_CSI1,
1169                         .dma[1] = -EINVAL,
1170                 },
1171                 .name = "imx-ipuv3-csi",
1172         }, {
1173                 .pdata = {
1174                         .di = 0,
1175                         .dc = 5,
1176                         .dp = IPU_DP_FLOW_SYNC_BG,
1177                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1178                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1179                 },
1180                 .name = "imx-ipuv3-crtc",
1181         }, {
1182                 .pdata = {
1183                         .di = 1,
1184                         .dc = 1,
1185                         .dp = -EINVAL,
1186                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1187                         .dma[1] = -EINVAL,
1188                 },
1189                 .name = "imx-ipuv3-crtc",
1190         },
1191 };
1192
1193 static DEFINE_MUTEX(ipu_client_id_mutex);
1194 static int ipu_client_id;
1195
1196 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1197 {
1198         struct device *dev = ipu->dev;
1199         unsigned i;
1200         int id, ret;
1201
1202         mutex_lock(&ipu_client_id_mutex);
1203         id = ipu_client_id;
1204         ipu_client_id += ARRAY_SIZE(client_reg);
1205         mutex_unlock(&ipu_client_id_mutex);
1206
1207         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1208                 struct ipu_platform_reg *reg = &client_reg[i];
1209                 struct platform_device *pdev;
1210                 struct device_node *of_node;
1211
1212                 /* Associate subdevice with the corresponding port node */
1213                 of_node = of_graph_get_port_by_id(dev->of_node, i);
1214                 if (!of_node) {
1215                         dev_info(dev,
1216                                  "no port@%d node in %s, not using %s%d\n",
1217                                  i, dev->of_node->full_name,
1218                                  (i / 2) ? "DI" : "CSI", i % 2);
1219                         continue;
1220                 }
1221
1222                 pdev = platform_device_alloc(reg->name, id++);
1223                 if (!pdev) {
1224                         ret = -ENOMEM;
1225                         goto err_register;
1226                 }
1227
1228                 pdev->dev.parent = dev;
1229
1230                 reg->pdata.of_node = of_node;
1231                 ret = platform_device_add_data(pdev, &reg->pdata,
1232                                                sizeof(reg->pdata));
1233                 if (!ret)
1234                         ret = platform_device_add(pdev);
1235                 if (ret) {
1236                         platform_device_put(pdev);
1237                         goto err_register;
1238                 }
1239
1240                 /*
1241                  * Set of_node only after calling platform_device_add. Otherwise
1242                  * the platform:imx-ipuv3-crtc modalias won't be used.
1243                  */
1244                 pdev->dev.of_node = of_node;
1245         }
1246
1247         return 0;
1248
1249 err_register:
1250         platform_device_unregister_children(to_platform_device(dev));
1251
1252         return ret;
1253 }
1254
1255
1256 static int ipu_irq_init(struct ipu_soc *ipu)
1257 {
1258         struct irq_chip_generic *gc;
1259         struct irq_chip_type *ct;
1260         unsigned long unused[IPU_NUM_IRQS / 32] = {
1261                 0x400100d0, 0xffe000fd,
1262                 0x400100d0, 0xffe000fd,
1263                 0x400100d0, 0xffe000fd,
1264                 0x4077ffff, 0xffe7e1fd,
1265                 0x23fffffe, 0x8880fff0,
1266                 0xf98fe7d0, 0xfff81fff,
1267                 0x400100d0, 0xffe000fd,
1268                 0x00000000,
1269         };
1270         int ret, i;
1271
1272         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1273                                             &irq_generic_chip_ops, ipu);
1274         if (!ipu->domain) {
1275                 dev_err(ipu->dev, "failed to add irq domain\n");
1276                 return -ENODEV;
1277         }
1278
1279         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1280                                              handle_level_irq, 0, 0, 0);
1281         if (ret < 0) {
1282                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1283                 irq_domain_remove(ipu->domain);
1284                 return ret;
1285         }
1286
1287         for (i = 0; i < IPU_NUM_IRQS; i += 32)
1288                 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1289
1290         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1291                 gc = irq_get_domain_generic_chip(ipu->domain, i);
1292                 gc->reg_base = ipu->cm_reg;
1293                 gc->unused = unused[i / 32];
1294                 ct = gc->chip_types;
1295                 ct->chip.irq_ack = irq_gc_ack_set_bit;
1296                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1297                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1298                 ct->regs.ack = IPU_INT_STAT(i / 32);
1299                 ct->regs.mask = IPU_INT_CTRL(i / 32);
1300         }
1301
1302         irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1303         irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1304                                          ipu);
1305
1306         return 0;
1307 }
1308
1309 static void ipu_irq_exit(struct ipu_soc *ipu)
1310 {
1311         int i, irq;
1312
1313         irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1314         irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1315
1316         /* TODO: remove irq_domain_generic_chips */
1317
1318         for (i = 0; i < IPU_NUM_IRQS; i++) {
1319                 irq = irq_linear_revmap(ipu->domain, i);
1320                 if (irq)
1321                         irq_dispose_mapping(irq);
1322         }
1323
1324         irq_domain_remove(ipu->domain);
1325 }
1326
1327 void ipu_dump(struct ipu_soc *ipu)
1328 {
1329         int i;
1330
1331         dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1332                 ipu_cm_read(ipu, IPU_CONF));
1333         dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1334                 ipu_idmac_read(ipu, IDMAC_CONF));
1335         dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1336                 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1337         dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1338                 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1339         dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1340                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1341         dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1342                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1343         dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1344                 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1345         dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1346                 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1347         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1348                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1349         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1350                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1351         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1352                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1353         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1354                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1355         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1356                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1357         dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1358                 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1359         for (i = 0; i < 15; i++)
1360                 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1361                         ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1362 }
1363 EXPORT_SYMBOL_GPL(ipu_dump);
1364
1365 static int ipu_probe(struct platform_device *pdev)
1366 {
1367         struct device_node *np = pdev->dev.of_node;
1368         struct ipu_soc *ipu;
1369         struct resource *res;
1370         unsigned long ipu_base;
1371         int i, ret, irq_sync, irq_err;
1372         const struct ipu_devtype *devtype;
1373
1374         devtype = of_device_get_match_data(&pdev->dev);
1375         if (!devtype)
1376                 return -EINVAL;
1377
1378         irq_sync = platform_get_irq(pdev, 0);
1379         irq_err = platform_get_irq(pdev, 1);
1380         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1381
1382         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1383                         irq_sync, irq_err);
1384
1385         if (!res || irq_sync < 0 || irq_err < 0)
1386                 return -ENODEV;
1387
1388         ipu_base = res->start;
1389
1390         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1391         if (!ipu)
1392                 return -ENODEV;
1393
1394         for (i = 0; i < 64; i++)
1395                 ipu->channel[i].ipu = ipu;
1396         ipu->devtype = devtype;
1397         ipu->ipu_type = devtype->type;
1398         ipu->id = of_alias_get_id(np, "ipu");
1399
1400         spin_lock_init(&ipu->lock);
1401         mutex_init(&ipu->channel_lock);
1402
1403         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
1404                         ipu_base + devtype->cm_ofs);
1405         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
1406                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1407         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
1408                         ipu_base + devtype->cpmem_ofs);
1409         dev_dbg(&pdev->dev, "csi0:    0x%08lx\n",
1410                         ipu_base + devtype->csi0_ofs);
1411         dev_dbg(&pdev->dev, "csi1:    0x%08lx\n",
1412                         ipu_base + devtype->csi1_ofs);
1413         dev_dbg(&pdev->dev, "ic:      0x%08lx\n",
1414                         ipu_base + devtype->ic_ofs);
1415         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1416                         ipu_base + devtype->disp0_ofs);
1417         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1418                         ipu_base + devtype->disp1_ofs);
1419         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1420                         ipu_base + devtype->srm_ofs);
1421         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1422                         ipu_base + devtype->tpm_ofs);
1423         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1424                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1425         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1426                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1427         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1428                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1429         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1430                         ipu_base + devtype->vdi_ofs);
1431
1432         ipu->cm_reg = devm_ioremap(&pdev->dev,
1433                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1434         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1435                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1436                         PAGE_SIZE);
1437
1438         if (!ipu->cm_reg || !ipu->idmac_reg)
1439                 return -ENOMEM;
1440
1441         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1442         if (IS_ERR(ipu->clk)) {
1443                 ret = PTR_ERR(ipu->clk);
1444                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1445                 return ret;
1446         }
1447
1448         platform_set_drvdata(pdev, ipu);
1449
1450         ret = clk_prepare_enable(ipu->clk);
1451         if (ret) {
1452                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1453                 return ret;
1454         }
1455
1456         ipu->dev = &pdev->dev;
1457         ipu->irq_sync = irq_sync;
1458         ipu->irq_err = irq_err;
1459
1460         ret = device_reset(&pdev->dev);
1461         if (ret) {
1462                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1463                 goto out_failed_reset;
1464         }
1465         ret = ipu_memory_reset(ipu);
1466         if (ret)
1467                 goto out_failed_reset;
1468
1469         ret = ipu_irq_init(ipu);
1470         if (ret)
1471                 goto out_failed_irq;
1472
1473         /* Set MCU_T to divide MCU access window into 2 */
1474         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1475                         IPU_DISP_GEN);
1476
1477         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1478         if (ret)
1479                 goto failed_submodules_init;
1480
1481         ret = ipu_add_client_devices(ipu, ipu_base);
1482         if (ret) {
1483                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1484                                 ret);
1485                 goto failed_add_clients;
1486         }
1487
1488         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1489
1490         return 0;
1491
1492 failed_add_clients:
1493         ipu_submodules_exit(ipu);
1494 failed_submodules_init:
1495         ipu_irq_exit(ipu);
1496 out_failed_irq:
1497 out_failed_reset:
1498         clk_disable_unprepare(ipu->clk);
1499         return ret;
1500 }
1501
1502 static int ipu_remove(struct platform_device *pdev)
1503 {
1504         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1505
1506         platform_device_unregister_children(pdev);
1507         ipu_submodules_exit(ipu);
1508         ipu_irq_exit(ipu);
1509
1510         clk_disable_unprepare(ipu->clk);
1511
1512         return 0;
1513 }
1514
1515 static struct platform_driver imx_ipu_driver = {
1516         .driver = {
1517                 .name = "imx-ipuv3",
1518                 .of_match_table = imx_ipu_dt_ids,
1519         },
1520         .probe = ipu_probe,
1521         .remove = ipu_remove,
1522 };
1523
1524 module_platform_driver(imx_ipu_driver);
1525
1526 MODULE_ALIAS("platform:imx-ipuv3");
1527 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1528 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1529 MODULE_LICENSE("GPL");