1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
9 #include <linux/dma-mapping.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
15 #include <linux/slab.h>
17 #define CREATE_TRACE_POINTS
18 #include <trace/events/host1x.h>
19 #undef CREATE_TRACE_POINTS
21 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
22 #include <asm/dma-iommu.h>
31 #include "hw/host1x01.h"
32 #include "hw/host1x02.h"
33 #include "hw/host1x04.h"
34 #include "hw/host1x05.h"
35 #include "hw/host1x06.h"
36 #include "hw/host1x07.h"
38 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
40 writel(v, host1x->hv_regs + r);
43 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
45 return readl(host1x->hv_regs + r);
48 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
50 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
52 writel(v, sync_regs + r);
55 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
57 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
59 return readl(sync_regs + r);
62 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
64 writel(v, ch->regs + r);
67 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
69 return readl(ch->regs + r);
72 static const struct host1x_info host1x01_info = {
77 .init = host1x01_init,
78 .sync_offset = 0x3000,
79 .dma_mask = DMA_BIT_MASK(32),
80 .has_wide_gather = false,
81 .has_hypervisor = false,
86 static const struct host1x_info host1x02_info = {
91 .init = host1x02_init,
92 .sync_offset = 0x3000,
93 .dma_mask = DMA_BIT_MASK(32),
94 .has_wide_gather = false,
95 .has_hypervisor = false,
100 static const struct host1x_info host1x04_info = {
105 .init = host1x04_init,
106 .sync_offset = 0x2100,
107 .dma_mask = DMA_BIT_MASK(34),
108 .has_wide_gather = false,
109 .has_hypervisor = false,
110 .num_sid_entries = 0,
114 static const struct host1x_info host1x05_info = {
119 .init = host1x05_init,
120 .sync_offset = 0x2100,
121 .dma_mask = DMA_BIT_MASK(34),
122 .has_wide_gather = false,
123 .has_hypervisor = false,
124 .num_sid_entries = 0,
128 static const struct host1x_sid_entry tegra186_sid_table[] = {
137 static const struct host1x_info host1x06_info = {
142 .init = host1x06_init,
144 .dma_mask = DMA_BIT_MASK(40),
145 .has_wide_gather = true,
146 .has_hypervisor = true,
147 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
148 .sid_table = tegra186_sid_table,
151 static const struct host1x_sid_entry tegra194_sid_table[] = {
160 static const struct host1x_info host1x07_info = {
165 .init = host1x07_init,
167 .dma_mask = DMA_BIT_MASK(40),
168 .has_wide_gather = true,
169 .has_hypervisor = true,
170 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
171 .sid_table = tegra194_sid_table,
174 static const struct of_device_id host1x_of_match[] = {
175 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
176 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
177 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
178 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
179 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
180 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
181 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
184 MODULE_DEVICE_TABLE(of, host1x_of_match);
186 static void host1x_setup_sid_table(struct host1x *host)
188 const struct host1x_info *info = host->info;
191 for (i = 0; i < info->num_sid_entries; i++) {
192 const struct host1x_sid_entry *entry = &info->sid_table[i];
194 host1x_hypervisor_writel(host, entry->offset, entry->base);
195 host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
199 static bool host1x_wants_iommu(struct host1x *host1x)
202 * If we support addressing a maximum of 32 bits of physical memory
203 * and if the host1x firewall is enabled, there's no need to enable
204 * IOMMU support. This can happen for example on Tegra20, Tegra30
207 * Tegra124 and later can address up to 34 bits of physical memory and
208 * many platforms come equipped with more than 2 GiB of system memory,
209 * which requires crossing the 4 GiB boundary. But there's a catch: on
210 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
211 * only address up to 32 bits of memory in GATHER opcodes, which means
212 * that command buffers need to either be in the first 2 GiB of system
213 * memory (which could quickly lead to memory exhaustion), or command
214 * buffers need to be treated differently from other buffers (which is
215 * not possible with the current ABI).
217 * A third option is to use the IOMMU in these cases to make sure all
218 * buffers will be mapped into a 32-bit IOVA space that host1x can
219 * address. This allows all of the system memory to be used and works
220 * within the limitations of the host1x on these SoCs.
222 * In summary, default to enable IOMMU on Tegra124 and later. For any
223 * of the earlier SoCs, only use the IOMMU for additional safety when
224 * the host1x firewall is disabled.
226 if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
227 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
234 static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
236 struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
239 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
240 if (host->dev->archdata.mapping) {
241 struct dma_iommu_mapping *mapping =
242 to_dma_iommu_mapping(host->dev);
243 arm_iommu_detach_device(host->dev);
244 arm_iommu_release_mapping(mapping);
246 domain = iommu_get_domain_for_dev(host->dev);
251 * We may not always want to enable IOMMU support (for example if the
252 * host1x firewall is already enabled and we don't support addressing
253 * more than 32 bits of physical memory), so check for that first.
255 * Similarly, if host1x is already attached to an IOMMU (via the DMA
256 * API), don't try to attach again.
258 if (!host1x_wants_iommu(host) || domain)
261 host->group = iommu_group_get(host->dev);
263 struct iommu_domain_geometry *geometry;
264 dma_addr_t start, end;
267 err = iova_cache_get();
271 host->domain = iommu_domain_alloc(&platform_bus_type);
277 err = iommu_attach_group(host->domain, host->group);
285 geometry = &host->domain->geometry;
286 start = geometry->aperture_start & host->info->dma_mask;
287 end = geometry->aperture_end & host->info->dma_mask;
289 order = __ffs(host->domain->pgsize_bitmap);
290 init_iova_domain(&host->iova, 1UL << order, start >> order);
291 host->iova_end = end;
293 domain = host->domain;
299 iommu_domain_free(host->domain);
304 iommu_group_put(host->group);
310 static int host1x_iommu_init(struct host1x *host)
312 u64 mask = host->info->dma_mask;
313 struct iommu_domain *domain;
316 domain = host1x_iommu_attach(host);
317 if (IS_ERR(domain)) {
318 err = PTR_ERR(domain);
319 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
324 * If we're not behind an IOMMU make sure we don't get push buffers
325 * that are allocated outside of the range addressable by the GATHER
328 * Newer generations of Tegra (Tegra186 and later) support a wide
329 * variant of the GATHER opcode that allows addressing more bits.
331 if (!domain && !host->info->has_wide_gather)
332 mask = DMA_BIT_MASK(32);
334 err = dma_coerce_mask_and_coherent(host->dev, mask);
336 dev_err(host->dev, "failed to set DMA mask: %d\n", err);
343 static void host1x_iommu_exit(struct host1x *host)
346 put_iova_domain(&host->iova);
347 iommu_detach_group(host->domain, host->group);
349 iommu_domain_free(host->domain);
354 iommu_group_put(host->group);
359 static int host1x_probe(struct platform_device *pdev)
362 struct resource *regs, *hv_regs = NULL;
366 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
370 host->info = of_device_get_match_data(&pdev->dev);
372 if (host->info->has_hypervisor) {
373 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
375 dev_err(&pdev->dev, "failed to get vm registers\n");
379 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
383 "failed to get hypervisor registers\n");
387 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
389 dev_err(&pdev->dev, "failed to get registers\n");
394 syncpt_irq = platform_get_irq(pdev, 0);
398 mutex_init(&host->devices_lock);
399 INIT_LIST_HEAD(&host->devices);
400 INIT_LIST_HEAD(&host->list);
401 host->dev = &pdev->dev;
403 /* set common host1x device data */
404 platform_set_drvdata(pdev, host);
406 host->regs = devm_ioremap_resource(&pdev->dev, regs);
407 if (IS_ERR(host->regs))
408 return PTR_ERR(host->regs);
410 if (host->info->has_hypervisor) {
411 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
412 if (IS_ERR(host->hv_regs))
413 return PTR_ERR(host->hv_regs);
416 host->dev->dma_parms = &host->dma_parms;
417 dma_set_max_seg_size(host->dev, UINT_MAX);
419 if (host->info->init) {
420 err = host->info->init(host);
425 host->clk = devm_clk_get(&pdev->dev, NULL);
426 if (IS_ERR(host->clk)) {
427 err = PTR_ERR(host->clk);
429 if (err != -EPROBE_DEFER)
430 dev_err(&pdev->dev, "failed to get clock: %d\n", err);
435 host->rst = devm_reset_control_get(&pdev->dev, "host1x");
436 if (IS_ERR(host->rst)) {
437 err = PTR_ERR(host->rst);
438 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
442 err = host1x_iommu_init(host);
444 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
448 err = host1x_channel_list_init(&host->channel_list,
449 host->info->nb_channels);
451 dev_err(&pdev->dev, "failed to initialize channel list\n");
455 err = clk_prepare_enable(host->clk);
457 dev_err(&pdev->dev, "failed to enable clock\n");
461 err = reset_control_deassert(host->rst);
463 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
464 goto unprepare_disable;
467 err = host1x_syncpt_init(host);
469 dev_err(&pdev->dev, "failed to initialize syncpts\n");
473 err = host1x_intr_init(host, syncpt_irq);
475 dev_err(&pdev->dev, "failed to initialize interrupts\n");
479 host1x_debug_init(host);
481 if (host->info->has_hypervisor)
482 host1x_setup_sid_table(host);
484 err = host1x_register(host);
488 err = devm_of_platform_populate(&pdev->dev);
495 host1x_unregister(host);
497 host1x_debug_deinit(host);
498 host1x_intr_deinit(host);
500 host1x_syncpt_deinit(host);
502 reset_control_assert(host->rst);
504 clk_disable_unprepare(host->clk);
506 host1x_channel_list_free(&host->channel_list);
508 host1x_iommu_exit(host);
513 static int host1x_remove(struct platform_device *pdev)
515 struct host1x *host = platform_get_drvdata(pdev);
517 host1x_unregister(host);
518 host1x_debug_deinit(host);
519 host1x_intr_deinit(host);
520 host1x_syncpt_deinit(host);
521 reset_control_assert(host->rst);
522 clk_disable_unprepare(host->clk);
523 host1x_channel_list_free(&host->channel_list);
524 host1x_iommu_exit(host);
529 static struct platform_driver tegra_host1x_driver = {
531 .name = "tegra-host1x",
532 .of_match_table = host1x_of_match,
534 .probe = host1x_probe,
535 .remove = host1x_remove,
538 static struct platform_driver * const drivers[] = {
539 &tegra_host1x_driver,
543 static int __init tegra_host1x_init(void)
547 err = bus_register(&host1x_bus_type);
551 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
553 bus_unregister(&host1x_bus_type);
557 module_init(tegra_host1x_init);
559 static void __exit tegra_host1x_exit(void)
561 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
562 bus_unregister(&host1x_bus_type);
564 module_exit(tegra_host1x_exit);
567 * host1x_get_dma_mask() - query the supported DMA mask for host1x
568 * @host1x: host1x instance
570 * Note that this returns the supported DMA mask for host1x, which can be
571 * different from the applicable DMA mask under certain circumstances.
573 u64 host1x_get_dma_mask(struct host1x *host1x)
575 return host1x->info->dma_mask;
577 EXPORT_SYMBOL(host1x_get_dma_mask);
579 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
580 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
581 MODULE_DESCRIPTION("Host1x driver for Tegra products");
582 MODULE_LICENSE("GPL");