drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /**************************************************************************
   3  *
   4  * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28 #include <linux/console.h>
  29
  30 #include <drm/drmP.h>
  31 #include "vmwgfx_drv.h"
  32 #include "vmwgfx_binding.h"
  33 #include <drm/ttm/ttm_placement.h>
  34 #include <drm/ttm/ttm_bo_driver.h>
  35 #include <drm/ttm/ttm_object.h>
  36 #include <drm/ttm/ttm_module.h>
  37 #include <linux/dma_remapping.h>
  38
  39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  40 #define VMWGFX_CHIP_SVGAII 0
  41 #define VMW_FB_RESERVATION 0
  42
  43 #define VMW_MIN_INITIAL_WIDTH 800
  44 #define VMW_MIN_INITIAL_HEIGHT 600
  45
  46 #ifndef VMWGFX_GIT_VERSION
  47 #define VMWGFX_GIT_VERSION "Unknown"
  48 #endif
  49
  50 #define VMWGFX_REPO "In Tree"
  51
  52
  53 /**
  54  * Fully encoded drm commands. Might move to vmw_drm.h
  55  */
  56
  57 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  58         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  59                  struct drm_vmw_getparam_arg)
  60 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  61         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  62                 union drm_vmw_alloc_dmabuf_arg)
  63 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  65                 struct drm_vmw_unref_dmabuf_arg)
  66 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  67         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  68                  struct drm_vmw_cursor_bypass_arg)
  69
  70 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  71         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  72                  struct drm_vmw_control_stream_arg)
  73 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  75                  struct drm_vmw_stream_arg)
  76 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  78                  struct drm_vmw_stream_arg)
  79
  80 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  81         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  82                 struct drm_vmw_context_arg)
  83 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  84         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  85                 struct drm_vmw_context_arg)
  86 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  87         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  88                  union drm_vmw_surface_create_arg)
  89 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  90         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  91                  struct drm_vmw_surface_arg)
  92 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  93         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  94                  union drm_vmw_surface_reference_arg)
  95 #define DRM_IOCTL_VMW_EXECBUF                                   \
  96         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  97                 struct drm_vmw_execbuf_arg)
  98 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  99         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
 100                  struct drm_vmw_get_3d_cap_arg)
 101 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
 102         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
 103                  struct drm_vmw_fence_wait_arg)
 104 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
 105         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
 106                  struct drm_vmw_fence_signaled_arg)
 107 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 108         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 109                  struct drm_vmw_fence_arg)
 110 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 111         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 112                  struct drm_vmw_fence_event_arg)
 113 #define DRM_IOCTL_VMW_PRESENT                                   \
 114         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 115                  struct drm_vmw_present_arg)
 116 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 117         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 118                  struct drm_vmw_present_readback_arg)
 119 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 120         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 121                  struct drm_vmw_update_layout_arg)
 122 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 123         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 124                  struct drm_vmw_shader_create_arg)
 125 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 126         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 127                  struct drm_vmw_shader_arg)
 128 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 129         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 130                  union drm_vmw_gb_surface_create_arg)
 131 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 132         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 133                  union drm_vmw_gb_surface_reference_arg)
 134 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 135         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 136                  struct drm_vmw_synccpu_arg)
 137 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT                   \
 138         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,    \
 139                 struct drm_vmw_context_arg)
 140 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT                             \
 141         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT,      \
 142                 union drm_vmw_gb_surface_create_ext_arg)
 143 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT                                \
 144         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT,         \
 145                 union drm_vmw_gb_surface_reference_ext_arg)
 146
 147 /**
 148  * The core DRM version of this macro doesn't account for
 149  * DRM_COMMAND_BASE.
 150  */
 151
 152 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 153   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
 154
 155 /**
 156  * Ioctl definitions.
 157  */
 158
 159 static const struct drm_ioctl_desc vmw_ioctls[] = {
 160         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 161                       DRM_AUTH | DRM_RENDER_ALLOW),
 162         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
 163                       DRM_AUTH | DRM_RENDER_ALLOW),
 164         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
 165                       DRM_RENDER_ALLOW),
 166         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 167                       vmw_kms_cursor_bypass_ioctl,
 168                       DRM_MASTER),
 169
 170         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 171                       DRM_MASTER),
 172         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 173                       DRM_MASTER),
 174         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 175                       DRM_MASTER),
 176
 177         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 178                       DRM_AUTH | DRM_RENDER_ALLOW),
 179         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 180                       DRM_RENDER_ALLOW),
 181         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 182                       DRM_AUTH | DRM_RENDER_ALLOW),
 183         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 184                       DRM_RENDER_ALLOW),
 185         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 186                       DRM_AUTH | DRM_RENDER_ALLOW),
 187         VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
 188                       DRM_RENDER_ALLOW),
 189         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 190                       DRM_RENDER_ALLOW),
 191         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 192                       vmw_fence_obj_signaled_ioctl,
 193                       DRM_RENDER_ALLOW),
 194         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 195                       DRM_RENDER_ALLOW),
 196         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
 197                       DRM_AUTH | DRM_RENDER_ALLOW),
 198         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 199                       DRM_AUTH | DRM_RENDER_ALLOW),
 200
 201         /* these allow direct access to the framebuffers mark as master only */
 202         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 203                       DRM_MASTER | DRM_AUTH),
 204         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 205                       vmw_present_readback_ioctl,
 206                       DRM_MASTER | DRM_AUTH),
 207         /*
 208          * The permissions of the below ioctl are overridden in
 209          * vmw_generic_ioctl(). We require either
 210          * DRM_MASTER or capable(CAP_SYS_ADMIN).
 211          */
 212         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 213                       vmw_kms_update_layout_ioctl,
 214                       DRM_RENDER_ALLOW),
 215         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 216                       vmw_shader_define_ioctl,
 217                       DRM_AUTH | DRM_RENDER_ALLOW),
 218         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 219                       vmw_shader_destroy_ioctl,
 220                       DRM_RENDER_ALLOW),
 221         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 222                       vmw_gb_surface_define_ioctl,
 223                       DRM_AUTH | DRM_RENDER_ALLOW),
 224         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 225                       vmw_gb_surface_reference_ioctl,
 226                       DRM_AUTH | DRM_RENDER_ALLOW),
 227         VMW_IOCTL_DEF(VMW_SYNCCPU,
 228                       vmw_user_bo_synccpu_ioctl,
 229                       DRM_RENDER_ALLOW),
 230         VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
 231                       vmw_extended_context_define_ioctl,
 232                       DRM_AUTH | DRM_RENDER_ALLOW),
 233         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
 234                       vmw_gb_surface_define_ext_ioctl,
 235                       DRM_AUTH | DRM_RENDER_ALLOW),
 236         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
 237                       vmw_gb_surface_reference_ext_ioctl,
 238                       DRM_AUTH | DRM_RENDER_ALLOW),
 239 };
 240
 241 static const struct pci_device_id vmw_pci_id_list[] = {
 242         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 243         {0, 0, 0}
 244 };
 245 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 246
 247 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 248 static int vmw_force_iommu;
 249 static int vmw_restrict_iommu;
 250 static int vmw_force_coherent;
 251 static int vmw_restrict_dma_mask;
 252 static int vmw_assume_16bpp;
 253
 254 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 255 static void vmw_master_init(struct vmw_master *);
 256 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 257                               void *ptr);
 258
 259 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 260 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 261 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 262 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 263 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 264 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 265 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 266 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 267 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 268 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 269 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
 270 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
 271
 272
 273 static void vmw_print_capabilities2(uint32_t capabilities2)
 274 {
 275         DRM_INFO("Capabilities2:\n");
 276         if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
 277                 DRM_INFO("  Grow oTable.\n");
 278         if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
 279                 DRM_INFO("  IntraSurface copy.\n");
 280 }
 281
 282 static void vmw_print_capabilities(uint32_t capabilities)
 283 {
 284         DRM_INFO("Capabilities:\n");
 285         if (capabilities & SVGA_CAP_RECT_COPY)
 286                 DRM_INFO("  Rect copy.\n");
 287         if (capabilities & SVGA_CAP_CURSOR)
 288                 DRM_INFO("  Cursor.\n");
 289         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 290                 DRM_INFO("  Cursor bypass.\n");
 291         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 292                 DRM_INFO("  Cursor bypass 2.\n");
 293         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 294                 DRM_INFO("  8bit emulation.\n");
 295         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 296                 DRM_INFO("  Alpha cursor.\n");
 297         if (capabilities & SVGA_CAP_3D)
 298                 DRM_INFO("  3D.\n");
 299         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 300                 DRM_INFO("  Extended Fifo.\n");
 301         if (capabilities & SVGA_CAP_MULTIMON)
 302                 DRM_INFO("  Multimon.\n");
 303         if (capabilities & SVGA_CAP_PITCHLOCK)
 304                 DRM_INFO("  Pitchlock.\n");
 305         if (capabilities & SVGA_CAP_IRQMASK)
 306                 DRM_INFO("  Irq mask.\n");
 307         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 308                 DRM_INFO("  Display Topology.\n");
 309         if (capabilities & SVGA_CAP_GMR)
 310                 DRM_INFO("  GMR.\n");
 311         if (capabilities & SVGA_CAP_TRACES)
 312                 DRM_INFO("  Traces.\n");
 313         if (capabilities & SVGA_CAP_GMR2)
 314                 DRM_INFO("  GMR2.\n");
 315         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 316                 DRM_INFO("  Screen Object 2.\n");
 317         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 318                 DRM_INFO("  Command Buffers.\n");
 319         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 320                 DRM_INFO("  Command Buffers 2.\n");
 321         if (capabilities & SVGA_CAP_GBOBJECTS)
 322                 DRM_INFO("  Guest Backed Resources.\n");
 323         if (capabilities & SVGA_CAP_DX)
 324                 DRM_INFO("  DX Features.\n");
 325         if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
 326                 DRM_INFO("  HP Command Queue.\n");
 327 }
 328
 329 /**
 330  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 331  *
 332  * @dev_priv: A device private structure.
 333  *
 334  * This function creates a small buffer object that holds the query
 335  * result for dummy queries emitted as query barriers.
 336  * The function will then map the first page and initialize a pending
 337  * occlusion query result structure, Finally it will unmap the buffer.
 338  * No interruptible waits are done within this function.
 339  *
 340  * Returns an error if bo creation or initialization fails.
 341  */
 342 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 343 {
 344         int ret;
 345         struct vmw_buffer_object *vbo;
 346         struct ttm_bo_kmap_obj map;
 347         volatile SVGA3dQueryResult *result;
 348         bool dummy;
 349
 350         /*
 351          * Create the vbo as pinned, so that a tryreserve will
 352          * immediately succeed. This is because we're the only
 353          * user of the bo currently.
 354          */
 355         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
 356         if (!vbo)
 357                 return -ENOMEM;
 358
 359         ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
 360                           &vmw_sys_ne_placement, false,
 361                           &vmw_bo_bo_free);
 362         if (unlikely(ret != 0))
 363                 return ret;
 364
 365         ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
 366         BUG_ON(ret != 0);
 367         vmw_bo_pin_reserved(vbo, true);
 368
 369         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
 370         if (likely(ret == 0)) {
 371                 result = ttm_kmap_obj_virtual(&map, &dummy);
 372                 result->totalSize = sizeof(*result);
 373                 result->state = SVGA3D_QUERYSTATE_PENDING;
 374                 result->result32 = 0xff;
 375                 ttm_bo_kunmap(&map);
 376         }
 377         vmw_bo_pin_reserved(vbo, false);
 378         ttm_bo_unreserve(&vbo->base);
 379
 380         if (unlikely(ret != 0)) {
 381                 DRM_ERROR("Dummy query buffer map failed.\n");
 382                 vmw_bo_unreference(&vbo);
 383         } else
 384                 dev_priv->dummy_query_bo = vbo;
 385
 386         return ret;
 387 }
 388
 389 /**
 390  * vmw_request_device_late - Perform late device setup
 391  *
 392  * @dev_priv: Pointer to device private.
 393  *
 394  * This function performs setup of otables and enables large command
 395  * buffer submission. These tasks are split out to a separate function
 396  * because it reverts vmw_release_device_early and is intended to be used
 397  * by an error path in the hibernation code.
 398  */
 399 static int vmw_request_device_late(struct vmw_private *dev_priv)
 400 {
 401         int ret;
 402
 403         if (dev_priv->has_mob) {
 404                 ret = vmw_otables_setup(dev_priv);
 405                 if (unlikely(ret != 0)) {
 406                         DRM_ERROR("Unable to initialize "
 407                                   "guest Memory OBjects.\n");
 408                         return ret;
 409                 }
 410         }
 411
 412         if (dev_priv->cman) {
 413                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
 414                                                256*4096, 2*4096);
 415                 if (ret) {
 416                         struct vmw_cmdbuf_man *man = dev_priv->cman;
 417
 418                         dev_priv->cman = NULL;
 419                         vmw_cmdbuf_man_destroy(man);
 420                 }
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int vmw_request_device(struct vmw_private *dev_priv)
 427 {
 428         int ret;
 429
 430         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 431         if (unlikely(ret != 0)) {
 432                 DRM_ERROR("Unable to initialize FIFO.\n");
 433                 return ret;
 434         }
 435         vmw_fence_fifo_up(dev_priv->fman);
 436         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
 437         if (IS_ERR(dev_priv->cman)) {
 438                 dev_priv->cman = NULL;
 439                 dev_priv->has_dx = false;
 440         }
 441
 442         ret = vmw_request_device_late(dev_priv);
 443         if (ret)
 444                 goto out_no_mob;
 445
 446         ret = vmw_dummy_query_bo_create(dev_priv);
 447         if (unlikely(ret != 0))
 448                 goto out_no_query_bo;
 449
 450         return 0;
 451
 452 out_no_query_bo:
 453         if (dev_priv->cman)
 454                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 455         if (dev_priv->has_mob) {
 456                 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 457                 vmw_otables_takedown(dev_priv);
 458         }
 459         if (dev_priv->cman)
 460                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 461 out_no_mob:
 462         vmw_fence_fifo_down(dev_priv->fman);
 463         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 464         return ret;
 465 }
 466
 467 /**
 468  * vmw_release_device_early - Early part of fifo takedown.
 469  *
 470  * @dev_priv: Pointer to device private struct.
 471  *
 472  * This is the first part of command submission takedown, to be called before
 473  * buffer management is taken down.
 474  */
 475 static void vmw_release_device_early(struct vmw_private *dev_priv)
 476 {
 477         /*
 478          * Previous destructions should've released
 479          * the pinned bo.
 480          */
 481
 482         BUG_ON(dev_priv->pinned_bo != NULL);
 483
 484         vmw_bo_unreference(&dev_priv->dummy_query_bo);
 485         if (dev_priv->cman)
 486                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 487
 488         if (dev_priv->has_mob) {
 489                 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 490                 vmw_otables_takedown(dev_priv);
 491         }
 492 }
 493
 494 /**
 495  * vmw_release_device_late - Late part of fifo takedown.
 496  *
 497  * @dev_priv: Pointer to device private struct.
 498  *
 499  * This is the last part of the command submission takedown, to be called when
 500  * command submission is no longer needed. It may wait on pending fences.
 501  */
 502 static void vmw_release_device_late(struct vmw_private *dev_priv)
 503 {
 504         vmw_fence_fifo_down(dev_priv->fman);
 505         if (dev_priv->cman)
 506                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 507
 508         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 509 }
 510
 511 /**
 512  * Sets the initial_[width|height] fields on the given vmw_private.
 513  *
 514  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 515  * clamping the value to fb_max_[width|height] fields and the
 516  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 517  * If the values appear to be invalid, set them to
 518  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 519  */
 520 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 521 {
 522         uint32_t width;
 523         uint32_t height;
 524
 525         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 526         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 527
 528         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 529         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 530
 531         if (width > dev_priv->fb_max_width ||
 532             height > dev_priv->fb_max_height) {
 533
 534                 /*
 535                  * This is a host error and shouldn't occur.
 536                  */
 537
 538                 width = VMW_MIN_INITIAL_WIDTH;
 539                 height = VMW_MIN_INITIAL_HEIGHT;
 540         }
 541
 542         dev_priv->initial_width = width;
 543         dev_priv->initial_height = height;
 544 }
 545
 546 /**
 547  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 548  * system.
 549  *
 550  * @dev_priv: Pointer to a struct vmw_private
 551  *
 552  * This functions tries to determine the IOMMU setup and what actions
 553  * need to be taken by the driver to make system pages visible to the
 554  * device.
 555  * If this function decides that DMA is not possible, it returns -EINVAL.
 556  * The driver may then try to disable features of the device that require
 557  * DMA.
 558  */
 559 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 560 {
 561         static const char *names[vmw_dma_map_max] = {
 562                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 563                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 564                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 565                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 566 #ifdef CONFIG_X86
 567         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 568
 569 #ifdef CONFIG_INTEL_IOMMU
 570         if (intel_iommu_enabled) {
 571                 dev_priv->map_mode = vmw_dma_map_populate;
 572                 goto out_fixup;
 573         }
 574 #endif
 575
 576         if (!(vmw_force_iommu || vmw_force_coherent)) {
 577                 dev_priv->map_mode = vmw_dma_phys;
 578                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 579                 return 0;
 580         }
 581
 582         dev_priv->map_mode = vmw_dma_map_populate;
 583
 584         if (dma_ops->sync_single_for_cpu)
 585                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 586 #ifdef CONFIG_SWIOTLB
 587         if (swiotlb_nr_tbl() == 0)
 588                 dev_priv->map_mode = vmw_dma_map_populate;
 589 #endif
 590
 591 #ifdef CONFIG_INTEL_IOMMU
 592 out_fixup:
 593 #endif
 594         if (dev_priv->map_mode == vmw_dma_map_populate &&
 595             vmw_restrict_iommu)
 596                 dev_priv->map_mode = vmw_dma_map_bind;
 597
 598         if (vmw_force_coherent)
 599                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 600
 601 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
 602         /*
 603          * No coherent page pool
 604          */
 605         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
 606                 return -EINVAL;
 607 #endif
 608
 609 #else /* CONFIG_X86 */
 610         dev_priv->map_mode = vmw_dma_map_populate;
 611 #endif /* CONFIG_X86 */
 612
 613         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 614
 615         return 0;
 616 }
 617
 618 /**
 619  * vmw_dma_masks - set required page- and dma masks
 620  *
 621  * @dev: Pointer to struct drm-device
 622  *
 623  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 624  * restriction also for 64-bit systems.
 625  */
 626 #ifdef CONFIG_INTEL_IOMMU
 627 static int vmw_dma_masks(struct vmw_private *dev_priv)
 628 {
 629         struct drm_device *dev = dev_priv->dev;
 630         int ret = 0;
 631
 632         ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
 633         if (dev_priv->map_mode != vmw_dma_phys &&
 634             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 635                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 636                 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
 637         }
 638
 639         return ret;
 640 }
 641 #else
 642 static int vmw_dma_masks(struct vmw_private *dev_priv)
 643 {
 644         return 0;
 645 }
 646 #endif
 647
 648 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 649 {
 650         struct vmw_private *dev_priv;
 651         int ret;
 652         uint32_t svga_id;
 653         enum vmw_res_type i;
 654         bool refuse_dma = false;
 655         char host_log[100] = {0};
 656
 657         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 658         if (unlikely(!dev_priv)) {
 659                 DRM_ERROR("Failed allocating a device private struct.\n");
 660                 return -ENOMEM;
 661         }
 662
 663         pci_set_master(dev->pdev);
 664
 665         dev_priv->dev = dev;
 666         dev_priv->vmw_chipset = chipset;
 667         dev_priv->last_read_seqno = (uint32_t) -100;
 668         mutex_init(&dev_priv->cmdbuf_mutex);
 669         mutex_init(&dev_priv->release_mutex);
 670         mutex_init(&dev_priv->binding_mutex);
 671         mutex_init(&dev_priv->requested_layout_mutex);
 672         mutex_init(&dev_priv->global_kms_state_mutex);
 673         rwlock_init(&dev_priv->resource_lock);
 674         ttm_lock_init(&dev_priv->reservation_sem);
 675         spin_lock_init(&dev_priv->hw_lock);
 676         spin_lock_init(&dev_priv->waiter_lock);
 677         spin_lock_init(&dev_priv->cap_lock);
 678         spin_lock_init(&dev_priv->svga_lock);
 679         spin_lock_init(&dev_priv->cursor_lock);
 680
 681         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 682                 idr_init(&dev_priv->res_idr[i]);
 683                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 684         }
 685
 686         mutex_init(&dev_priv->init_mutex);
 687         init_waitqueue_head(&dev_priv->fence_queue);
 688         init_waitqueue_head(&dev_priv->fifo_queue);
 689         dev_priv->fence_queue_waiters = 0;
 690         dev_priv->fifo_queue_waiters = 0;
 691
 692         dev_priv->used_memory_size = 0;
 693
 694         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 695         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 696         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 697
 698         dev_priv->assume_16bpp = !!vmw_assume_16bpp;
 699
 700         dev_priv->enable_fb = enable_fbdev;
 701
 702         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 703         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 704         if (svga_id != SVGA_ID_2) {
 705                 ret = -ENOSYS;
 706                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 707                 goto out_err0;
 708         }
 709
 710         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 711
 712         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
 713                 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
 714         }
 715
 716
 717         ret = vmw_dma_select_mode(dev_priv);
 718         if (unlikely(ret != 0)) {
 719                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 720                 refuse_dma = true;
 721         }
 722
 723         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 724         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 725         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 726         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 727
 728         vmw_get_initial_size(dev_priv);
 729
 730         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 731                 dev_priv->max_gmr_ids =
 732                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 733                 dev_priv->max_gmr_pages =
 734                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 735                 dev_priv->memory_size =
 736                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 737                 dev_priv->memory_size -= dev_priv->vram_size;
 738         } else {
 739                 /*
 740                  * An arbitrary limit of 512MiB on surface
 741                  * memory. But all HWV8 hardware supports GMR2.
 742                  */
 743                 dev_priv->memory_size = 512*1024*1024;
 744         }
 745         dev_priv->max_mob_pages = 0;
 746         dev_priv->max_mob_size = 0;
 747         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 748                 uint64_t mem_size =
 749                         vmw_read(dev_priv,
 750                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 751
 752                 /*
 753                  * Workaround for low memory 2D VMs to compensate for the
 754                  * allocation taken by fbdev
 755                  */
 756                 if (!(dev_priv->capabilities & SVGA_CAP_3D))
 757                         mem_size *= 3;
 758
 759                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 760                 dev_priv->prim_bb_mem =
 761                         vmw_read(dev_priv,
 762                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 763                 dev_priv->max_mob_size =
 764                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
 765                 dev_priv->stdu_max_width =
 766                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
 767                 dev_priv->stdu_max_height =
 768                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
 769
 770                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 771                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
 772                 dev_priv->texture_max_width = vmw_read(dev_priv,
 773                                                        SVGA_REG_DEV_CAP);
 774                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 775                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
 776                 dev_priv->texture_max_height = vmw_read(dev_priv,
 777                                                         SVGA_REG_DEV_CAP);
 778         } else {
 779                 dev_priv->texture_max_width = 8192;
 780                 dev_priv->texture_max_height = 8192;
 781                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 782         }
 783
 784         vmw_print_capabilities(dev_priv->capabilities);
 785         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
 786                 vmw_print_capabilities2(dev_priv->capabilities2);
 787
 788         ret = vmw_dma_masks(dev_priv);
 789         if (unlikely(ret != 0))
 790                 goto out_err0;
 791
 792         dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
 793                                              SCATTERLIST_MAX_SEGMENT));
 794
 795         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 796                 DRM_INFO("Max GMR ids is %u\n",
 797                          (unsigned)dev_priv->max_gmr_ids);
 798                 DRM_INFO("Max number of GMR pages is %u\n",
 799                          (unsigned)dev_priv->max_gmr_pages);
 800                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 801                          (unsigned)dev_priv->memory_size / 1024);
 802         }
 803         DRM_INFO("Maximum display memory size is %u kiB\n",
 804                  dev_priv->prim_bb_mem / 1024);
 805         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 806                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 807         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 808                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 809
 810         ret = vmw_ttm_global_init(dev_priv);
 811         if (unlikely(ret != 0))
 812                 goto out_err0;
 813
 814
 815         vmw_master_init(&dev_priv->fbdev_master);
 816         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 817         dev_priv->active_master = &dev_priv->fbdev_master;
 818
 819         dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
 820                                        dev_priv->mmio_size, MEMREMAP_WB);
 821
 822         if (unlikely(dev_priv->mmio_virt == NULL)) {
 823                 ret = -ENOMEM;
 824                 DRM_ERROR("Failed mapping MMIO.\n");
 825                 goto out_err3;
 826         }
 827
 828         /* Need mmio memory to check for fifo pitchlock cap. */
 829         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 830             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 831             !vmw_fifo_have_pitchlock(dev_priv)) {
 832                 ret = -ENOSYS;
 833                 DRM_ERROR("Hardware has no pitchlock\n");
 834                 goto out_err4;
 835         }
 836
 837         dev_priv->tdev = ttm_object_device_init
 838                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 839
 840         if (unlikely(dev_priv->tdev == NULL)) {
 841                 DRM_ERROR("Unable to initialize TTM object management.\n");
 842                 ret = -ENOMEM;
 843                 goto out_err4;
 844         }
 845
 846         dev->dev_private = dev_priv;
 847
 848         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 849         dev_priv->stealth = (ret != 0);
 850         if (dev_priv->stealth) {
 851                 /**
 852                  * Request at least the mmio PCI resource.
 853                  */
 854
 855                 DRM_INFO("It appears like vesafb is loaded. "
 856                          "Ignore above error if any.\n");
 857                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 858                 if (unlikely(ret != 0)) {
 859                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 860                         goto out_no_device;
 861                 }
 862         }
 863
 864         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 865                 ret = vmw_irq_install(dev, dev->pdev->irq);
 866                 if (ret != 0) {
 867                         DRM_ERROR("Failed installing irq: %d\n", ret);
 868                         goto out_no_irq;
 869                 }
 870         }
 871
 872         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 873         if (unlikely(dev_priv->fman == NULL)) {
 874                 ret = -ENOMEM;
 875                 goto out_no_fman;
 876         }
 877
 878         ret = ttm_bo_device_init(&dev_priv->bdev,
 879                                  dev_priv->bo_global_ref.ref.object,
 880                                  &vmw_bo_driver,
 881                                  dev->anon_inode->i_mapping,
 882                                  VMWGFX_FILE_PAGE_OFFSET,
 883                                  false);
 884         if (unlikely(ret != 0)) {
 885                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 886                 goto out_no_bdev;
 887         }
 888
 889         /*
 890          * Enable VRAM, but initially don't use it until SVGA is enabled and
 891          * unhidden.
 892          */
 893         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 894                              (dev_priv->vram_size >> PAGE_SHIFT));
 895         if (unlikely(ret != 0)) {
 896                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 897                 goto out_no_vram;
 898         }
 899         dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
 900
 901         dev_priv->has_gmr = true;
 902         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 903             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 904                                          VMW_PL_GMR) != 0) {
 905                 DRM_INFO("No GMR memory available. "
 906                          "Graphics memory resources are very limited.\n");
 907                 dev_priv->has_gmr = false;
 908         }
 909
 910         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 911                 dev_priv->has_mob = true;
 912                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 913                                    VMW_PL_MOB) != 0) {
 914                         DRM_INFO("No MOB memory available. "
 915                                  "3D will be disabled.\n");
 916                         dev_priv->has_mob = false;
 917                 }
 918         }
 919
 920         if (dev_priv->has_mob) {
 921                 spin_lock(&dev_priv->cap_lock);
 922                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
 923                 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
 924                 spin_unlock(&dev_priv->cap_lock);
 925         }
 926
 927
 928         ret = vmw_kms_init(dev_priv);
 929         if (unlikely(ret != 0))
 930                 goto out_no_kms;
 931         vmw_overlay_init(dev_priv);
 932
 933         ret = vmw_request_device(dev_priv);
 934         if (ret)
 935                 goto out_no_fifo;
 936
 937         if (dev_priv->has_dx) {
 938                 /*
 939                  * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1
 940                  * support
 941                  */
 942                 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) {
 943                         vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 944                                         SVGA3D_DEVCAP_SM41);
 945                         dev_priv->has_sm4_1 = vmw_read(dev_priv,
 946                                                         SVGA_REG_DEV_CAP);
 947                 }
 948         }
 949
 950         DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
 951         DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
 952                  ? "yes." : "no.");
 953         DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no.");
 954
 955         snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
 956                 VMWGFX_REPO, VMWGFX_GIT_VERSION);
 957         vmw_host_log(host_log);
 958
 959         memset(host_log, 0, sizeof(host_log));
 960         snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
 961                 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
 962                 VMWGFX_DRIVER_PATCHLEVEL);
 963         vmw_host_log(host_log);
 964
 965         if (dev_priv->enable_fb) {
 966                 vmw_fifo_resource_inc(dev_priv);
 967                 vmw_svga_enable(dev_priv);
 968                 vmw_fb_init(dev_priv);
 969         }
 970
 971         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 972         register_pm_notifier(&dev_priv->pm_nb);
 973
 974         return 0;
 975
 976 out_no_fifo:
 977         vmw_overlay_close(dev_priv);
 978         vmw_kms_close(dev_priv);
 979 out_no_kms:
 980         if (dev_priv->has_mob)
 981                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 982         if (dev_priv->has_gmr)
 983                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 984         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 985 out_no_vram:
 986         (void)ttm_bo_device_release(&dev_priv->bdev);
 987 out_no_bdev:
 988         vmw_fence_manager_takedown(dev_priv->fman);
 989 out_no_fman:
 990         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 991                 vmw_irq_uninstall(dev_priv->dev);
 992 out_no_irq:
 993         if (dev_priv->stealth)
 994                 pci_release_region(dev->pdev, 2);
 995         else
 996                 pci_release_regions(dev->pdev);
 997 out_no_device:
 998         ttm_object_device_release(&dev_priv->tdev);
 999 out_err4:
1000         memunmap(dev_priv->mmio_virt);
1001 out_err3:
1002         vmw_ttm_global_release(dev_priv);
1003 out_err0:
1004         for (i = vmw_res_context; i < vmw_res_max; ++i)
1005                 idr_destroy(&dev_priv->res_idr[i]);
1006
1007         if (dev_priv->ctx.staged_bindings)
1008                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1009         kfree(dev_priv);
1010         return ret;
1011 }
1012
1013 static void vmw_driver_unload(struct drm_device *dev)
1014 {
1015         struct vmw_private *dev_priv = vmw_priv(dev);
1016         enum vmw_res_type i;
1017
1018         unregister_pm_notifier(&dev_priv->pm_nb);
1019
1020         if (dev_priv->ctx.res_ht_initialized)
1021                 drm_ht_remove(&dev_priv->ctx.res_ht);
1022         vfree(dev_priv->ctx.cmd_bounce);
1023         if (dev_priv->enable_fb) {
1024                 vmw_fb_off(dev_priv);
1025                 vmw_fb_close(dev_priv);
1026                 vmw_fifo_resource_dec(dev_priv);
1027                 vmw_svga_disable(dev_priv);
1028         }
1029
1030         vmw_kms_close(dev_priv);
1031         vmw_overlay_close(dev_priv);
1032
1033         if (dev_priv->has_gmr)
1034                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
1035         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
1036
1037         vmw_release_device_early(dev_priv);
1038         if (dev_priv->has_mob)
1039                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
1040         (void) ttm_bo_device_release(&dev_priv->bdev);
1041         vmw_release_device_late(dev_priv);
1042         vmw_fence_manager_takedown(dev_priv->fman);
1043         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1044                 vmw_irq_uninstall(dev_priv->dev);
1045         if (dev_priv->stealth)
1046                 pci_release_region(dev->pdev, 2);
1047         else
1048                 pci_release_regions(dev->pdev);
1049
1050         ttm_object_device_release(&dev_priv->tdev);
1051         memunmap(dev_priv->mmio_virt);
1052         if (dev_priv->ctx.staged_bindings)
1053                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1054         vmw_ttm_global_release(dev_priv);
1055
1056         for (i = vmw_res_context; i < vmw_res_max; ++i)
1057                 idr_destroy(&dev_priv->res_idr[i]);
1058
1059         kfree(dev_priv);
1060 }
1061
1062 static void vmw_postclose(struct drm_device *dev,
1063                          struct drm_file *file_priv)
1064 {
1065         struct vmw_fpriv *vmw_fp;
1066
1067         vmw_fp = vmw_fpriv(file_priv);
1068
1069         if (vmw_fp->locked_master) {
1070                 struct vmw_master *vmaster =
1071                         vmw_master(vmw_fp->locked_master);
1072
1073                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1074                 ttm_vt_unlock(&vmaster->lock);
1075                 drm_master_put(&vmw_fp->locked_master);
1076         }
1077
1078         ttm_object_file_release(&vmw_fp->tfile);
1079         kfree(vmw_fp);
1080 }
1081
1082 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1083 {
1084         struct vmw_private *dev_priv = vmw_priv(dev);
1085         struct vmw_fpriv *vmw_fp;
1086         int ret = -ENOMEM;
1087
1088         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1089         if (unlikely(!vmw_fp))
1090                 return ret;
1091
1092         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1093         if (unlikely(vmw_fp->tfile == NULL))
1094                 goto out_no_tfile;
1095
1096         file_priv->driver_priv = vmw_fp;
1097
1098         return 0;
1099
1100 out_no_tfile:
1101         kfree(vmw_fp);
1102         return ret;
1103 }
1104
1105 static struct vmw_master *vmw_master_check(struct drm_device *dev,
1106                                            struct drm_file *file_priv,
1107                                            unsigned int flags)
1108 {
1109         int ret;
1110         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1111         struct vmw_master *vmaster;
1112
1113         if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1114                 return NULL;
1115
1116         ret = mutex_lock_interruptible(&dev->master_mutex);
1117         if (unlikely(ret != 0))
1118                 return ERR_PTR(-ERESTARTSYS);
1119
1120         if (drm_is_current_master(file_priv)) {
1121                 mutex_unlock(&dev->master_mutex);
1122                 return NULL;
1123         }
1124
1125         /*
1126          * Check if we were previously master, but now dropped. In that
1127          * case, allow at least render node functionality.
1128          */
1129         if (vmw_fp->locked_master) {
1130                 mutex_unlock(&dev->master_mutex);
1131
1132                 if (flags & DRM_RENDER_ALLOW)
1133                         return NULL;
1134
1135                 DRM_ERROR("Dropped master trying to access ioctl that "
1136                           "requires authentication.\n");
1137                 return ERR_PTR(-EACCES);
1138         }
1139         mutex_unlock(&dev->master_mutex);
1140
1141         /*
1142          * Take the TTM lock. Possibly sleep waiting for the authenticating
1143          * master to become master again, or for a SIGTERM if the
1144          * authenticating master exits.
1145          */
1146         vmaster = vmw_master(file_priv->master);
1147         ret = ttm_read_lock(&vmaster->lock, true);
1148         if (unlikely(ret != 0))
1149                 vmaster = ERR_PTR(ret);
1150
1151         return vmaster;
1152 }
1153
1154 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1155                               unsigned long arg,
1156                               long (*ioctl_func)(struct file *, unsigned int,
1157                                                  unsigned long))
1158 {
1159         struct drm_file *file_priv = filp->private_data;
1160         struct drm_device *dev = file_priv->minor->dev;
1161         unsigned int nr = DRM_IOCTL_NR(cmd);
1162         struct vmw_master *vmaster;
1163         unsigned int flags;
1164         long ret;
1165
1166         /*
1167          * Do extra checking on driver private ioctls.
1168          */
1169
1170         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1171             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1172                 const struct drm_ioctl_desc *ioctl =
1173                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1174
1175                 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1176                         ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1177                         if (unlikely(ret != 0))
1178                                 return ret;
1179
1180                         if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1181                                 goto out_io_encoding;
1182
1183                         return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1184                                                         _IOC_SIZE(cmd));
1185                 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1186                         if (!drm_is_current_master(file_priv) &&
1187                             !capable(CAP_SYS_ADMIN))
1188                                 return -EACCES;
1189                 }
1190
1191                 if (unlikely(ioctl->cmd != cmd))
1192                         goto out_io_encoding;
1193
1194                 flags = ioctl->flags;
1195         } else if (!drm_ioctl_flags(nr, &flags))
1196                 return -EINVAL;
1197
1198         vmaster = vmw_master_check(dev, file_priv, flags);
1199         if (IS_ERR(vmaster)) {
1200                 ret = PTR_ERR(vmaster);
1201
1202                 if (ret != -ERESTARTSYS)
1203                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1204                                  nr, ret);
1205                 return ret;
1206         }
1207
1208         ret = ioctl_func(filp, cmd, arg);
1209         if (vmaster)
1210                 ttm_read_unlock(&vmaster->lock);
1211
1212         return ret;
1213
1214 out_io_encoding:
1215         DRM_ERROR("Invalid command format, ioctl %d\n",
1216                   nr - DRM_COMMAND_BASE);
1217
1218         return -EINVAL;
1219 }
1220
1221 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1222                                unsigned long arg)
1223 {
1224         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1225 }
1226
1227 #ifdef CONFIG_COMPAT
1228 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1229                              unsigned long arg)
1230 {
1231         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1232 }
1233 #endif
1234
1235 static void vmw_lastclose(struct drm_device *dev)
1236 {
1237 }
1238
1239 static void vmw_master_init(struct vmw_master *vmaster)
1240 {
1241         ttm_lock_init(&vmaster->lock);
1242 }
1243
1244 static int vmw_master_create(struct drm_device *dev,
1245                              struct drm_master *master)
1246 {
1247         struct vmw_master *vmaster;
1248
1249         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1250         if (unlikely(!vmaster))
1251                 return -ENOMEM;
1252
1253         vmw_master_init(vmaster);
1254         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1255         master->driver_priv = vmaster;
1256
1257         return 0;
1258 }
1259
1260 static void vmw_master_destroy(struct drm_device *dev,
1261                                struct drm_master *master)
1262 {
1263         struct vmw_master *vmaster = vmw_master(master);
1264
1265         master->driver_priv = NULL;
1266         kfree(vmaster);
1267 }
1268
1269 static int vmw_master_set(struct drm_device *dev,
1270                           struct drm_file *file_priv,
1271                           bool from_open)
1272 {
1273         struct vmw_private *dev_priv = vmw_priv(dev);
1274         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1275         struct vmw_master *active = dev_priv->active_master;
1276         struct vmw_master *vmaster = vmw_master(file_priv->master);
1277         int ret = 0;
1278
1279         if (active) {
1280                 BUG_ON(active != &dev_priv->fbdev_master);
1281                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1282                 if (unlikely(ret != 0))
1283                         return ret;
1284
1285                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1286                 dev_priv->active_master = NULL;
1287         }
1288
1289         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1290         if (!from_open) {
1291                 ttm_vt_unlock(&vmaster->lock);
1292                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1293                 drm_master_put(&vmw_fp->locked_master);
1294         }
1295
1296         dev_priv->active_master = vmaster;
1297
1298         /*
1299          * Inform a new master that the layout may have changed while
1300          * it was gone.
1301          */
1302         if (!from_open)
1303                 drm_sysfs_hotplug_event(dev);
1304
1305         return 0;
1306 }
1307
1308 static void vmw_master_drop(struct drm_device *dev,
1309                             struct drm_file *file_priv)
1310 {
1311         struct vmw_private *dev_priv = vmw_priv(dev);
1312         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1313         struct vmw_master *vmaster = vmw_master(file_priv->master);
1314         int ret;
1315
1316         /**
1317          * Make sure the master doesn't disappear while we have
1318          * it locked.
1319          */
1320
1321         vmw_fp->locked_master = drm_master_get(file_priv->master);
1322         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1323         vmw_kms_legacy_hotspot_clear(dev_priv);
1324         if (unlikely((ret != 0))) {
1325                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1326                 drm_master_put(&vmw_fp->locked_master);
1327         }
1328
1329         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1330
1331         if (!dev_priv->enable_fb)
1332                 vmw_svga_disable(dev_priv);
1333
1334         dev_priv->active_master = &dev_priv->fbdev_master;
1335         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1336         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1337 }
1338
1339 /**
1340  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1341  *
1342  * @dev_priv: Pointer to device private struct.
1343  * Needs the reservation sem to be held in non-exclusive mode.
1344  */
1345 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1346 {
1347         spin_lock(&dev_priv->svga_lock);
1348         if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1349                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1350                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1351         }
1352         spin_unlock(&dev_priv->svga_lock);
1353 }
1354
1355 /**
1356  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1357  *
1358  * @dev_priv: Pointer to device private struct.
1359  */
1360 void vmw_svga_enable(struct vmw_private *dev_priv)
1361 {
1362         (void) ttm_read_lock(&dev_priv->reservation_sem, false);
1363         __vmw_svga_enable(dev_priv);
1364         ttm_read_unlock(&dev_priv->reservation_sem);
1365 }
1366
1367 /**
1368  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1369  *
1370  * @dev_priv: Pointer to device private struct.
1371  * Needs the reservation sem to be held in exclusive mode.
1372  * Will not empty VRAM. VRAM must be emptied by caller.
1373  */
1374 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1375 {
1376         spin_lock(&dev_priv->svga_lock);
1377         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1378                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1379                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1380                           SVGA_REG_ENABLE_HIDE |
1381                           SVGA_REG_ENABLE_ENABLE);
1382         }
1383         spin_unlock(&dev_priv->svga_lock);
1384 }
1385
1386 /**
1387  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1388  * running.
1389  *
1390  * @dev_priv: Pointer to device private struct.
1391  * Will empty VRAM.
1392  */
1393 void vmw_svga_disable(struct vmw_private *dev_priv)
1394 {
1395         /*
1396          * Disabling SVGA will turn off device modesetting capabilities, so
1397          * notify KMS about that so that it doesn't cache atomic state that
1398          * isn't valid anymore, for example crtcs turned on.
1399          * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1400          * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1401          * end up with lock order reversal. Thus, a master may actually perform
1402          * a new modeset just after we call vmw_kms_lost_device() and race with
1403          * vmw_svga_disable(), but that should at worst cause atomic KMS state
1404          * to be inconsistent with the device, causing modesetting problems.
1405          *
1406          */
1407         vmw_kms_lost_device(dev_priv->dev);
1408         ttm_write_lock(&dev_priv->reservation_sem, false);
1409         spin_lock(&dev_priv->svga_lock);
1410         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1411                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1412                 spin_unlock(&dev_priv->svga_lock);
1413                 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1414                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1415                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1416                           SVGA_REG_ENABLE_HIDE |
1417                           SVGA_REG_ENABLE_ENABLE);
1418         } else
1419                 spin_unlock(&dev_priv->svga_lock);
1420         ttm_write_unlock(&dev_priv->reservation_sem);
1421 }
1422
1423 static void vmw_remove(struct pci_dev *pdev)
1424 {
1425         struct drm_device *dev = pci_get_drvdata(pdev);
1426
1427         pci_disable_device(pdev);
1428         drm_put_dev(dev);
1429 }
1430
1431 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1432                               void *ptr)
1433 {
1434         struct vmw_private *dev_priv =
1435                 container_of(nb, struct vmw_private, pm_nb);
1436
1437         switch (val) {
1438         case PM_HIBERNATION_PREPARE:
1439                 /*
1440                  * Take the reservation sem in write mode, which will make sure
1441                  * there are no other processes holding a buffer object
1442                  * reservation, meaning we should be able to evict all buffer
1443                  * objects if needed.
1444                  * Once user-space processes have been frozen, we can release
1445                  * the lock again.
1446                  */
1447                 ttm_suspend_lock(&dev_priv->reservation_sem);
1448                 dev_priv->suspend_locked = true;
1449                 break;
1450         case PM_POST_HIBERNATION:
1451         case PM_POST_RESTORE:
1452                 if (READ_ONCE(dev_priv->suspend_locked)) {
1453                         dev_priv->suspend_locked = false;
1454                         ttm_suspend_unlock(&dev_priv->reservation_sem);
1455                 }
1456                 break;
1457         default:
1458                 break;
1459         }
1460         return 0;
1461 }
1462
1463 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1464 {
1465         struct drm_device *dev = pci_get_drvdata(pdev);
1466         struct vmw_private *dev_priv = vmw_priv(dev);
1467
1468         if (dev_priv->refuse_hibernation)
1469                 return -EBUSY;
1470
1471         pci_save_state(pdev);
1472         pci_disable_device(pdev);
1473         pci_set_power_state(pdev, PCI_D3hot);
1474         return 0;
1475 }
1476
1477 static int vmw_pci_resume(struct pci_dev *pdev)
1478 {
1479         pci_set_power_state(pdev, PCI_D0);
1480         pci_restore_state(pdev);
1481         return pci_enable_device(pdev);
1482 }
1483
1484 static int vmw_pm_suspend(struct device *kdev)
1485 {
1486         struct pci_dev *pdev = to_pci_dev(kdev);
1487         struct pm_message dummy;
1488
1489         dummy.event = 0;
1490
1491         return vmw_pci_suspend(pdev, dummy);
1492 }
1493
1494 static int vmw_pm_resume(struct device *kdev)
1495 {
1496         struct pci_dev *pdev = to_pci_dev(kdev);
1497
1498         return vmw_pci_resume(pdev);
1499 }
1500
1501 static int vmw_pm_freeze(struct device *kdev)
1502 {
1503         struct pci_dev *pdev = to_pci_dev(kdev);
1504         struct drm_device *dev = pci_get_drvdata(pdev);
1505         struct vmw_private *dev_priv = vmw_priv(dev);
1506         int ret;
1507
1508         /*
1509          * Unlock for vmw_kms_suspend.
1510          * No user-space processes should be running now.
1511          */
1512         ttm_suspend_unlock(&dev_priv->reservation_sem);
1513         ret = vmw_kms_suspend(dev_priv->dev);
1514         if (ret) {
1515                 ttm_suspend_lock(&dev_priv->reservation_sem);
1516                 DRM_ERROR("Failed to freeze modesetting.\n");
1517                 return ret;
1518         }
1519         if (dev_priv->enable_fb)
1520                 vmw_fb_off(dev_priv);
1521
1522         ttm_suspend_lock(&dev_priv->reservation_sem);
1523         vmw_execbuf_release_pinned_bo(dev_priv);
1524         vmw_resource_evict_all(dev_priv);
1525         vmw_release_device_early(dev_priv);
1526         ttm_bo_swapout_all(&dev_priv->bdev);
1527         if (dev_priv->enable_fb)
1528                 vmw_fifo_resource_dec(dev_priv);
1529         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1530                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1531                 if (dev_priv->enable_fb)
1532                         vmw_fifo_resource_inc(dev_priv);
1533                 WARN_ON(vmw_request_device_late(dev_priv));
1534                 dev_priv->suspend_locked = false;
1535                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1536                 if (dev_priv->suspend_state)
1537                         vmw_kms_resume(dev);
1538                 if (dev_priv->enable_fb)
1539                         vmw_fb_on(dev_priv);
1540                 return -EBUSY;
1541         }
1542
1543         vmw_fence_fifo_down(dev_priv->fman);
1544         __vmw_svga_disable(dev_priv);
1545
1546         vmw_release_device_late(dev_priv);
1547         return 0;
1548 }
1549
1550 static int vmw_pm_restore(struct device *kdev)
1551 {
1552         struct pci_dev *pdev = to_pci_dev(kdev);
1553         struct drm_device *dev = pci_get_drvdata(pdev);
1554         struct vmw_private *dev_priv = vmw_priv(dev);
1555         int ret;
1556
1557         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1558         (void) vmw_read(dev_priv, SVGA_REG_ID);
1559
1560         if (dev_priv->enable_fb)
1561                 vmw_fifo_resource_inc(dev_priv);
1562
1563         ret = vmw_request_device(dev_priv);
1564         if (ret)
1565                 return ret;
1566
1567         if (dev_priv->enable_fb)
1568                 __vmw_svga_enable(dev_priv);
1569
1570         vmw_fence_fifo_up(dev_priv->fman);
1571         dev_priv->suspend_locked = false;
1572         ttm_suspend_unlock(&dev_priv->reservation_sem);
1573         if (dev_priv->suspend_state)
1574                 vmw_kms_resume(dev_priv->dev);
1575
1576         if (dev_priv->enable_fb)
1577                 vmw_fb_on(dev_priv);
1578
1579         return 0;
1580 }
1581
1582 static const struct dev_pm_ops vmw_pm_ops = {
1583         .freeze = vmw_pm_freeze,
1584         .thaw = vmw_pm_restore,
1585         .restore = vmw_pm_restore,
1586         .suspend = vmw_pm_suspend,
1587         .resume = vmw_pm_resume,
1588 };
1589
1590 static const struct file_operations vmwgfx_driver_fops = {
1591         .owner = THIS_MODULE,
1592         .open = drm_open,
1593         .release = drm_release,
1594         .unlocked_ioctl = vmw_unlocked_ioctl,
1595         .mmap = vmw_mmap,
1596         .poll = vmw_fops_poll,
1597         .read = vmw_fops_read,
1598 #if defined(CONFIG_COMPAT)
1599         .compat_ioctl = vmw_compat_ioctl,
1600 #endif
1601         .llseek = noop_llseek,
1602 };
1603
1604 static struct drm_driver driver = {
1605         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1606         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
1607         .load = vmw_driver_load,
1608         .unload = vmw_driver_unload,
1609         .lastclose = vmw_lastclose,
1610         .get_vblank_counter = vmw_get_vblank_counter,
1611         .enable_vblank = vmw_enable_vblank,
1612         .disable_vblank = vmw_disable_vblank,
1613         .ioctls = vmw_ioctls,
1614         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1615         .master_create = vmw_master_create,
1616         .master_destroy = vmw_master_destroy,
1617         .master_set = vmw_master_set,
1618         .master_drop = vmw_master_drop,
1619         .open = vmw_driver_open,
1620         .postclose = vmw_postclose,
1621
1622         .dumb_create = vmw_dumb_create,
1623         .dumb_map_offset = vmw_dumb_map_offset,
1624         .dumb_destroy = vmw_dumb_destroy,
1625
1626         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1627         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1628
1629         .fops = &vmwgfx_driver_fops,
1630         .name = VMWGFX_DRIVER_NAME,
1631         .desc = VMWGFX_DRIVER_DESC,
1632         .date = VMWGFX_DRIVER_DATE,
1633         .major = VMWGFX_DRIVER_MAJOR,
1634         .minor = VMWGFX_DRIVER_MINOR,
1635         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1636 };
1637
1638 static struct pci_driver vmw_pci_driver = {
1639         .name = VMWGFX_DRIVER_NAME,
1640         .id_table = vmw_pci_id_list,
1641         .probe = vmw_probe,
1642         .remove = vmw_remove,
1643         .driver = {
1644                 .pm = &vmw_pm_ops
1645         }
1646 };
1647
1648 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1649 {
1650         return drm_get_pci_dev(pdev, ent, &driver);
1651 }
1652
1653 static int __init vmwgfx_init(void)
1654 {
1655         int ret;
1656
1657         if (vgacon_text_force())
1658                 return -EINVAL;
1659
1660         ret = pci_register_driver(&vmw_pci_driver);
1661         if (ret)
1662                 DRM_ERROR("Failed initializing DRM.\n");
1663         return ret;
1664 }
1665
1666 static void __exit vmwgfx_exit(void)
1667 {
1668         pci_unregister_driver(&vmw_pci_driver);
1669 }
1670
1671 module_init(vmwgfx_init);
1672 module_exit(vmwgfx_exit);
1673
1674 MODULE_AUTHOR("VMware Inc. and others");
1675 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1676 MODULE_LICENSE("GPL and additional rights");
1677 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1678                __stringify(VMWGFX_DRIVER_MINOR) "."
1679                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1680                "0");