1 /**********************************************************
2 * Copyright 1998-2015 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
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9 * of the Software, and to permit persons to whom the Software is
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12 * The above copyright notice and this permission notice shall be
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
29 * Virtual hardware definitions for the VMware SVGA II device.
34 #include <linux/pci_ids.h>
36 #define INCLUDE_ALLOW_MODULE
37 #define INCLUDE_ALLOW_USERLEVEL
39 #define INCLUDE_ALLOW_VMCORE
40 #include "includeCheck.h"
42 #include "svga_types.h"
45 * SVGA_REG_ENABLE bit definitions.
48 SVGA_REG_ENABLE_DISABLE = 0,
49 SVGA_REG_ENABLE_ENABLE = (1 << 0),
50 SVGA_REG_ENABLE_HIDE = (1 << 1),
53 typedef uint32 SVGAMobId;
56 * Arbitrary and meaningless limits. Please ignore these when writing
59 #define SVGA_MAX_WIDTH 2560
60 #define SVGA_MAX_HEIGHT 1600
63 #define SVGA_MAX_BITS_PER_PIXEL 32
64 #define SVGA_MAX_DEPTH 24
65 #define SVGA_MAX_DISPLAYS 10
68 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
69 * cursor bypass mode. This is still supported, but no new guest
70 * drivers should use it.
72 #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
73 #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
74 #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
75 #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
78 * The maximum framebuffer size that can traced for guests unless the
79 * SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case
80 * the full framebuffer can be traced independent of this limit.
82 #define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
84 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
85 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
86 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
88 #define SVGA_MAGIC 0x900000UL
89 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
91 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
92 #define SVGA_VERSION_2 2
93 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
95 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
96 PALETTE_BASE has moved */
97 #define SVGA_VERSION_1 1
98 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
100 /* Version 0 is the initial version */
101 #define SVGA_VERSION_0 0
102 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
104 /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
105 #define SVGA_ID_INVALID 0xFFFFFFFF
107 /* Port offsets, relative to BAR0 */
108 #define SVGA_INDEX_PORT 0x0
109 #define SVGA_VALUE_PORT 0x1
110 #define SVGA_BIOS_PORT 0x2
111 #define SVGA_IRQSTATUS_PORT 0x8
114 * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
116 * Interrupts are only supported when the
117 * SVGA_CAP_IRQMASK capability is present.
119 #define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */
120 #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */
121 #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */
122 #define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */
123 #define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */
134 SVGA_REG_MAX_WIDTH = 4,
135 SVGA_REG_MAX_HEIGHT = 5,
137 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
138 SVGA_REG_PSEUDOCOLOR = 8,
139 SVGA_REG_RED_MASK = 9,
140 SVGA_REG_GREEN_MASK = 10,
141 SVGA_REG_BLUE_MASK = 11,
142 SVGA_REG_BYTES_PER_LINE = 12,
143 SVGA_REG_FB_START = 13, /* (Deprecated) */
144 SVGA_REG_FB_OFFSET = 14,
145 SVGA_REG_VRAM_SIZE = 15,
146 SVGA_REG_FB_SIZE = 16,
148 /* ID 0 implementation only had the above registers, then the palette */
149 SVGA_REG_ID_0_TOP = 17,
151 SVGA_REG_CAPABILITIES = 17,
152 SVGA_REG_MEM_START = 18, /* (Deprecated) */
153 SVGA_REG_MEM_SIZE = 19,
154 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
155 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
156 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
157 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
158 SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
159 SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
160 SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
161 SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */
162 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
163 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
164 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
165 SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */
166 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
167 SVGA_REG_IRQMASK = 33, /* Interrupt mask */
169 /* Legacy multi-monitor support */
170 SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
171 SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */
172 SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
173 SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
174 SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
175 SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */
176 SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */
178 /* See "Guest memory regions" below. */
179 SVGA_REG_GMR_ID = 41,
180 SVGA_REG_GMR_DESCRIPTOR = 42,
181 SVGA_REG_GMR_MAX_IDS = 43,
182 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
184 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
185 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
186 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
187 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
188 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
189 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
190 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
191 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
192 SVGA_REG_CMD_PREPEND_LOW = 53,
193 SVGA_REG_CMD_PREPEND_HIGH = 54,
194 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
195 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
196 SVGA_REG_MOB_MAX_SIZE = 57,
197 SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
199 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
200 /* Next 768 (== 256*3) registers exist for colormap */
201 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
202 /* Base of scratch registers */
203 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
204 First 4 are reserved for VESA BIOS Extension; any remaining are for
205 the use of the current SVGA driver. */
209 * Guest memory regions (GMRs):
211 * This is a new memory mapping feature available in SVGA devices
212 * which have the SVGA_CAP_GMR bit set. Previously, there were two
213 * fixed memory regions available with which to share data between the
214 * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
215 * are our name for an extensible way of providing arbitrary DMA
216 * buffers for use between the driver and the SVGA device. They are a
217 * new alternative to framebuffer memory, usable for both 2D and 3D
218 * graphics operations.
220 * Since GMR mapping must be done synchronously with guest CPU
221 * execution, we use a new pair of SVGA registers:
226 * This register holds the 32-bit ID (a small positive integer)
227 * of a GMR to create, delete, or redefine. Writing this register
228 * has no side-effects.
230 * SVGA_REG_GMR_DESCRIPTOR --
233 * Writing this register will create, delete, or redefine the GMR
234 * specified by the above ID register. If this register is zero,
235 * the GMR is deleted. Any pointers into this GMR (including those
236 * currently being processed by FIFO commands) will be
237 * synchronously invalidated.
239 * If this register is nonzero, it must be the physical page
240 * number (PPN) of a data structure which describes the physical
241 * layout of the memory region this GMR should describe. The
242 * descriptor structure will be read synchronously by the SVGA
243 * device when this register is written. The descriptor need not
244 * remain allocated for the lifetime of the GMR.
246 * The guest driver should write SVGA_REG_GMR_ID first, then
247 * SVGA_REG_GMR_DESCRIPTOR.
249 * SVGA_REG_GMR_MAX_IDS --
252 * The SVGA device may choose to support a maximum number of
253 * user-defined GMR IDs. This register holds the number of supported
254 * IDs. (The maximum supported ID plus 1)
256 * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
259 * The SVGA device may choose to put a limit on the total number
260 * of SVGAGuestMemDescriptor structures it will read when defining
263 * The descriptor structure is an array of SVGAGuestMemDescriptor
264 * structures. Each structure may do one of three things:
266 * - Terminate the GMR descriptor list.
267 * (ppn==0, numPages==0)
269 * - Add a PPN or range of PPNs to the GMR's virtual address space.
270 * (ppn != 0, numPages != 0)
272 * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
273 * support multi-page GMR descriptor tables without forcing the
274 * driver to allocate physically contiguous memory.
275 * (ppn != 0, numPages == 0)
277 * Note that each physical page of SVGAGuestMemDescriptor structures
278 * can describe at least 2MB of guest memory. If the driver needs to
279 * use more than one page of descriptor structures, it must use one of
280 * its SVGAGuestMemDescriptors to point to an additional page. The
281 * device will never automatically cross a page boundary.
283 * Once the driver has described a GMR, it is immediately available
284 * for use via any FIFO command that uses an SVGAGuestPtr structure.
285 * These pointers include a GMR identifier plus an offset into that
288 * The driver must check the SVGA_CAP_GMR bit before using the GMR
293 * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
294 * memory as well. In the future, these IDs could even be used to
295 * allow legacy memory regions to be redefined by the guest as GMRs.
297 * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
298 * is being phased out. Please try to use user-defined GMRs whenever
301 #define SVGA_GMR_NULL ((uint32) -1)
302 #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */
305 #include "vmware_pack_begin.h"
306 struct SVGAGuestMemDescriptor {
310 #include "vmware_pack_end.h"
311 SVGAGuestMemDescriptor;
314 #include "vmware_pack_begin.h"
315 struct SVGAGuestPtr {
319 #include "vmware_pack_end.h"
323 * Register based command buffers --
325 * Provide an SVGA device interface that allows the guest to submit
326 * command buffers to the SVGA device through an SVGA device register.
327 * The metadata for each command buffer is contained in the
328 * SVGACBHeader structure along with the return status codes.
330 * The SVGA device supports command buffers if
331 * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The
332 * fifo must be enabled for command buffers to be submitted.
334 * Command buffers are submitted when the guest writing the 64 byte
335 * aligned physical address into the SVGA_REG_COMMAND_LOW and
336 * SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32
337 * bits of the physical address. SVGA_REG_COMMAND_LOW contains the
338 * lower 32 bits of the physical address, since the command buffer
339 * headers are required to be 64 byte aligned the lower 6 bits are
340 * used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW
341 * submits the command buffer to the device and queues it for
342 * execution. The SVGA device supports at least
343 * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
344 * per context and if that limit is reached the device will write the
345 * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
346 * buffer header synchronously and not raise any IRQs.
348 * It is invalid to submit a command buffer without a valid physical
349 * address and results are undefined.
351 * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
352 * will be supported. If a larger command buffer is submitted results
353 * are unspecified and the device will either complete the command
354 * buffer or return an error.
356 * The device guarantees that any individual command in a command
357 * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
358 * enough to fit a 64x64 color-cursor definition. If the command is
359 * too large the device is allowed to process the command or return an
362 * The device context is a special SVGACBContext that allows for
363 * synchronous register like accesses with the flexibility of
364 * commands. There is a different command set defined by
365 * SVGADeviceContextCmdId. The commands in each command buffer is not
366 * allowed to straddle physical pages.
368 * The offset field which is available starting with the
369 * SVGA_CAP_CMD_BUFFERS_2 cap bit can be set by the guest to bias the
370 * start of command processing into the buffer. If an error is
371 * encountered the errorOffset will still be relative to the specific
372 * PA, not biased by the offset. When the command buffer is finished
373 * the guest should not read the offset field as there is no guarantee
374 * what it will set to.
377 #define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */
378 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
379 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */
381 #define SVGA_CB_CONTEXT_MASK 0x3f
383 SVGA_CB_CONTEXT_DEVICE = 0x3f,
384 SVGA_CB_CONTEXT_0 = 0x0,
385 SVGA_CB_CONTEXT_MAX = 0x1,
391 * The guest is supposed to write SVGA_CB_STATUS_NONE to the status
392 * field before submitting the command buffer header, the host will
393 * change the value when it is done with the command buffer.
395 SVGA_CB_STATUS_NONE = 0,
398 * Written by the host when a command buffer completes successfully.
399 * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
400 * the SVGA_CB_FLAG_NO_IRQ flag is set.
402 SVGA_CB_STATUS_COMPLETED = 1,
405 * Written by the host synchronously with the command buffer
406 * submission to indicate the command buffer was not submitted. No
409 SVGA_CB_STATUS_QUEUE_FULL = 2,
412 * Written by the host when an error was detected parsing a command
413 * in the command buffer, errorOffset is written to contain the
414 * offset to the first byte of the failing command. The device
415 * raises the IRQ with both SVGA_IRQFLAG_ERROR and
416 * SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been
419 SVGA_CB_STATUS_COMMAND_ERROR = 3,
422 * Written by the host if there is an error parsing the command
423 * buffer header. The device raises the IRQ with both
424 * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device
425 * did not processes any of the command buffer.
427 SVGA_CB_STATUS_CB_HEADER_ERROR = 4,
430 * Written by the host if the guest requested the host to preempt
431 * the command buffer. The device will not raise any IRQs and the
432 * command buffer was not processed.
434 SVGA_CB_STATUS_PREEMPTED = 5,
437 * Written by the host synchronously with the command buffer
438 * submission to indicate the the command buffer was not submitted
439 * due to an error. No IRQ is raised.
441 SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
445 SVGA_CB_FLAG_NONE = 0,
446 SVGA_CB_FLAG_NO_IRQ = 1 << 0,
447 SVGA_CB_FLAG_DX_CONTEXT = 1 << 1,
448 SVGA_CB_FLAG_MOB = 1 << 2,
452 #include "vmware_pack_begin.h"
454 volatile SVGACBStatus status;
455 volatile uint32 errorOffset;
466 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise */
467 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
468 uint32 mustBeZero[6];
470 #include "vmware_pack_end.h"
475 SVGA_DC_CMD_START_STOP_CONTEXT = 1,
476 SVGA_DC_CMD_PREEMPT = 2,
478 SVGA_DC_CMD_FORCE_UINT = MAX_UINT32,
479 } SVGADeviceContextCmdId;
483 SVGACBContext context;
484 } SVGADCCmdStartStop;
487 * SVGADCCmdPreempt --
489 * This command allows the guest to request that all command buffers
490 * on the specified context be preempted that can be. After execution
491 * of this command all command buffers that were preempted will
492 * already have SVGA_CB_STATUS_PREEMPTED written into the status
493 * field. The device might still be processing a command buffer,
494 * assuming execution of it started before the preemption request was
495 * received. Specifying the ignoreIDZero flag to TRUE will cause the
496 * device to not preempt command buffers with the id field in the
497 * command buffer header set to zero.
501 SVGACBContext context;
506 * SVGAGMRImageFormat --
508 * This is a packed representation of the source 2D image format
509 * for a GMR-to-screen blit. Currently it is defined as an encoding
510 * of the screen's color depth and bits-per-pixel, however, 16 bits
511 * are reserved for future use to identify other encodings (such as
512 * RGBA or higher-precision images).
514 * Currently supported formats:
516 * bpp depth Format Name
517 * --- ----- -----------
525 typedef struct SVGAGMRImageFormat {
528 uint32 bitsPerPixel : 8;
529 uint32 colorDepth : 8;
530 uint32 reserved : 16; /* Must be zero */
535 } SVGAGMRImageFormat;
538 #include "vmware_pack_begin.h"
539 struct SVGAGuestImage {
543 * A note on interpretation of pitch: This value of pitch is the
544 * number of bytes between vertically adjacent image
545 * blocks. Normally this is the number of bytes between the first
546 * pixel of two adjacent scanlines. With compressed textures,
547 * however, this may represent the number of bytes between
548 * compression blocks rather than between rows of pixels.
550 * XXX: Compressed textures currently must be tightly packed in guest memory.
552 * If the image is 1-dimensional, pitch is ignored.
554 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
555 * assuming each row of blocks is tightly packed.
559 #include "vmware_pack_end.h"
565 * A 24-bit color format (BGRX), which does not depend on the
566 * format of the legacy guest framebuffer (GFB) or the current
570 typedef struct SVGAColorBGRX {
576 uint32 x : 8; /* Unused */
588 * Signed rectangle and point primitives. These are used by the new
589 * 2D primitives for drawing to Screen Objects, which can occupy a
590 * signed virtual coordinate space.
592 * SVGASignedRect specifies a half-open interval: the (left, top)
593 * pixel is part of the rectangle, but the (right, bottom) pixel is
598 #include "vmware_pack_begin.h"
605 #include "vmware_pack_end.h"
609 #include "vmware_pack_begin.h"
614 #include "vmware_pack_end.h"
619 * SVGA Device Capabilities
621 * Note the holes in the bitfield. Missing bits have been deprecated,
622 * and must not be reused. Those capabilities will never be reported
623 * by new versions of the SVGA device.
625 * XXX: Add longer descriptions for each capability, including a list
626 * of the new features that each capability provides.
628 * SVGA_CAP_IRQMASK --
629 * Provides device interrupts. Adds device register SVGA_REG_IRQMASK
630 * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
631 * set/clear pending interrupts.
634 * Provides synchronous mapping of guest memory regions (GMR).
635 * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
636 * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
639 * Allows framebuffer trace-based updates even when FIFO is enabled.
640 * Adds device register SVGA_REG_TRACES.
643 * Provides asynchronous commands to define and remap guest memory
644 * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and
645 * SVGA_REG_MEMORY_SIZE.
647 * SVGA_CAP_SCREEN_OBJECT_2 --
648 * Allow screen object support, and require backing stores from the
649 * guest for each screen object.
651 * SVGA_CAP_COMMAND_BUFFERS --
652 * Enable register based command buffer submission.
655 * This cap was incorrectly used by old drivers and should not be
658 * SVGA_CAP_CMD_BUFFERS_2 --
659 * Enable support for the prepend command buffer submision
660 * registers. SVGA_REG_CMD_PREPEND_LOW and
661 * SVGA_REG_CMD_PREPEND_HIGH.
663 * SVGA_CAP_GBOBJECTS --
664 * Enable guest-backed objects and surfaces.
666 * SVGA_CAP_CMD_BUFFERS_3 --
667 * Enable support for command buffers in a mob.
670 #define SVGA_CAP_NONE 0x00000000
671 #define SVGA_CAP_RECT_COPY 0x00000002
672 #define SVGA_CAP_CURSOR 0x00000020
673 #define SVGA_CAP_CURSOR_BYPASS 0x00000040
674 #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
675 #define SVGA_CAP_8BIT_EMULATION 0x00000100
676 #define SVGA_CAP_ALPHA_CURSOR 0x00000200
677 #define SVGA_CAP_3D 0x00004000
678 #define SVGA_CAP_EXTENDED_FIFO 0x00008000
679 #define SVGA_CAP_MULTIMON 0x00010000
680 #define SVGA_CAP_PITCHLOCK 0x00020000
681 #define SVGA_CAP_IRQMASK 0x00040000
682 #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
683 #define SVGA_CAP_GMR 0x00100000
684 #define SVGA_CAP_TRACES 0x00200000
685 #define SVGA_CAP_GMR2 0x00400000
686 #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
687 #define SVGA_CAP_COMMAND_BUFFERS 0x01000000
688 #define SVGA_CAP_DEAD1 0x02000000
689 #define SVGA_CAP_CMD_BUFFERS_2 0x04000000
690 #define SVGA_CAP_GBOBJECTS 0x08000000
691 #define SVGA_CAP_DX 0x10000000
693 #define SVGA_CAP_CMD_RESERVED 0x80000000
697 * The Guest can optionally read some SVGA device capabilities through
698 * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
699 * the SVGA device is initialized. The type of capability the guest
700 * is requesting from the SVGABackdoorCapType enum should be placed in
701 * the upper 16 bits of the backdoor command id (ECX). On success the
702 * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
703 * the requested capability. If the command is not supported then EBX
704 * will be left unchanged and EAX will be set to -1. Because it is
705 * possible that -1 is the value of the requested cap the correct way
706 * to check if the command was successful is to check if EBX was changed
707 * to BDOOR_MAGIC making sure to initialize the register to something
712 SVGABackdoorCapDeviceCaps = 0,
713 SVGABackdoorCapFifoCaps = 1,
714 SVGABackdoorCap3dHWVersion = 2,
715 SVGABackdoorCapMax = 3,
716 } SVGABackdoorCapType;
720 * FIFO register indices.
722 * The FIFO is a chunk of device memory mapped into guest physmem. It
723 * is always treated as 32-bit words.
725 * The guest driver gets to decide how to partition it between
726 * - FIFO registers (there are always at least 4, specifying where the
727 * following data area is and how much data it contains; there may be
728 * more registers following these, depending on the FIFO protocol
730 * - FIFO data, written by the guest and slurped out by the VMX.
731 * These indices are 32-bit word offsets into the FIFO.
736 * Block 1 (basic registers): The originally defined FIFO registers.
737 * These exist and are valid for all versions of the FIFO protocol.
741 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
746 * Block 2 (extended registers): Mandatory registers for the extended
747 * FIFO. These exist if the SVGA caps register includes
748 * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
749 * associated capability bit is enabled.
751 * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
752 * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
753 * This means that the guest has to test individually (in most cases
754 * using FIFO caps) for the presence of registers after this; the VMX
755 * can define "extended FIFO" to mean whatever it wants, and currently
756 * won't enable it unless there's room for that set and much more.
759 SVGA_FIFO_CAPABILITIES = 4,
761 /* Valid with SVGA_FIFO_CAP_FENCE: */
765 * Block 3a (optional extended registers): Additional registers for the
766 * extended FIFO, whose presence isn't actually implied by
767 * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
768 * leave room for them.
770 * These in block 3a, the VMX currently considers mandatory for the
774 /* Valid if exists (i.e. if extended FIFO enabled): */
775 SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */
776 /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
779 /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
780 SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */
781 SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */
782 SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */
783 SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */
784 SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
786 /* Valid with SVGA_FIFO_CAP_RESERVE: */
787 SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */
790 * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
792 * By default this is SVGA_ID_INVALID, to indicate that the cursor
793 * coordinates are specified relative to the virtual root. If this
794 * is set to a specific screen ID, cursor position is reinterpreted
795 * as a signed offset relative to that screen's origin.
797 SVGA_FIFO_CURSOR_SCREEN_ID,
800 * Valid with SVGA_FIFO_CAP_DEAD
802 * An arbitrary value written by the host, drivers should not use it.
807 * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
809 * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
810 * on platforms that can enforce graphics resource limits.
812 SVGA_FIFO_3D_HWVERSION_REVISED,
815 * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
816 * registers, but this must be done carefully and with judicious use of
817 * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
818 * enough to tell you whether the register exists: we've shipped drivers
819 * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
820 * the earlier ones. The actual order of introduction was:
823 * - CURSOR_* (cursor bypass 3)
825 * So, code that wants to know whether it can use any of the
826 * aforementioned registers, or anything else added after PITCHLOCK and
827 * before 3D_CAPS, needs to reason about something other than
832 * 3D caps block space; valid with 3D hardware version >=
833 * SVGA3D_HWVERSION_WS6_B1.
835 SVGA_FIFO_3D_CAPS = 32,
836 SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
839 * End of VMX's current definition of "extended-FIFO registers".
840 * Registers before here are always enabled/disabled as a block; either
841 * the extended FIFO is enabled and includes all preceding registers, or
842 * it's disabled entirely.
844 * Block 3b (truly optional extended registers): Additional registers for
845 * the extended FIFO, which the VMX already knows how to enable and
846 * disable with correct granularity.
848 * Registers after here exist if and only if the guest SVGA driver
849 * sets SVGA_FIFO_MIN high enough to leave room for them.
852 /* Valid if register exists: */
853 SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
854 SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
855 SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */
858 * Always keep this last. This defines the maximum number of
859 * registers we know about. At power-on, this value is placed in
860 * the SVGA_REG_MEM_REGS register, and we expect the guest driver
861 * to allocate this much space in FIFO memory for registers.
868 * Definition of registers included in extended FIFO support.
870 * The guest SVGA driver gets to allocate the FIFO between registers
871 * and data. It must always allocate at least 4 registers, but old
872 * drivers stopped there.
874 * The VMX will enable extended FIFO support if and only if the guest
875 * left enough room for all registers defined as part of the mandatory
876 * set for the extended FIFO.
878 * Note that the guest drivers typically allocate the FIFO only at
879 * initialization time, not at mode switches, so it's likely that the
880 * number of FIFO registers won't change without a reboot.
882 * All registers less than this value are guaranteed to be present if
883 * svgaUser->fifo.extended is set. Any later registers must be tested
884 * individually for compatibility at each use (in the VMX).
886 * This value is used only by the VMX, so it can change without
887 * affecting driver compatibility; keep it that way?
889 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
893 * FIFO Synchronization Registers
895 * This explains the relationship between the various FIFO
896 * sync-related registers in IOSpace and in FIFO space.
900 * The SYNC register can be used in two different ways by the guest:
902 * 1. If the guest wishes to fully sync (drain) the FIFO,
903 * it will write once to SYNC then poll on the BUSY
904 * register. The FIFO is sync'ed once BUSY is zero.
906 * 2. If the guest wants to asynchronously wake up the host,
907 * it will write once to SYNC without polling on BUSY.
908 * Ideally it will do this after some new commands have
909 * been placed in the FIFO, and after reading a zero
910 * from SVGA_FIFO_BUSY.
912 * (1) is the original behaviour that SYNC was designed to
913 * support. Originally, a write to SYNC would implicitly
914 * trigger a read from BUSY. This causes us to synchronously
917 * This behaviour has since been changed so that writing SYNC
918 * will *not* implicitly cause a read from BUSY. Instead, it
919 * makes a channel call which asynchronously wakes up the MKS
922 * New guests can use this new behaviour to implement (2)
923 * efficiently. This lets guests get the host's attention
924 * without waiting for the MKS to poll, which gives us much
925 * better CPU utilization on SMP hosts and on UP hosts while
926 * we're blocked on the host GPU.
928 * Old guests shouldn't notice the behaviour change. SYNC was
929 * never guaranteed to process the entire FIFO, since it was
930 * bounded to a particular number of CPU cycles. Old guests will
931 * still loop on the BUSY register until the FIFO is empty.
933 * Writing to SYNC currently has the following side-effects:
935 * - Sets SVGA_REG_BUSY to TRUE (in the monitor)
936 * - Asynchronously wakes up the MKS thread for FIFO processing
937 * - The value written to SYNC is recorded as a "reason", for
940 * If SVGA_FIFO_BUSY is available, drivers are advised to only
941 * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
942 * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
943 * eventually set SVGA_FIFO_BUSY on its own, but this approach
944 * lets the driver avoid sending multiple asynchronous wakeup
945 * messages to the MKS thread.
949 * This register is set to TRUE when SVGA_REG_SYNC is written,
950 * and it reads as FALSE when the FIFO has been completely
953 * Every read from this register causes us to synchronously
954 * process FIFO commands. There is no guarantee as to how many
955 * commands each read will process.
957 * CPU time spent processing FIFO commands will be billed to
960 * New drivers should avoid using this register unless they
961 * need to guarantee that the FIFO is completely drained. It
962 * is overkill for performing a sync-to-fence. Older drivers
963 * will use this register for any type of synchronization.
967 * This register is a fast way for the guest driver to check
968 * whether the FIFO is already being processed. It reads and
969 * writes at normal RAM speeds, with no monitor intervention.
971 * If this register reads as TRUE, the host is guaranteeing that
972 * any new commands written into the FIFO will be noticed before
973 * the MKS goes back to sleep.
975 * If this register reads as FALSE, no such guarantee can be
978 * The guest should use this register to quickly determine
979 * whether or not it needs to wake up the host. If the guest
980 * just wrote a command or group of commands that it would like
981 * the host to begin processing, it should:
983 * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
984 * action is necessary.
986 * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
987 * code that we've already sent a SYNC to the host and we
988 * don't need to send a duplicate.
990 * 3. Write a reason to SVGA_REG_SYNC. This will send an
991 * asynchronous wakeup to the MKS thread.
998 * Fence -- Fence register and command are supported
999 * Accel Front -- Front buffer only commands are supported
1000 * Pitch Lock -- Pitch lock register is supported
1001 * Video -- SVGA Video overlay units are supported
1002 * Escape -- Escape command is supported
1004 * XXX: Add longer descriptions for each capability, including a list
1005 * of the new features that each capability provides.
1007 * SVGA_FIFO_CAP_SCREEN_OBJECT --
1009 * Provides dynamic multi-screen rendering, for improved Unity and
1010 * multi-monitor modes. With Screen Object, the guest can
1011 * dynamically create and destroy 'screens', which can represent
1012 * Unity windows or virtual monitors. Screen Object also provides
1013 * strong guarantees that DMA operations happen only when
1014 * guest-initiated. Screen Object deprecates the BAR1 guest
1015 * framebuffer (GFB) and all commands that work only with the GFB.
1018 * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
1021 * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
1022 * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
1025 * BLIT_SURFACE_TO_SCREEN
1029 * - The host will not read or write guest memory, including the GFB,
1030 * except when explicitly initiated by a DMA command.
1032 * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
1033 * is guaranteed to complete before any subsequent FENCEs.
1035 * - All legacy commands which affect a Screen (UPDATE, PRESENT,
1036 * PRESENT_READBACK) as well as new Screen blit commands will
1037 * all behave consistently as blits, and memory will be read
1038 * or written in FIFO order.
1040 * For example, if you PRESENT from one SVGA3D surface to multiple
1041 * places on the screen, the data copied will always be from the
1042 * SVGA3D surface at the time the PRESENT was issued in the FIFO.
1043 * This was not necessarily true on devices without Screen Object.
1045 * This means that on devices that support Screen Object, the
1046 * PRESENT_READBACK command should not be necessary unless you
1047 * actually want to read back the results of 3D rendering into
1048 * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
1049 * command provides a strict superset of functionality.)
1051 * - When a screen is resized, either using Screen Object commands or
1052 * legacy multimon registers, its contents are preserved.
1054 * SVGA_FIFO_CAP_GMR2 --
1056 * Provides new commands to define and remap guest memory regions (GMR).
1059 * DEFINE_GMR2, REMAP_GMR2.
1061 * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
1063 * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
1064 * This register may replace SVGA_FIFO_3D_HWVERSION on platforms
1065 * that enforce graphics resource limits. This allows the platform
1066 * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
1067 * drivers that do not limit their resources.
1069 * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
1070 * are codependent (and thus we use a single capability bit).
1072 * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
1074 * Modifies the DEFINE_SCREEN command to include a guest provided
1075 * backing store in GMR memory and the bytesPerLine for the backing
1076 * store. This capability requires the use of a backing store when
1077 * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT
1078 * is present then backing stores are optional.
1080 * SVGA_FIFO_CAP_DEAD --
1082 * Drivers should not use this cap bit. This cap bit can not be
1083 * reused since some hosts already expose it.
1086 #define SVGA_FIFO_CAP_NONE 0
1087 #define SVGA_FIFO_CAP_FENCE (1<<0)
1088 #define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
1089 #define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
1090 #define SVGA_FIFO_CAP_VIDEO (1<<3)
1091 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4)
1092 #define SVGA_FIFO_CAP_ESCAPE (1<<5)
1093 #define SVGA_FIFO_CAP_RESERVE (1<<6)
1094 #define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7)
1095 #define SVGA_FIFO_CAP_GMR2 (1<<8)
1096 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
1097 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9)
1098 #define SVGA_FIFO_CAP_DEAD (1<<10)
1104 * Accel Front -- Driver should use front buffer only commands
1107 #define SVGA_FIFO_FLAG_NONE 0
1108 #define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
1109 #define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */
1112 * FIFO reservation sentinel value
1115 #define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
1119 * Video overlay support
1122 #define SVGA_NUM_OVERLAY_UNITS 32
1126 * Video capabilities that the guest is currently using
1129 #define SVGA_VIDEO_FLAG_COLORKEY 0x0001
1133 * Offsets for the video overlay registers
1137 SVGA_VIDEO_ENABLED = 0,
1139 SVGA_VIDEO_DATA_OFFSET,
1141 SVGA_VIDEO_COLORKEY,
1142 SVGA_VIDEO_SIZE, /* Deprecated */
1147 SVGA_VIDEO_SRC_WIDTH,
1148 SVGA_VIDEO_SRC_HEIGHT,
1149 SVGA_VIDEO_DST_X, /* Signed int32 */
1150 SVGA_VIDEO_DST_Y, /* Signed int32 */
1151 SVGA_VIDEO_DST_WIDTH,
1152 SVGA_VIDEO_DST_HEIGHT,
1156 SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
1157 SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
1158 /* (SVGA_ID_INVALID) */
1164 * SVGA Overlay Units
1166 * width and height relate to the entire source video frame.
1167 * srcX, srcY, srcWidth and srcHeight represent subset of the source
1168 * video frame to be displayed.
1172 #include "vmware_pack_begin.h"
1173 struct SVGAOverlayUnit {
1194 #include "vmware_pack_end.h"
1199 * Guest display topology
1201 * XXX: This structure is not part of the SVGA device's interface, and
1202 * doesn't really belong here.
1204 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1206 typedef struct SVGADisplayTopology {
1213 } SVGADisplayTopology;
1217 * SVGAScreenObject --
1219 * This is a new way to represent a guest's multi-monitor screen or
1220 * Unity window. Screen objects are only supported if the
1221 * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
1223 * If Screen Objects are supported, they can be used to fully
1224 * replace the functionality provided by the framebuffer registers
1225 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
1227 * The screen object is a struct with guaranteed binary
1228 * compatibility. New flags can be added, and the struct may grow,
1229 * but existing fields must retain their meaning.
1231 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
1232 * a SVGAGuestPtr that is used to back the screen contents. This
1233 * memory must come from the GFB. The guest is not allowed to
1234 * access the memory and doing so will have undefined results. The
1235 * backing store is required to be page aligned and the size is
1236 * padded to the next page boundry. The number of pages is:
1237 * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
1239 * The pitch in the backingStore is required to be at least large
1240 * enough to hold a 32bbp scanline. It is recommended that the
1241 * driver pad bytesPerLine for a potential performance win.
1243 * The cloneCount field is treated as a hint from the guest that
1244 * the user wants this display to be cloned, countCount times. A
1245 * value of zero means no cloning should happen.
1248 #define SVGA_SCREEN_MUST_BE_SET (1 << 0)
1249 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
1250 #define SVGA_SCREEN_IS_PRIMARY (1 << 1)
1251 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
1254 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
1255 * deactivated the base layer is defined to lose all contents and
1256 * become black. When a screen is deactivated the backing store is
1257 * optional. When set backingPtr and bytesPerLine will be ignored.
1259 #define SVGA_SCREEN_DEACTIVATE (1 << 3)
1262 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set
1263 * the screen contents will be outputted as all black to the user
1264 * though the base layer contents is preserved. The screen base layer
1265 * can still be read and written to like normal though the no visible
1266 * effect will be seen by the user. When the flag is changed the
1267 * screen will be blanked or redrawn to the current contents as needed
1268 * without any extra commands from the driver. This flag only has an
1269 * effect when the screen is not deactivated.
1271 #define SVGA_SCREEN_BLANKING (1 << 4)
1274 #include "vmware_pack_begin.h"
1276 uint32 structSize; /* sizeof(SVGAScreenObject) */
1289 * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
1290 * with SVGA_FIFO_CAP_SCREEN_OBJECT.
1292 SVGAGuestImage backingStore;
1295 * The cloneCount field is treated as a hint from the guest that
1296 * the user wants this display to be cloned, cloneCount times.
1298 * A value of zero means no cloning should happen.
1302 #include "vmware_pack_end.h"
1307 * Commands in the command FIFO:
1309 * Command IDs defined below are used for the traditional 2D FIFO
1310 * communication (not all commands are available for all versions of the
1311 * SVGA FIFO protocol).
1313 * Note the holes in the command ID numbers: These commands have been
1314 * deprecated, and the old IDs must not be reused.
1316 * Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
1319 * Each command's parameters are described by the comments and
1324 SVGA_CMD_INVALID_CMD = 0,
1325 SVGA_CMD_UPDATE = 1,
1326 SVGA_CMD_RECT_COPY = 3,
1327 SVGA_CMD_RECT_ROP_COPY = 14,
1328 SVGA_CMD_DEFINE_CURSOR = 19,
1329 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
1330 SVGA_CMD_UPDATE_VERBOSE = 25,
1331 SVGA_CMD_FRONT_ROP_FILL = 29,
1332 SVGA_CMD_FENCE = 30,
1333 SVGA_CMD_ESCAPE = 33,
1334 SVGA_CMD_DEFINE_SCREEN = 34,
1335 SVGA_CMD_DESTROY_SCREEN = 35,
1336 SVGA_CMD_DEFINE_GMRFB = 36,
1337 SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37,
1338 SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38,
1339 SVGA_CMD_ANNOTATION_FILL = 39,
1340 SVGA_CMD_ANNOTATION_COPY = 40,
1341 SVGA_CMD_DEFINE_GMR2 = 41,
1342 SVGA_CMD_REMAP_GMR2 = 42,
1344 SVGA_CMD_DEAD_2 = 44,
1346 SVGA_CMD_NOP_ERROR = 46,
1350 #define SVGA_CMD_MAX_DATASIZE (256 * 1024)
1351 #define SVGA_CMD_MAX_ARGS 64
1355 * SVGA_CMD_UPDATE --
1357 * This is a DMA transfer which copies from the Guest Framebuffer
1358 * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
1359 * intersect with the provided virtual rectangle.
1361 * This command does not support using arbitrary guest memory as a
1362 * data source- it only works with the pre-defined GFB memory.
1363 * This command also does not support signed virtual coordinates.
1364 * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
1365 * negative root x/y coordinates, the negative portion of those
1366 * screens will not be reachable by this command.
1368 * This command is not necessary when using framebuffer
1369 * traces. Traces are automatically enabled if the SVGA FIFO is
1370 * disabled, and you may explicitly enable/disable traces using
1371 * SVGA_REG_TRACES. With traces enabled, any write to the GFB will
1372 * automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
1374 * Traces and SVGA_CMD_UPDATE are the only supported ways to render
1375 * pseudocolor screen updates. The newer Screen Object commands
1376 * only support true color formats.
1383 #include "vmware_pack_begin.h"
1390 #include "vmware_pack_end.h"
1395 * SVGA_CMD_RECT_COPY --
1397 * Perform a rectangular DMA transfer from one area of the GFB to
1398 * another, and copy the result to any screens which intersect it.
1401 * SVGA_CAP_RECT_COPY
1405 #include "vmware_pack_begin.h"
1414 #include "vmware_pack_end.h"
1415 SVGAFifoCmdRectCopy;
1419 * SVGA_CMD_RECT_ROP_COPY --
1421 * Perform a rectangular DMA transfer from one area of the GFB to
1422 * another, and copy the result to any screens which intersect it.
1423 * The value of ROP may only be SVGA_ROP_COPY, and this command is
1424 * only supported for backwards compatibility reasons.
1427 * SVGA_CAP_RECT_COPY
1431 #include "vmware_pack_begin.h"
1441 #include "vmware_pack_end.h"
1442 SVGAFifoCmdRectRopCopy;
1446 * SVGA_CMD_DEFINE_CURSOR --
1448 * Provide a new cursor image, as an AND/XOR mask.
1450 * The recommended way to position the cursor overlay is by using
1451 * the SVGA_FIFO_CURSOR_* registers, supported by the
1452 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1459 #include "vmware_pack_begin.h"
1461 uint32 id; /* Reserved, must be zero. */
1466 uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */
1467 uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */
1469 * Followed by scanline data for AND mask, then XOR mask.
1470 * Each scanline is padded to a 32-bit boundary.
1473 #include "vmware_pack_end.h"
1474 SVGAFifoCmdDefineCursor;
1478 * SVGA_CMD_DEFINE_ALPHA_CURSOR --
1480 * Provide a new cursor image, in 32-bit BGRA format.
1482 * The recommended way to position the cursor overlay is by using
1483 * the SVGA_FIFO_CURSOR_* registers, supported by the
1484 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1487 * SVGA_CAP_ALPHA_CURSOR
1491 #include "vmware_pack_begin.h"
1493 uint32 id; /* Reserved, must be zero. */
1498 /* Followed by scanline data */
1500 #include "vmware_pack_end.h"
1501 SVGAFifoCmdDefineAlphaCursor;
1505 * SVGA_CMD_UPDATE_VERBOSE --
1507 * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
1508 * 'reason' value, an opaque cookie which is used by internal
1509 * debugging tools. Third party drivers should not use this
1513 * SVGA_CAP_EXTENDED_FIFO
1517 #include "vmware_pack_begin.h"
1525 #include "vmware_pack_end.h"
1526 SVGAFifoCmdUpdateVerbose;
1530 * SVGA_CMD_FRONT_ROP_FILL --
1532 * This is a hint which tells the SVGA device that the driver has
1533 * just filled a rectangular region of the GFB with a solid
1534 * color. Instead of reading these pixels from the GFB, the device
1535 * can assume that they all equal 'color'. This is primarily used
1536 * for remote desktop protocols.
1539 * SVGA_FIFO_CAP_ACCELFRONT
1542 #define SVGA_ROP_COPY 0x03
1545 #include "vmware_pack_begin.h"
1547 uint32 color; /* In the same format as the GFB */
1552 uint32 rop; /* Must be SVGA_ROP_COPY */
1554 #include "vmware_pack_end.h"
1555 SVGAFifoCmdFrontRopFill;
1561 * Insert a synchronization fence. When the SVGA device reaches
1562 * this command, it will copy the 'fence' value into the
1563 * SVGA_FIFO_FENCE register. It will also compare the fence against
1564 * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
1565 * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
1566 * raise this interrupt.
1569 * SVGA_FIFO_FENCE for this command,
1570 * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
1574 #include "vmware_pack_begin.h"
1578 #include "vmware_pack_end.h"
1583 * SVGA_CMD_ESCAPE --
1585 * Send an extended or vendor-specific variable length command.
1586 * This is used for video overlay, third party plugins, and
1587 * internal debugging tools. See svga_escape.h
1590 * SVGA_FIFO_CAP_ESCAPE
1594 #include "vmware_pack_begin.h"
1598 /* followed by 'size' bytes of data */
1600 #include "vmware_pack_end.h"
1605 * SVGA_CMD_DEFINE_SCREEN --
1607 * Define or redefine an SVGAScreenObject. See the description of
1608 * SVGAScreenObject above. The video driver is responsible for
1609 * generating new screen IDs. They should be small positive
1610 * integers. The virtual device will have an implementation
1611 * specific upper limit on the number of screen IDs
1612 * supported. Drivers are responsible for recycling IDs. The first
1615 * - Interaction with other registers:
1617 * For backwards compatibility, when the GFB mode registers (WIDTH,
1618 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1619 * deletes all screens other than screen #0, and redefines screen
1620 * #0 according to the specified mode. Drivers that use
1621 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
1623 * If you use screen objects, do not use the legacy multi-mon
1624 * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
1627 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1631 #include "vmware_pack_begin.h"
1633 SVGAScreenObject screen; /* Variable-length according to version */
1635 #include "vmware_pack_end.h"
1636 SVGAFifoCmdDefineScreen;
1640 * SVGA_CMD_DESTROY_SCREEN --
1642 * Destroy an SVGAScreenObject. Its ID is immediately available for
1646 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1650 #include "vmware_pack_begin.h"
1654 #include "vmware_pack_end.h"
1655 SVGAFifoCmdDestroyScreen;
1659 * SVGA_CMD_DEFINE_GMRFB --
1661 * This command sets a piece of SVGA device state called the
1662 * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
1663 * piece of light-weight state which identifies the location and
1664 * format of an image in guest memory or in BAR1. The GMRFB has
1665 * an arbitrary size, and it doesn't need to match the geometry
1666 * of the GFB or any screen object.
1668 * The GMRFB can be redefined as often as you like. You could
1669 * always use the same GMRFB, you could redefine it before
1670 * rendering from a different guest screen, or you could even
1671 * redefine it before every blit.
1673 * There are multiple ways to use this command. The simplest way is
1674 * to use it to move the framebuffer either to elsewhere in the GFB
1675 * (BAR1) memory region, or to a user-defined GMR. This lets a
1676 * driver use a framebuffer allocated entirely out of normal system
1677 * memory, which we encourage.
1679 * Another way to use this command is to set up a ring buffer of
1680 * updates in GFB memory. If a driver wants to ensure that no
1681 * frames are skipped by the SVGA device, it is important that the
1682 * driver not modify the source data for a blit until the device is
1683 * done processing the command. One efficient way to accomplish
1684 * this is to use a ring of small DMA buffers. Each buffer is used
1685 * for one blit, then we move on to the next buffer in the
1686 * ring. The FENCE mechanism is used to protect each buffer from
1687 * re-use until the device is finished with that buffer's
1688 * corresponding blit.
1690 * This command does not affect the meaning of SVGA_CMD_UPDATE.
1691 * UPDATEs always occur from the legacy GFB memory area. This
1692 * command has no support for pseudocolor GMRFBs. Currently only
1693 * true-color 15, 16, and 24-bit depths are supported. Future
1694 * devices may expose capabilities for additional framebuffer
1697 * The default GMRFB value is undefined. Drivers must always send
1698 * this command at least once before performing any blit from the
1702 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1706 #include "vmware_pack_begin.h"
1709 uint32 bytesPerLine;
1710 SVGAGMRImageFormat format;
1712 #include "vmware_pack_end.h"
1713 SVGAFifoCmdDefineGMRFB;
1717 * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
1719 * This is a guest-to-host blit. It performs a DMA operation to
1720 * copy a rectangular region of pixels from the current GMRFB to
1723 * The destination coordinate may be specified relative to a
1724 * screen's origin. The provided screen ID must be valid.
1726 * The SVGA device is guaranteed to finish reading from the GMRFB
1727 * by the time any subsequent FENCE commands are reached.
1729 * This command consumes an annotation. See the
1730 * SVGA_CMD_ANNOTATION_* commands for details.
1733 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1737 #include "vmware_pack_begin.h"
1739 SVGASignedPoint srcOrigin;
1740 SVGASignedRect destRect;
1741 uint32 destScreenId;
1743 #include "vmware_pack_end.h"
1744 SVGAFifoCmdBlitGMRFBToScreen;
1748 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
1750 * This is a host-to-guest blit. It performs a DMA operation to
1751 * copy a rectangular region of pixels from a single ScreenObject
1752 * back to the current GMRFB.
1754 * The source coordinate is specified relative to a screen's
1755 * origin. The provided screen ID must be valid. If any parameters
1756 * are invalid, the resulting pixel values are undefined.
1758 * The SVGA device is guaranteed to finish writing to the GMRFB by
1759 * the time any subsequent FENCE commands are reached.
1762 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1766 #include "vmware_pack_begin.h"
1768 SVGASignedPoint destOrigin;
1769 SVGASignedRect srcRect;
1772 #include "vmware_pack_end.h"
1773 SVGAFifoCmdBlitScreenToGMRFB;
1777 * SVGA_CMD_ANNOTATION_FILL --
1779 * The annotation commands have been deprecated, should not be used
1780 * by new drivers. They used to provide performance hints to the SVGA
1781 * device about the content of screen updates, but newer SVGA devices
1785 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1789 #include "vmware_pack_begin.h"
1791 SVGAColorBGRX color;
1793 #include "vmware_pack_end.h"
1794 SVGAFifoCmdAnnotationFill;
1798 * SVGA_CMD_ANNOTATION_COPY --
1800 * The annotation commands have been deprecated, should not be used
1801 * by new drivers. They used to provide performance hints to the SVGA
1802 * device about the content of screen updates, but newer SVGA devices
1806 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1810 #include "vmware_pack_begin.h"
1812 SVGASignedPoint srcOrigin;
1815 #include "vmware_pack_end.h"
1816 SVGAFifoCmdAnnotationCopy;
1820 * SVGA_CMD_DEFINE_GMR2 --
1822 * Define guest memory region v2. See the description of GMRs above.
1829 #include "vmware_pack_begin.h"
1834 #include "vmware_pack_end.h"
1835 SVGAFifoCmdDefineGMR2;
1839 * SVGA_CMD_REMAP_GMR2 --
1841 * Remap guest memory region v2. See the description of GMRs above.
1843 * This command allows guest to modify a portion of an existing GMR by
1844 * invalidating it or reassigning it to different guest physical pages.
1845 * The pages are identified by physical page number (PPN). The pages
1846 * are assumed to be pinned and valid for DMA operations.
1848 * Description of command flags:
1850 * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
1851 * The PPN list must not overlap with the remap region (this can be
1852 * handled trivially by referencing a separate GMR). If flag is
1853 * disabled, PPN list is appended to SVGARemapGMR command.
1855 * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
1856 * it is in PPN32 format.
1858 * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
1859 * A single PPN can be used to invalidate a portion of a GMR or
1860 * map it to to a single guest scratch page.
1867 SVGA_REMAP_GMR2_PPN32 = 0,
1868 SVGA_REMAP_GMR2_VIA_GMR = (1 << 0),
1869 SVGA_REMAP_GMR2_PPN64 = (1 << 1),
1870 SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2),
1871 } SVGARemapGMR2Flags;
1874 #include "vmware_pack_begin.h"
1877 SVGARemapGMR2Flags flags;
1878 uint32 offsetPages; /* offset in pages to begin remap */
1879 uint32 numPages; /* number of pages to remap */
1881 * Followed by additional data depending on SVGARemapGMR2Flags.
1883 * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
1884 * Otherwise an array of page descriptors in PPN32 or PPN64 format
1885 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
1886 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
1889 #include "vmware_pack_end.h"
1890 SVGAFifoCmdRemapGMR2;
1894 * Size of SVGA device memory such as frame buffer and FIFO.
1896 #define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */
1897 #define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
1898 #define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
1899 #define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
1900 #define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
1901 #define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
1902 #define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
1903 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
1905 #define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
1908 * To simplify autoDetect display configuration, support a minimum of
1909 * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
1911 * maxWidth = numDisplay * 1920 = 3840
1912 * maxHeight = rotated width of single monitor = 1920
1913 * vramSize = maxWidth * maxHeight * 4 = 29491200
1915 #define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
1917 #if defined(VMX86_SERVER)
1918 #define SVGA_VRAM_SIZE (4 * 1024 * 1024)
1919 #define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
1920 #define SVGA_FIFO_SIZE (256 * 1024)
1921 #define SVGA_FIFO_SIZE_3D (516 * 1024)
1922 #define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
1923 #define SVGA_AUTODETECT_DEFAULT FALSE
1925 #define SVGA_VRAM_SIZE (16 * 1024 * 1024)
1926 #define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
1927 #define SVGA_FIFO_SIZE (2 * 1024 * 1024)
1928 #define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
1929 #define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
1930 #define SVGA_AUTODETECT_DEFAULT TRUE
1933 #define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
1934 #define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)