2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 plane module
12 * Each DRM plane is a layer of pixels being scanned out by the HVS.
14 * At atomic modeset check time, we compute the HVS display element
15 * state that would be necessary for displaying the plane (giving us a
16 * chance to figure out if a plane configuration is invalid), then at
17 * atomic flush time the CRTC will ask us to write our element state
18 * into the region of the HVS that it has allocated for us.
23 #include "drm_atomic_helper.h"
24 #include "drm_fb_cma_helper.h"
25 #include "drm_plane_helper.h"
27 enum vc4_scaling_mode {
33 struct vc4_plane_state {
34 struct drm_plane_state base;
35 /* System memory copy of the display list for this element, computed
36 * at atomic_check time.
39 u32 dlist_size; /* Number of dwords allocated for the display list */
40 u32 dlist_count; /* Number of used dwords in the display list. */
42 /* Offset in the dlist to various words, for pageflip or
49 /* Offset where the plane's dlist was last stored in the
50 * hardware at vc4_crtc_atomic_flush() time.
52 u32 __iomem *hw_dlist;
54 /* Clipped coordinates of the plane on the display. */
55 int crtc_x, crtc_y, crtc_w, crtc_h;
56 /* Clipped area being scanned from in the FB. */
59 u32 src_w[2], src_h[2];
61 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
62 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
66 /* Offset to start scanning out from the start of the plane's
71 /* Our allocation in LBM for temporary storage during scaling. */
72 struct drm_mm_node lbm;
75 static inline struct vc4_plane_state *
76 to_vc4_plane_state(struct drm_plane_state *state)
78 return (struct vc4_plane_state *)state;
81 static const struct hvs_format {
82 u32 drm; /* DRM_FORMAT_* */
83 u32 hvs; /* HVS_FORMAT_* */
89 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
90 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
93 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
94 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
97 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
98 .pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = true,
101 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
102 .pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = false,
105 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
106 .pixel_order = HVS_PIXEL_ORDER_XRGB, .has_alpha = false,
109 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
110 .pixel_order = HVS_PIXEL_ORDER_XBGR, .has_alpha = false,
113 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
114 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
117 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
118 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
121 .drm = DRM_FORMAT_YUV422,
122 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
125 .drm = DRM_FORMAT_YVU422,
126 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
130 .drm = DRM_FORMAT_YUV420,
131 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
134 .drm = DRM_FORMAT_YVU420,
135 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
139 .drm = DRM_FORMAT_NV12,
140 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
143 .drm = DRM_FORMAT_NV16,
144 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
148 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
152 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
153 if (hvs_formats[i].drm == drm_format)
154 return &hvs_formats[i];
160 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
163 return VC4_SCALING_PPF;
165 return VC4_SCALING_TPZ;
167 return VC4_SCALING_NONE;
170 static bool plane_enabled(struct drm_plane_state *state)
172 return state->fb && state->crtc;
175 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
177 struct vc4_plane_state *vc4_state;
179 if (WARN_ON(!plane->state))
182 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
186 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
188 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
190 if (vc4_state->dlist) {
191 vc4_state->dlist = kmemdup(vc4_state->dlist,
192 vc4_state->dlist_count * 4,
194 if (!vc4_state->dlist) {
198 vc4_state->dlist_size = vc4_state->dlist_count;
201 return &vc4_state->base;
204 static void vc4_plane_destroy_state(struct drm_plane *plane,
205 struct drm_plane_state *state)
207 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
208 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
210 if (vc4_state->lbm.allocated) {
211 unsigned long irqflags;
213 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
214 drm_mm_remove_node(&vc4_state->lbm);
215 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
218 kfree(vc4_state->dlist);
219 __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
223 /* Called during init to allocate the plane's atomic state. */
224 static void vc4_plane_reset(struct drm_plane *plane)
226 struct vc4_plane_state *vc4_state;
228 WARN_ON(plane->state);
230 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
234 plane->state = &vc4_state->base;
235 vc4_state->base.plane = plane;
238 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
240 if (vc4_state->dlist_count == vc4_state->dlist_size) {
241 u32 new_size = max(4u, vc4_state->dlist_count * 2);
242 u32 *new_dlist = kmalloc(new_size * 4, GFP_KERNEL);
246 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
248 kfree(vc4_state->dlist);
249 vc4_state->dlist = new_dlist;
250 vc4_state->dlist_size = new_size;
253 vc4_state->dlist[vc4_state->dlist_count++] = val;
256 /* Returns the scl0/scl1 field based on whether the dimensions need to
257 * be up/down/non-scaled.
259 * This is a replication of a table from the spec.
261 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
263 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
265 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
266 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
267 return SCALER_CTL0_SCL_H_PPF_V_PPF;
268 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
269 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
270 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
271 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
272 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
273 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
274 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
275 return SCALER_CTL0_SCL_H_PPF_V_NONE;
276 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
277 return SCALER_CTL0_SCL_H_NONE_V_PPF;
278 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
279 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
280 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
281 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
283 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
284 /* The unity case is independently handled by
291 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
293 struct drm_plane *plane = state->plane;
294 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
295 struct drm_framebuffer *fb = state->fb;
296 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
297 u32 subpixel_src_mask = (1 << 16) - 1;
298 u32 format = fb->pixel_format;
299 int num_planes = drm_format_num_planes(format);
304 for (i = 0; i < num_planes; i++)
305 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
307 /* We don't support subpixel source positioning for scaling. */
308 if ((state->src_x & subpixel_src_mask) ||
309 (state->src_y & subpixel_src_mask) ||
310 (state->src_w & subpixel_src_mask) ||
311 (state->src_h & subpixel_src_mask)) {
315 vc4_state->src_x = state->src_x >> 16;
316 vc4_state->src_y = state->src_y >> 16;
317 vc4_state->src_w[0] = state->src_w >> 16;
318 vc4_state->src_h[0] = state->src_h >> 16;
320 vc4_state->crtc_x = state->crtc_x;
321 vc4_state->crtc_y = state->crtc_y;
322 vc4_state->crtc_w = state->crtc_w;
323 vc4_state->crtc_h = state->crtc_h;
325 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
327 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
330 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
331 vc4_state->y_scaling[0] == VC4_SCALING_NONE);
333 if (num_planes > 1) {
334 vc4_state->is_yuv = true;
336 h_subsample = drm_format_horz_chroma_subsampling(format);
337 v_subsample = drm_format_vert_chroma_subsampling(format);
338 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
339 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
341 vc4_state->x_scaling[1] =
342 vc4_get_scaling_mode(vc4_state->src_w[1],
344 vc4_state->y_scaling[1] =
345 vc4_get_scaling_mode(vc4_state->src_h[1],
348 /* YUV conversion requires that horizontal scaling be enabled
349 * on the UV plane even if vc4_get_scaling_mode() returned
350 * VC4_SCALING_NONE (which can happen when the down-scaling
351 * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
354 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
355 vc4_state->x_scaling[1] = VC4_SCALING_PPF;
357 vc4_state->is_yuv = false;
358 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
359 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
362 /* No configuring scaling on the cursor plane, since it gets
363 non-vblank-synced updates, and scaling requires requires
364 LBM changes which have to be vblank-synced.
366 if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
369 /* Clamp the on-screen start x/y to 0. The hardware doesn't
370 * support negative y, and negative x wastes bandwidth.
372 if (vc4_state->crtc_x < 0) {
373 for (i = 0; i < num_planes; i++) {
374 u32 cpp = drm_format_plane_cpp(fb->pixel_format, i);
375 u32 subs = ((i == 0) ? 1 : h_subsample);
377 vc4_state->offsets[i] += (cpp *
378 (-vc4_state->crtc_x) / subs);
380 vc4_state->src_w[0] += vc4_state->crtc_x;
381 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
382 vc4_state->crtc_x = 0;
385 if (vc4_state->crtc_y < 0) {
386 for (i = 0; i < num_planes; i++) {
387 u32 subs = ((i == 0) ? 1 : v_subsample);
389 vc4_state->offsets[i] += (fb->pitches[i] *
390 (-vc4_state->crtc_y) / subs);
392 vc4_state->src_h[0] += vc4_state->crtc_y;
393 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
394 vc4_state->crtc_y = 0;
400 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
404 scale = (1 << 16) * src / dst;
406 /* The specs note that while the reciprocal would be defined
407 * as (1<<32)/scale, ~0 is close enough.
411 vc4_dlist_write(vc4_state,
412 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
413 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
414 vc4_dlist_write(vc4_state,
415 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
418 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
420 u32 scale = (1 << 16) * src / dst;
422 vc4_dlist_write(vc4_state,
424 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
425 VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
428 static u32 vc4_lbm_size(struct drm_plane_state *state)
430 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
431 /* This is the worst case number. One of the two sizes will
432 * be used depending on the scaling configuration.
434 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
437 if (!vc4_state->is_yuv) {
438 if (vc4_state->is_unity)
440 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
441 lbm = pix_per_line * 8;
443 /* In special cases, this multiplier might be 12. */
444 lbm = pix_per_line * 16;
447 /* There are cases for this going down to a multiplier
448 * of 2, but according to the firmware source, the
449 * table in the docs is somewhat wrong.
451 lbm = pix_per_line * 16;
454 lbm = roundup(lbm, 32);
459 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
462 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
464 /* Ch0 H-PPF Word 0: Scaling Parameters */
465 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
466 vc4_write_ppf(vc4_state,
467 vc4_state->src_w[channel], vc4_state->crtc_w);
470 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
471 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
472 vc4_write_ppf(vc4_state,
473 vc4_state->src_h[channel], vc4_state->crtc_h);
474 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
477 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
478 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
479 vc4_write_tpz(vc4_state,
480 vc4_state->src_w[channel], vc4_state->crtc_w);
483 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
484 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
485 vc4_write_tpz(vc4_state,
486 vc4_state->src_h[channel], vc4_state->crtc_h);
487 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
491 /* Writes out a full display list for an active plane to the plane's
492 * private dlist state.
494 static int vc4_plane_mode_set(struct drm_plane *plane,
495 struct drm_plane_state *state)
497 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
498 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
499 struct drm_framebuffer *fb = state->fb;
500 u32 ctl0_offset = vc4_state->dlist_count;
501 const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
502 int num_planes = drm_format_num_planes(format->drm);
505 unsigned long irqflags;
508 ret = vc4_plane_setup_clipping_and_scaling(state);
512 /* Allocate the LBM memory that the HVS will use for temporary
513 * storage due to our scaling/format conversion.
515 lbm_size = vc4_lbm_size(state);
517 if (!vc4_state->lbm.allocated) {
518 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
519 ret = drm_mm_insert_node(&vc4->hvs->lbm_mm,
522 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
524 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
531 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB
532 * and 4:4:4, scl1 should be set to scl0 so both channels of
533 * the scaler do the same thing. For YUV, the Y plane needs
534 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
535 * the scl fields here.
537 if (num_planes == 1) {
538 scl0 = vc4_get_scl_field(state, 0);
541 scl0 = vc4_get_scl_field(state, 1);
542 scl1 = vc4_get_scl_field(state, 0);
546 vc4_dlist_write(vc4_state,
548 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
549 (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
550 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
551 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
552 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
554 /* Position Word 0: Image Positions and Alpha Value */
555 vc4_state->pos0_offset = vc4_state->dlist_count;
556 vc4_dlist_write(vc4_state,
557 VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
558 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
559 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
561 /* Position Word 1: Scaled Image Dimensions. */
562 if (!vc4_state->is_unity) {
563 vc4_dlist_write(vc4_state,
564 VC4_SET_FIELD(vc4_state->crtc_w,
565 SCALER_POS1_SCL_WIDTH) |
566 VC4_SET_FIELD(vc4_state->crtc_h,
567 SCALER_POS1_SCL_HEIGHT));
570 /* Position Word 2: Source Image Size, Alpha Mode */
571 vc4_state->pos2_offset = vc4_state->dlist_count;
572 vc4_dlist_write(vc4_state,
573 VC4_SET_FIELD(format->has_alpha ?
574 SCALER_POS2_ALPHA_MODE_PIPELINE :
575 SCALER_POS2_ALPHA_MODE_FIXED,
576 SCALER_POS2_ALPHA_MODE) |
577 VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
578 VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
580 /* Position Word 3: Context. Written by the HVS. */
581 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
584 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
586 * The pointers may be any byte address.
588 vc4_state->ptr0_offset = vc4_state->dlist_count;
589 if (!format->flip_cbcr) {
590 for (i = 0; i < num_planes; i++)
591 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
593 WARN_ON_ONCE(num_planes != 3);
594 vc4_dlist_write(vc4_state, vc4_state->offsets[0]);
595 vc4_dlist_write(vc4_state, vc4_state->offsets[2]);
596 vc4_dlist_write(vc4_state, vc4_state->offsets[1]);
599 /* Pointer Context Word 0/1/2: Written by the HVS */
600 for (i = 0; i < num_planes; i++)
601 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
603 /* Pitch word 0/1/2 */
604 for (i = 0; i < num_planes; i++) {
605 vc4_dlist_write(vc4_state,
606 VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
609 /* Colorspace conversion words */
610 if (vc4_state->is_yuv) {
611 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
612 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
613 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
616 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
617 vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
618 vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
619 vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
620 /* LBM Base Address. */
621 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
622 vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
623 vc4_dlist_write(vc4_state, vc4_state->lbm.start);
626 if (num_planes > 1) {
627 /* Emit Cb/Cr as channel 0 and Y as channel
628 * 1. This matches how we set up scl0/scl1
631 vc4_write_scaling_parameters(state, 1);
633 vc4_write_scaling_parameters(state, 0);
635 /* If any PPF setup was done, then all the kernel
636 * pointers get uploaded.
638 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
639 vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
640 vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
641 vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
642 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
643 SCALER_PPF_KERNEL_OFFSET);
646 vc4_dlist_write(vc4_state, kernel);
648 vc4_dlist_write(vc4_state, kernel);
650 vc4_dlist_write(vc4_state, kernel);
652 vc4_dlist_write(vc4_state, kernel);
656 vc4_state->dlist[ctl0_offset] |=
657 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
662 /* If a modeset involves changing the setup of a plane, the atomic
663 * infrastructure will call this to validate a proposed plane setup.
664 * However, if a plane isn't getting updated, this (and the
665 * corresponding vc4_plane_atomic_update) won't get called. Thus, we
666 * compute the dlist here and have all active plane dlists get updated
667 * in the CRTC's flush.
669 static int vc4_plane_atomic_check(struct drm_plane *plane,
670 struct drm_plane_state *state)
672 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
674 vc4_state->dlist_count = 0;
676 if (plane_enabled(state))
677 return vc4_plane_mode_set(plane, state);
682 static void vc4_plane_atomic_update(struct drm_plane *plane,
683 struct drm_plane_state *old_state)
685 /* No contents here. Since we don't know where in the CRTC's
686 * dlist we should be stored, our dlist is uploaded to the
687 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
692 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
694 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
697 vc4_state->hw_dlist = dlist;
699 /* Can't memcpy_toio() because it needs to be 32-bit writes. */
700 for (i = 0; i < vc4_state->dlist_count; i++)
701 writel(vc4_state->dlist[i], &dlist[i]);
703 return vc4_state->dlist_count;
706 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
708 const struct vc4_plane_state *vc4_state =
709 container_of(state, typeof(*vc4_state), base);
711 return vc4_state->dlist_count;
714 /* Updates the plane to immediately (well, once the FIFO needs
715 * refilling) scan out from at a new framebuffer.
717 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
719 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
720 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
723 /* We're skipping the address adjustment for negative origin,
724 * because this is only called on the primary plane.
726 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
727 addr = bo->paddr + fb->offsets[0];
729 /* Write the new address into the hardware immediately. The
730 * scanout will start from this address as soon as the FIFO
731 * needs to refill with pixels.
733 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
735 /* Also update the CPU-side dlist copy, so that any later
736 * atomic updates that don't do a new modeset on our plane
737 * also use our updated address.
739 vc4_state->dlist[vc4_state->ptr0_offset] = addr;
742 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
743 .atomic_check = vc4_plane_atomic_check,
744 .atomic_update = vc4_plane_atomic_update,
747 static void vc4_plane_destroy(struct drm_plane *plane)
749 drm_plane_helper_disable(plane);
750 drm_plane_cleanup(plane);
753 /* Implements immediate (non-vblank-synced) updates of the cursor
754 * position, or falls back to the atomic helper otherwise.
757 vc4_update_plane(struct drm_plane *plane,
758 struct drm_crtc *crtc,
759 struct drm_framebuffer *fb,
760 int crtc_x, int crtc_y,
761 unsigned int crtc_w, unsigned int crtc_h,
762 uint32_t src_x, uint32_t src_y,
763 uint32_t src_w, uint32_t src_h)
765 struct drm_plane_state *plane_state;
766 struct vc4_plane_state *vc4_state;
768 if (plane != crtc->cursor)
771 plane_state = plane->state;
772 vc4_state = to_vc4_plane_state(plane_state);
777 /* If we're changing the cursor contents, do that in the
778 * normal vblank-synced atomic path.
780 if (fb != plane_state->fb)
783 /* No configuring new scaling in the fast path. */
784 if (crtc_w != plane_state->crtc_w ||
785 crtc_h != plane_state->crtc_h ||
786 src_w != plane_state->src_w ||
787 src_h != plane_state->src_h) {
791 /* Set the cursor's position on the screen. This is the
792 * expected change from the drm_mode_cursor_universal()
795 plane_state->crtc_x = crtc_x;
796 plane_state->crtc_y = crtc_y;
798 /* Allow changing the start position within the cursor BO, if
801 plane_state->src_x = src_x;
802 plane_state->src_y = src_y;
804 /* Update the display list based on the new crtc_x/y. */
805 vc4_plane_atomic_check(plane, plane_state);
807 /* Note that we can't just call vc4_plane_write_dlist()
808 * because that would smash the context data that the HVS is
811 writel(vc4_state->dlist[vc4_state->pos0_offset],
812 &vc4_state->hw_dlist[vc4_state->pos0_offset]);
813 writel(vc4_state->dlist[vc4_state->pos2_offset],
814 &vc4_state->hw_dlist[vc4_state->pos2_offset]);
815 writel(vc4_state->dlist[vc4_state->ptr0_offset],
816 &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
821 return drm_atomic_helper_update_plane(plane, crtc, fb,
828 static const struct drm_plane_funcs vc4_plane_funcs = {
829 .update_plane = vc4_update_plane,
830 .disable_plane = drm_atomic_helper_disable_plane,
831 .destroy = vc4_plane_destroy,
832 .set_property = NULL,
833 .reset = vc4_plane_reset,
834 .atomic_duplicate_state = vc4_plane_duplicate_state,
835 .atomic_destroy_state = vc4_plane_destroy_state,
838 struct drm_plane *vc4_plane_init(struct drm_device *dev,
839 enum drm_plane_type type)
841 struct drm_plane *plane = NULL;
842 struct vc4_plane *vc4_plane;
843 u32 formats[ARRAY_SIZE(hvs_formats)];
848 vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
855 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
856 /* Don't allow YUV in cursor planes, since that means
857 * tuning on the scaler, which we don't allow for the
860 if (type != DRM_PLANE_TYPE_CURSOR ||
861 hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
862 formats[num_formats++] = hvs_formats[i].drm;
865 plane = &vc4_plane->base;
866 ret = drm_universal_plane_init(dev, plane, 0xff,
868 formats, num_formats,
871 drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
876 vc4_plane_destroy(plane);