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25 * DOC: Interrupt management for the V3D engine
27 * We have an interrupt status register (V3D_INTCTL) which reports
28 * interrupts, and where writing 1 bits clears those interrupts.
29 * There are also a pair of interrupt registers
30 * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
31 * disables that specific interrupt, and 0s written are ignored
32 * (reading either one returns the set of enabled interrupts).
34 * When we take a binning flush done interrupt, we need to submit the
35 * next frame for binning and move the finished frame to the render
38 * When we take a render frame interrupt, we need to wake the
39 * processes waiting for some frame to be done, and get the next frame
40 * submitted ASAP (so the hardware doesn't sit idle when there's work
43 * When we take the binner out of memory interrupt, we need to
44 * allocate some new memory and pass it to the binner so that the
45 * current job can make progress.
51 #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
55 DECLARE_WAIT_QUEUE_HEAD(render_wait);
58 vc4_overflow_mem_work(struct work_struct *work)
61 container_of(work, struct vc4_dev, overflow_mem_work);
62 struct vc4_bo *bo = vc4->bin_bo;
64 struct vc4_exec_info *exec;
65 unsigned long irqflags;
67 bin_bo_slot = vc4_v3d_get_bin_slot(vc4);
68 if (bin_bo_slot < 0) {
69 DRM_ERROR("Couldn't allocate binner overflow mem\n");
73 spin_lock_irqsave(&vc4->job_lock, irqflags);
75 if (vc4->bin_alloc_overflow) {
76 /* If we had overflow memory allocated previously,
77 * then that chunk will free when the current bin job
78 * is done. If we don't have a bin job running, then
79 * the chunk will be done whenever the list of render
82 exec = vc4_first_bin_job(vc4);
84 exec = vc4_last_render_job(vc4);
86 exec->bin_slots |= vc4->bin_alloc_overflow;
88 /* There's nothing queued in the hardware, so
89 * the old slot is free immediately.
91 vc4->bin_alloc_used &= ~vc4->bin_alloc_overflow;
94 vc4->bin_alloc_overflow = BIT(bin_bo_slot);
96 V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size);
97 V3D_WRITE(V3D_BPOS, bo->base.base.size);
98 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
99 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
100 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
104 vc4_irq_finish_bin_job(struct drm_device *dev)
106 struct vc4_dev *vc4 = to_vc4_dev(dev);
107 struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
112 vc4_move_job_to_render(dev, exec);
113 vc4_submit_next_bin_job(dev);
117 vc4_cancel_bin_job(struct drm_device *dev)
119 struct vc4_dev *vc4 = to_vc4_dev(dev);
120 struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
125 list_move_tail(&exec->head, &vc4->bin_job_list);
126 vc4_submit_next_bin_job(dev);
130 vc4_irq_finish_render_job(struct drm_device *dev)
132 struct vc4_dev *vc4 = to_vc4_dev(dev);
133 struct vc4_exec_info *exec = vc4_first_render_job(vc4);
138 vc4->finished_seqno++;
139 list_move_tail(&exec->head, &vc4->job_done_list);
141 dma_fence_signal_locked(exec->fence);
142 dma_fence_put(exec->fence);
145 vc4_submit_next_render_job(dev);
147 wake_up_all(&vc4->job_wait_queue);
148 schedule_work(&vc4->job_done_work);
152 vc4_irq(int irq, void *arg)
154 struct drm_device *dev = arg;
155 struct vc4_dev *vc4 = to_vc4_dev(dev);
157 irqreturn_t status = IRQ_NONE;
160 intctl = V3D_READ(V3D_INTCTL);
162 /* Acknowledge the interrupts we're handling here. The binner
163 * last flush / render frame done interrupt will be cleared,
164 * while OUTOMEM will stay high until the underlying cause is
167 V3D_WRITE(V3D_INTCTL, intctl);
169 if (intctl & V3D_INT_OUTOMEM) {
170 /* Disable OUTOMEM until the work is done. */
171 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
172 schedule_work(&vc4->overflow_mem_work);
173 status = IRQ_HANDLED;
176 if (intctl & V3D_INT_FLDONE) {
177 spin_lock(&vc4->job_lock);
178 vc4_irq_finish_bin_job(dev);
179 spin_unlock(&vc4->job_lock);
180 status = IRQ_HANDLED;
183 if (intctl & V3D_INT_FRDONE) {
184 spin_lock(&vc4->job_lock);
185 vc4_irq_finish_render_job(dev);
186 spin_unlock(&vc4->job_lock);
187 status = IRQ_HANDLED;
194 vc4_irq_preinstall(struct drm_device *dev)
196 struct vc4_dev *vc4 = to_vc4_dev(dev);
198 init_waitqueue_head(&vc4->job_wait_queue);
199 INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
201 /* Clear any pending interrupts someone might have left around
204 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
208 vc4_irq_postinstall(struct drm_device *dev)
210 struct vc4_dev *vc4 = to_vc4_dev(dev);
212 /* Enable both the render done and out of memory interrupts. */
213 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
219 vc4_irq_uninstall(struct drm_device *dev)
221 struct vc4_dev *vc4 = to_vc4_dev(dev);
223 /* Disable sending interrupts for our driver's IRQs. */
224 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
226 /* Clear any pending interrupts we might have left. */
227 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
229 /* Finish any interrupt handler still in flight. */
230 disable_irq(dev->irq);
232 cancel_work_sync(&vc4->overflow_mem_work);
235 /** Reinitializes interrupt registers when a GPU reset is performed. */
236 void vc4_irq_reset(struct drm_device *dev)
238 struct vc4_dev *vc4 = to_vc4_dev(dev);
239 unsigned long irqflags;
241 /* Acknowledge any stale IRQs. */
242 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
245 * Turn all our interrupts on. Binner out of memory is the
246 * only one we expect to trigger at this point, since we've
247 * just come from poweron and haven't supplied any overflow
250 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
252 spin_lock_irqsave(&vc4->job_lock, irqflags);
253 vc4_cancel_bin_job(dev);
254 vc4_irq_finish_render_job(dev);
255 spin_unlock_irqrestore(&vc4->job_lock, irqflags);