drivers/gpu/drm/tilcdc/tilcdc_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /* LCDC DRM driver, based on da8xx-fb */
  19
  20 #include <linux/component.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/suspend.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27
  28 #include "tilcdc_drv.h"
  29 #include "tilcdc_regs.h"
  30 #include "tilcdc_tfp410.h"
  31 #include "tilcdc_panel.h"
  32 #include "tilcdc_external.h"
  33
  34 static LIST_HEAD(module_list);
  35
  36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  37
  38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  39                                                DRM_FORMAT_BGR888,
  40                                                DRM_FORMAT_XBGR8888 };
  41
  42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  43                                               DRM_FORMAT_RGB888,
  44                                               DRM_FORMAT_XRGB8888 };
  45
  46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  47                                              DRM_FORMAT_RGB888,
  48                                              DRM_FORMAT_XRGB8888 };
  49
  50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  51                 const struct tilcdc_module_ops *funcs)
  52 {
  53         mod->name = name;
  54         mod->funcs = funcs;
  55         INIT_LIST_HEAD(&mod->list);
  56         list_add(&mod->list, &module_list);
  57 }
  58
  59 void tilcdc_module_cleanup(struct tilcdc_module *mod)
  60 {
  61         list_del(&mod->list);
  62 }
  63
  64 static struct of_device_id tilcdc_of_match[];
  65
  66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  67                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  68 {
  69         return drm_gem_fb_create(dev, file_priv, mode_cmd);
  70 }
  71
  72 static int tilcdc_atomic_check(struct drm_device *dev,
  73                                struct drm_atomic_state *state)
  74 {
  75         int ret;
  76
  77         ret = drm_atomic_helper_check_modeset(dev, state);
  78         if (ret)
  79                 return ret;
  80
  81         ret = drm_atomic_helper_check_planes(dev, state);
  82         if (ret)
  83                 return ret;
  84
  85         /*
  86          * tilcdc ->atomic_check can update ->mode_changed if pixel format
  87          * changes, hence will we check modeset changes again.
  88          */
  89         ret = drm_atomic_helper_check_modeset(dev, state);
  90         if (ret)
  91                 return ret;
  92
  93         return ret;
  94 }
  95
  96 static int tilcdc_commit(struct drm_device *dev,
  97                   struct drm_atomic_state *state,
  98                   bool async)
  99 {
 100         int ret;
 101
 102         ret = drm_atomic_helper_prepare_planes(dev, state);
 103         if (ret)
 104                 return ret;
 105
 106         ret = drm_atomic_helper_swap_state(state, true);
 107         if (ret) {
 108                 drm_atomic_helper_cleanup_planes(dev, state);
 109                 return ret;
 110         }
 111
 112         /*
 113          * Everything below can be run asynchronously without the need to grab
 114          * any modeset locks at all under one condition: It must be guaranteed
 115          * that the asynchronous work has either been cancelled (if the driver
 116          * supports it, which at least requires that the framebuffers get
 117          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 118          * before the new state gets committed on the software side with
 119          * drm_atomic_helper_swap_state().
 120          *
 121          * This scheme allows new atomic state updates to be prepared and
 122          * checked in parallel to the asynchronous completion of the previous
 123          * update. Which is important since compositors need to figure out the
 124          * composition of the next frame right after having submitted the
 125          * current layout.
 126          */
 127
 128         drm_atomic_helper_commit_modeset_disables(dev, state);
 129
 130         drm_atomic_helper_commit_planes(dev, state, 0);
 131
 132         drm_atomic_helper_commit_modeset_enables(dev, state);
 133
 134         drm_atomic_helper_wait_for_vblanks(dev, state);
 135
 136         drm_atomic_helper_cleanup_planes(dev, state);
 137
 138         return 0;
 139 }
 140
 141 static const struct drm_mode_config_funcs mode_config_funcs = {
 142         .fb_create = tilcdc_fb_create,
 143         .output_poll_changed = drm_fb_helper_output_poll_changed,
 144         .atomic_check = tilcdc_atomic_check,
 145         .atomic_commit = tilcdc_commit,
 146 };
 147
 148 static void modeset_init(struct drm_device *dev)
 149 {
 150         struct tilcdc_drm_private *priv = dev->dev_private;
 151         struct tilcdc_module *mod;
 152
 153         list_for_each_entry(mod, &module_list, list) {
 154                 DBG("loading module: %s", mod->name);
 155                 mod->funcs->modeset_init(mod, dev);
 156         }
 157
 158         dev->mode_config.min_width = 0;
 159         dev->mode_config.min_height = 0;
 160         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
 161         dev->mode_config.max_height = 2048;
 162         dev->mode_config.funcs = &mode_config_funcs;
 163 }
 164
 165 #ifdef CONFIG_CPU_FREQ
 166 static int cpufreq_transition(struct notifier_block *nb,
 167                                      unsigned long val, void *data)
 168 {
 169         struct tilcdc_drm_private *priv = container_of(nb,
 170                         struct tilcdc_drm_private, freq_transition);
 171
 172         if (val == CPUFREQ_POSTCHANGE)
 173                 tilcdc_crtc_update_clk(priv->crtc);
 174
 175         return 0;
 176 }
 177 #endif
 178
 179 /*
 180  * DRM operations:
 181  */
 182
 183 static void tilcdc_fini(struct drm_device *dev)
 184 {
 185         struct tilcdc_drm_private *priv = dev->dev_private;
 186
 187 #ifdef CONFIG_CPU_FREQ
 188         if (priv->freq_transition.notifier_call)
 189                 cpufreq_unregister_notifier(&priv->freq_transition,
 190                                             CPUFREQ_TRANSITION_NOTIFIER);
 191 #endif
 192
 193         if (priv->crtc)
 194                 tilcdc_crtc_shutdown(priv->crtc);
 195
 196         if (priv->is_registered)
 197                 drm_dev_unregister(dev);
 198
 199         drm_kms_helper_poll_fini(dev);
 200
 201         drm_fb_cma_fbdev_fini(dev);
 202
 203         drm_irq_uninstall(dev);
 204         drm_mode_config_cleanup(dev);
 205         tilcdc_remove_external_device(dev);
 206
 207         if (priv->clk)
 208                 clk_put(priv->clk);
 209
 210         if (priv->mmio)
 211                 iounmap(priv->mmio);
 212
 213         if (priv->wq) {
 214                 flush_workqueue(priv->wq);
 215                 destroy_workqueue(priv->wq);
 216         }
 217
 218         dev->dev_private = NULL;
 219
 220         pm_runtime_disable(dev->dev);
 221
 222         drm_dev_put(dev);
 223 }
 224
 225 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
 226 {
 227         struct drm_device *ddev;
 228         struct platform_device *pdev = to_platform_device(dev);
 229         struct device_node *node = dev->of_node;
 230         struct tilcdc_drm_private *priv;
 231         struct resource *res;
 232         u32 bpp = 0;
 233         int ret;
 234
 235         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 236         if (!priv)
 237                 return -ENOMEM;
 238
 239         ddev = drm_dev_alloc(ddrv, dev);
 240         if (IS_ERR(ddev))
 241                 return PTR_ERR(ddev);
 242
 243         ddev->dev_private = priv;
 244         platform_set_drvdata(pdev, ddev);
 245         drm_mode_config_init(ddev);
 246
 247         priv->is_componentized =
 248                 tilcdc_get_external_components(dev, NULL) > 0;
 249
 250         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
 251         if (!priv->wq) {
 252                 ret = -ENOMEM;
 253                 goto init_failed;
 254         }
 255
 256         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 257         if (!res) {
 258                 dev_err(dev, "failed to get memory resource\n");
 259                 ret = -EINVAL;
 260                 goto init_failed;
 261         }
 262
 263         priv->mmio = ioremap_nocache(res->start, resource_size(res));
 264         if (!priv->mmio) {
 265                 dev_err(dev, "failed to ioremap\n");
 266                 ret = -ENOMEM;
 267                 goto init_failed;
 268         }
 269
 270         priv->clk = clk_get(dev, "fck");
 271         if (IS_ERR(priv->clk)) {
 272                 dev_err(dev, "failed to get functional clock\n");
 273                 ret = -ENODEV;
 274                 goto init_failed;
 275         }
 276
 277         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
 278                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
 279
 280         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
 281
 282         if (of_property_read_u32(node, "max-width", &priv->max_width))
 283                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
 284
 285         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
 286
 287         if (of_property_read_u32(node, "max-pixelclock",
 288                                         &priv->max_pixelclock))
 289                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
 290
 291         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
 292
 293         pm_runtime_enable(dev);
 294
 295         /* Determine LCD IP Version */
 296         pm_runtime_get_sync(dev);
 297         switch (tilcdc_read(ddev, LCDC_PID_REG)) {
 298         case 0x4c100102:
 299                 priv->rev = 1;
 300                 break;
 301         case 0x4f200800:
 302         case 0x4f201000:
 303                 priv->rev = 2;
 304                 break;
 305         default:
 306                 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
 307                         "defaulting to LCD revision 1\n",
 308                         tilcdc_read(ddev, LCDC_PID_REG));
 309                 priv->rev = 1;
 310                 break;
 311         }
 312
 313         pm_runtime_put_sync(dev);
 314
 315         if (priv->rev == 1) {
 316                 DBG("Revision 1 LCDC supports only RGB565 format");
 317                 priv->pixelformats = tilcdc_rev1_formats;
 318                 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
 319                 bpp = 16;
 320         } else {
 321                 const char *str = "\0";
 322
 323                 of_property_read_string(node, "blue-and-red-wiring", &str);
 324                 if (0 == strcmp(str, "crossed")) {
 325                         DBG("Configured for crossed blue and red wires");
 326                         priv->pixelformats = tilcdc_crossed_formats;
 327                         priv->num_pixelformats =
 328                                 ARRAY_SIZE(tilcdc_crossed_formats);
 329                         bpp = 32; /* Choose bpp with RGB support for fbdef */
 330                 } else if (0 == strcmp(str, "straight")) {
 331                         DBG("Configured for straight blue and red wires");
 332                         priv->pixelformats = tilcdc_straight_formats;
 333                         priv->num_pixelformats =
 334                                 ARRAY_SIZE(tilcdc_straight_formats);
 335                         bpp = 16; /* Choose bpp with RGB support for fbdef */
 336                 } else {
 337                         DBG("Blue and red wiring '%s' unknown, use legacy mode",
 338                             str);
 339                         priv->pixelformats = tilcdc_legacy_formats;
 340                         priv->num_pixelformats =
 341                                 ARRAY_SIZE(tilcdc_legacy_formats);
 342                         bpp = 16; /* This is just a guess */
 343                 }
 344         }
 345
 346         ret = tilcdc_crtc_create(ddev);
 347         if (ret < 0) {
 348                 dev_err(dev, "failed to create crtc\n");
 349                 goto init_failed;
 350         }
 351         modeset_init(ddev);
 352
 353 #ifdef CONFIG_CPU_FREQ
 354         priv->freq_transition.notifier_call = cpufreq_transition;
 355         ret = cpufreq_register_notifier(&priv->freq_transition,
 356                         CPUFREQ_TRANSITION_NOTIFIER);
 357         if (ret) {
 358                 dev_err(dev, "failed to register cpufreq notifier\n");
 359                 priv->freq_transition.notifier_call = NULL;
 360                 goto init_failed;
 361         }
 362 #endif
 363
 364         if (priv->is_componentized) {
 365                 ret = component_bind_all(dev, ddev);
 366                 if (ret < 0)
 367                         goto init_failed;
 368
 369                 ret = tilcdc_add_component_encoder(ddev);
 370                 if (ret < 0)
 371                         goto init_failed;
 372         } else {
 373                 ret = tilcdc_attach_external_device(ddev);
 374                 if (ret)
 375                         goto init_failed;
 376         }
 377
 378         if (!priv->external_connector &&
 379             ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
 380                 dev_err(dev, "no encoders/connectors found\n");
 381                 ret = -EPROBE_DEFER;
 382                 goto init_failed;
 383         }
 384
 385         ret = drm_vblank_init(ddev, 1);
 386         if (ret < 0) {
 387                 dev_err(dev, "failed to initialize vblank\n");
 388                 goto init_failed;
 389         }
 390
 391         ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
 392         if (ret < 0) {
 393                 dev_err(dev, "failed to install IRQ handler\n");
 394                 goto init_failed;
 395         }
 396
 397         drm_mode_config_reset(ddev);
 398
 399         ret = drm_fb_cma_fbdev_init(ddev, bpp, 0);
 400         if (ret)
 401                 goto init_failed;
 402
 403         drm_kms_helper_poll_init(ddev);
 404
 405         ret = drm_dev_register(ddev, 0);
 406         if (ret)
 407                 goto init_failed;
 408
 409         priv->is_registered = true;
 410         return 0;
 411
 412 init_failed:
 413         tilcdc_fini(ddev);
 414
 415         return ret;
 416 }
 417
 418 static irqreturn_t tilcdc_irq(int irq, void *arg)
 419 {
 420         struct drm_device *dev = arg;
 421         struct tilcdc_drm_private *priv = dev->dev_private;
 422         return tilcdc_crtc_irq(priv->crtc);
 423 }
 424
 425 #if defined(CONFIG_DEBUG_FS)
 426 static const struct {
 427         const char *name;
 428         uint8_t  rev;
 429         uint8_t  save;
 430         uint32_t reg;
 431 } registers[] =         {
 432 #define REG(rev, save, reg) { #reg, rev, save, reg }
 433                 /* exists in revision 1: */
 434                 REG(1, false, LCDC_PID_REG),
 435                 REG(1, true,  LCDC_CTRL_REG),
 436                 REG(1, false, LCDC_STAT_REG),
 437                 REG(1, true,  LCDC_RASTER_CTRL_REG),
 438                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
 439                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
 440                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
 441                 REG(1, true,  LCDC_DMA_CTRL_REG),
 442                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
 443                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
 444                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
 445                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
 446                 /* new in revision 2: */
 447                 REG(2, false, LCDC_RAW_STAT_REG),
 448                 REG(2, false, LCDC_MASKED_STAT_REG),
 449                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
 450                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
 451                 REG(2, false, LCDC_END_OF_INT_IND_REG),
 452                 REG(2, true,  LCDC_CLK_ENABLE_REG),
 453 #undef REG
 454 };
 455
 456 #endif
 457
 458 #ifdef CONFIG_DEBUG_FS
 459 static int tilcdc_regs_show(struct seq_file *m, void *arg)
 460 {
 461         struct drm_info_node *node = (struct drm_info_node *) m->private;
 462         struct drm_device *dev = node->minor->dev;
 463         struct tilcdc_drm_private *priv = dev->dev_private;
 464         unsigned i;
 465
 466         pm_runtime_get_sync(dev->dev);
 467
 468         seq_printf(m, "revision: %d\n", priv->rev);
 469
 470         for (i = 0; i < ARRAY_SIZE(registers); i++)
 471                 if (priv->rev >= registers[i].rev)
 472                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
 473                                         tilcdc_read(dev, registers[i].reg));
 474
 475         pm_runtime_put_sync(dev->dev);
 476
 477         return 0;
 478 }
 479
 480 static int tilcdc_mm_show(struct seq_file *m, void *arg)
 481 {
 482         struct drm_info_node *node = (struct drm_info_node *) m->private;
 483         struct drm_device *dev = node->minor->dev;
 484         struct drm_printer p = drm_seq_file_printer(m);
 485         drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
 486         return 0;
 487 }
 488
 489 static struct drm_info_list tilcdc_debugfs_list[] = {
 490                 { "regs", tilcdc_regs_show, 0 },
 491                 { "mm",   tilcdc_mm_show,   0 },
 492 };
 493
 494 static int tilcdc_debugfs_init(struct drm_minor *minor)
 495 {
 496         struct drm_device *dev = minor->dev;
 497         struct tilcdc_module *mod;
 498         int ret;
 499
 500         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
 501                         ARRAY_SIZE(tilcdc_debugfs_list),
 502                         minor->debugfs_root, minor);
 503
 504         list_for_each_entry(mod, &module_list, list)
 505                 if (mod->funcs->debugfs_init)
 506                         mod->funcs->debugfs_init(mod, minor);
 507
 508         if (ret) {
 509                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
 510                 return ret;
 511         }
 512
 513         return ret;
 514 }
 515 #endif
 516
 517 DEFINE_DRM_GEM_CMA_FOPS(fops);
 518
 519 static struct drm_driver tilcdc_driver = {
 520         .driver_features    = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
 521                                DRIVER_PRIME | DRIVER_ATOMIC),
 522         .lastclose          = drm_fb_helper_lastclose,
 523         .irq_handler        = tilcdc_irq,
 524         .gem_free_object_unlocked = drm_gem_cma_free_object,
 525         .gem_print_info     = drm_gem_cma_print_info,
 526         .gem_vm_ops         = &drm_gem_cma_vm_ops,
 527         .dumb_create        = drm_gem_cma_dumb_create,
 528
 529         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 530         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 531         .gem_prime_import       = drm_gem_prime_import,
 532         .gem_prime_export       = drm_gem_prime_export,
 533         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 534         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 535         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 536         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 537         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 538 #ifdef CONFIG_DEBUG_FS
 539         .debugfs_init       = tilcdc_debugfs_init,
 540 #endif
 541         .fops               = &fops,
 542         .name               = "tilcdc",
 543         .desc               = "TI LCD Controller DRM",
 544         .date               = "20121205",
 545         .major              = 1,
 546         .minor              = 0,
 547 };
 548
 549 /*
 550  * Power management:
 551  */
 552
 553 #ifdef CONFIG_PM_SLEEP
 554 static int tilcdc_pm_suspend(struct device *dev)
 555 {
 556         struct drm_device *ddev = dev_get_drvdata(dev);
 557         struct tilcdc_drm_private *priv = ddev->dev_private;
 558
 559         priv->saved_state = drm_atomic_helper_suspend(ddev);
 560
 561         /* Select sleep pin state */
 562         pinctrl_pm_select_sleep_state(dev);
 563
 564         return 0;
 565 }
 566
 567 static int tilcdc_pm_resume(struct device *dev)
 568 {
 569         struct drm_device *ddev = dev_get_drvdata(dev);
 570         struct tilcdc_drm_private *priv = ddev->dev_private;
 571         int ret = 0;
 572
 573         /* Select default pin state */
 574         pinctrl_pm_select_default_state(dev);
 575
 576         if (priv->saved_state)
 577                 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
 578
 579         return ret;
 580 }
 581 #endif
 582
 583 static const struct dev_pm_ops tilcdc_pm_ops = {
 584         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
 585 };
 586
 587 /*
 588  * Platform driver:
 589  */
 590 static int tilcdc_bind(struct device *dev)
 591 {
 592         return tilcdc_init(&tilcdc_driver, dev);
 593 }
 594
 595 static void tilcdc_unbind(struct device *dev)
 596 {
 597         struct drm_device *ddev = dev_get_drvdata(dev);
 598
 599         /* Check if a subcomponent has already triggered the unloading. */
 600         if (!ddev->dev_private)
 601                 return;
 602
 603         tilcdc_fini(dev_get_drvdata(dev));
 604 }
 605
 606 static const struct component_master_ops tilcdc_comp_ops = {
 607         .bind = tilcdc_bind,
 608         .unbind = tilcdc_unbind,
 609 };
 610
 611 static int tilcdc_pdev_probe(struct platform_device *pdev)
 612 {
 613         struct component_match *match = NULL;
 614         int ret;
 615
 616         /* bail out early if no DT data: */
 617         if (!pdev->dev.of_node) {
 618                 dev_err(&pdev->dev, "device-tree data is missing\n");
 619                 return -ENXIO;
 620         }
 621
 622         ret = tilcdc_get_external_components(&pdev->dev, &match);
 623         if (ret < 0)
 624                 return ret;
 625         else if (ret == 0)
 626                 return tilcdc_init(&tilcdc_driver, &pdev->dev);
 627         else
 628                 return component_master_add_with_match(&pdev->dev,
 629                                                        &tilcdc_comp_ops,
 630                                                        match);
 631 }
 632
 633 static int tilcdc_pdev_remove(struct platform_device *pdev)
 634 {
 635         int ret;
 636
 637         ret = tilcdc_get_external_components(&pdev->dev, NULL);
 638         if (ret < 0)
 639                 return ret;
 640         else if (ret == 0)
 641                 tilcdc_fini(platform_get_drvdata(pdev));
 642         else
 643                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
 644
 645         return 0;
 646 }
 647
 648 static struct of_device_id tilcdc_of_match[] = {
 649                 { .compatible = "ti,am33xx-tilcdc", },
 650                 { .compatible = "ti,da850-tilcdc", },
 651                 { },
 652 };
 653 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
 654
 655 static struct platform_driver tilcdc_platform_driver = {
 656         .probe      = tilcdc_pdev_probe,
 657         .remove     = tilcdc_pdev_remove,
 658         .driver     = {
 659                 .name   = "tilcdc",
 660                 .pm     = &tilcdc_pm_ops,
 661                 .of_match_table = tilcdc_of_match,
 662         },
 663 };
 664
 665 static int __init tilcdc_drm_init(void)
 666 {
 667         DBG("init");
 668         tilcdc_tfp410_init();
 669         tilcdc_panel_init();
 670         return platform_driver_register(&tilcdc_platform_driver);
 671 }
 672
 673 static void __exit tilcdc_drm_fini(void)
 674 {
 675         DBG("fini");
 676         platform_driver_unregister(&tilcdc_platform_driver);
 677         tilcdc_panel_fini();
 678         tilcdc_tfp410_fini();
 679 }
 680
 681 module_init(tilcdc_drm_init);
 682 module_exit(tilcdc_drm_fini);
 683
 684 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
 685 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
 686 MODULE_LICENSE("GPL");