drivers/gpu/drm/tilcdc/tilcdc_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /* LCDC DRM driver, based on da8xx-fb */
  19
  20 #include <linux/component.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/suspend.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27
  28 #include "tilcdc_drv.h"
  29 #include "tilcdc_regs.h"
  30 #include "tilcdc_tfp410.h"
  31 #include "tilcdc_panel.h"
  32 #include "tilcdc_external.h"
  33
  34 static LIST_HEAD(module_list);
  35
  36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  37
  38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  39                                                DRM_FORMAT_BGR888,
  40                                                DRM_FORMAT_XBGR8888 };
  41
  42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  43                                               DRM_FORMAT_RGB888,
  44                                               DRM_FORMAT_XRGB8888 };
  45
  46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  47                                              DRM_FORMAT_RGB888,
  48                                              DRM_FORMAT_XRGB8888 };
  49
  50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  51                 const struct tilcdc_module_ops *funcs)
  52 {
  53         mod->name = name;
  54         mod->funcs = funcs;
  55         INIT_LIST_HEAD(&mod->list);
  56         list_add(&mod->list, &module_list);
  57 }
  58
  59 void tilcdc_module_cleanup(struct tilcdc_module *mod)
  60 {
  61         list_del(&mod->list);
  62 }
  63
  64 static struct of_device_id tilcdc_of_match[];
  65
  66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  67                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  68 {
  69         return drm_gem_fb_create(dev, file_priv, mode_cmd);
  70 }
  71
  72 static int tilcdc_atomic_check(struct drm_device *dev,
  73                                struct drm_atomic_state *state)
  74 {
  75         int ret;
  76
  77         ret = drm_atomic_helper_check_modeset(dev, state);
  78         if (ret)
  79                 return ret;
  80
  81         ret = drm_atomic_helper_check_planes(dev, state);
  82         if (ret)
  83                 return ret;
  84
  85         /*
  86          * tilcdc ->atomic_check can update ->mode_changed if pixel format
  87          * changes, hence will we check modeset changes again.
  88          */
  89         ret = drm_atomic_helper_check_modeset(dev, state);
  90         if (ret)
  91                 return ret;
  92
  93         return ret;
  94 }
  95
  96 static int tilcdc_commit(struct drm_device *dev,
  97                   struct drm_atomic_state *state,
  98                   bool async)
  99 {
 100         int ret;
 101
 102         ret = drm_atomic_helper_prepare_planes(dev, state);
 103         if (ret)
 104                 return ret;
 105
 106         ret = drm_atomic_helper_swap_state(state, true);
 107         if (ret) {
 108                 drm_atomic_helper_cleanup_planes(dev, state);
 109                 return ret;
 110         }
 111
 112         /*
 113          * Everything below can be run asynchronously without the need to grab
 114          * any modeset locks at all under one condition: It must be guaranteed
 115          * that the asynchronous work has either been cancelled (if the driver
 116          * supports it, which at least requires that the framebuffers get
 117          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 118          * before the new state gets committed on the software side with
 119          * drm_atomic_helper_swap_state().
 120          *
 121          * This scheme allows new atomic state updates to be prepared and
 122          * checked in parallel to the asynchronous completion of the previous
 123          * update. Which is important since compositors need to figure out the
 124          * composition of the next frame right after having submitted the
 125          * current layout.
 126          */
 127
 128         drm_atomic_helper_commit_modeset_disables(dev, state);
 129
 130         drm_atomic_helper_commit_planes(dev, state, 0);
 131
 132         drm_atomic_helper_commit_modeset_enables(dev, state);
 133
 134         drm_atomic_helper_wait_for_vblanks(dev, state);
 135
 136         drm_atomic_helper_cleanup_planes(dev, state);
 137
 138         return 0;
 139 }
 140
 141 static const struct drm_mode_config_funcs mode_config_funcs = {
 142         .fb_create = tilcdc_fb_create,
 143         .output_poll_changed = drm_fb_helper_output_poll_changed,
 144         .atomic_check = tilcdc_atomic_check,
 145         .atomic_commit = tilcdc_commit,
 146 };
 147
 148 static void modeset_init(struct drm_device *dev)
 149 {
 150         struct tilcdc_drm_private *priv = dev->dev_private;
 151         struct tilcdc_module *mod;
 152
 153         list_for_each_entry(mod, &module_list, list) {
 154                 DBG("loading module: %s", mod->name);
 155                 mod->funcs->modeset_init(mod, dev);
 156         }
 157
 158         dev->mode_config.min_width = 0;
 159         dev->mode_config.min_height = 0;
 160         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
 161         dev->mode_config.max_height = 2048;
 162         dev->mode_config.funcs = &mode_config_funcs;
 163 }
 164
 165 #ifdef CONFIG_CPU_FREQ
 166 static int cpufreq_transition(struct notifier_block *nb,
 167                                      unsigned long val, void *data)
 168 {
 169         struct tilcdc_drm_private *priv = container_of(nb,
 170                         struct tilcdc_drm_private, freq_transition);
 171
 172         if (val == CPUFREQ_POSTCHANGE)
 173                 tilcdc_crtc_update_clk(priv->crtc);
 174
 175         return 0;
 176 }
 177 #endif
 178
 179 /*
 180  * DRM operations:
 181  */
 182
 183 static void tilcdc_fini(struct drm_device *dev)
 184 {
 185         struct tilcdc_drm_private *priv = dev->dev_private;
 186
 187 #ifdef CONFIG_CPU_FREQ
 188         if (priv->freq_transition.notifier_call)
 189                 cpufreq_unregister_notifier(&priv->freq_transition,
 190                                             CPUFREQ_TRANSITION_NOTIFIER);
 191 #endif
 192
 193         if (priv->crtc)
 194                 tilcdc_crtc_shutdown(priv->crtc);
 195
 196         if (priv->is_registered)
 197                 drm_dev_unregister(dev);
 198
 199         drm_kms_helper_poll_fini(dev);
 200
 201         drm_fb_cma_fbdev_fini(dev);
 202
 203         drm_irq_uninstall(dev);
 204         drm_mode_config_cleanup(dev);
 205
 206         if (priv->clk)
 207                 clk_put(priv->clk);
 208
 209         if (priv->mmio)
 210                 iounmap(priv->mmio);
 211
 212         if (priv->wq) {
 213                 flush_workqueue(priv->wq);
 214                 destroy_workqueue(priv->wq);
 215         }
 216
 217         dev->dev_private = NULL;
 218
 219         pm_runtime_disable(dev->dev);
 220
 221         drm_dev_put(dev);
 222 }
 223
 224 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
 225 {
 226         struct drm_device *ddev;
 227         struct platform_device *pdev = to_platform_device(dev);
 228         struct device_node *node = dev->of_node;
 229         struct tilcdc_drm_private *priv;
 230         struct resource *res;
 231         u32 bpp = 0;
 232         int ret;
 233
 234         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 235         if (!priv)
 236                 return -ENOMEM;
 237
 238         ddev = drm_dev_alloc(ddrv, dev);
 239         if (IS_ERR(ddev))
 240                 return PTR_ERR(ddev);
 241
 242         ddev->dev_private = priv;
 243         platform_set_drvdata(pdev, ddev);
 244         drm_mode_config_init(ddev);
 245
 246         priv->is_componentized =
 247                 tilcdc_get_external_components(dev, NULL) > 0;
 248
 249         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
 250         if (!priv->wq) {
 251                 ret = -ENOMEM;
 252                 goto init_failed;
 253         }
 254
 255         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 256         if (!res) {
 257                 dev_err(dev, "failed to get memory resource\n");
 258                 ret = -EINVAL;
 259                 goto init_failed;
 260         }
 261
 262         priv->mmio = ioremap_nocache(res->start, resource_size(res));
 263         if (!priv->mmio) {
 264                 dev_err(dev, "failed to ioremap\n");
 265                 ret = -ENOMEM;
 266                 goto init_failed;
 267         }
 268
 269         priv->clk = clk_get(dev, "fck");
 270         if (IS_ERR(priv->clk)) {
 271                 dev_err(dev, "failed to get functional clock\n");
 272                 ret = -ENODEV;
 273                 goto init_failed;
 274         }
 275
 276         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
 277                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
 278
 279         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
 280
 281         if (of_property_read_u32(node, "max-width", &priv->max_width))
 282                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
 283
 284         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
 285
 286         if (of_property_read_u32(node, "max-pixelclock",
 287                                         &priv->max_pixelclock))
 288                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
 289
 290         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
 291
 292         pm_runtime_enable(dev);
 293
 294         /* Determine LCD IP Version */
 295         pm_runtime_get_sync(dev);
 296         switch (tilcdc_read(ddev, LCDC_PID_REG)) {
 297         case 0x4c100102:
 298                 priv->rev = 1;
 299                 break;
 300         case 0x4f200800:
 301         case 0x4f201000:
 302                 priv->rev = 2;
 303                 break;
 304         default:
 305                 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
 306                         "defaulting to LCD revision 1\n",
 307                         tilcdc_read(ddev, LCDC_PID_REG));
 308                 priv->rev = 1;
 309                 break;
 310         }
 311
 312         pm_runtime_put_sync(dev);
 313
 314         if (priv->rev == 1) {
 315                 DBG("Revision 1 LCDC supports only RGB565 format");
 316                 priv->pixelformats = tilcdc_rev1_formats;
 317                 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
 318                 bpp = 16;
 319         } else {
 320                 const char *str = "\0";
 321
 322                 of_property_read_string(node, "blue-and-red-wiring", &str);
 323                 if (0 == strcmp(str, "crossed")) {
 324                         DBG("Configured for crossed blue and red wires");
 325                         priv->pixelformats = tilcdc_crossed_formats;
 326                         priv->num_pixelformats =
 327                                 ARRAY_SIZE(tilcdc_crossed_formats);
 328                         bpp = 32; /* Choose bpp with RGB support for fbdef */
 329                 } else if (0 == strcmp(str, "straight")) {
 330                         DBG("Configured for straight blue and red wires");
 331                         priv->pixelformats = tilcdc_straight_formats;
 332                         priv->num_pixelformats =
 333                                 ARRAY_SIZE(tilcdc_straight_formats);
 334                         bpp = 16; /* Choose bpp with RGB support for fbdef */
 335                 } else {
 336                         DBG("Blue and red wiring '%s' unknown, use legacy mode",
 337                             str);
 338                         priv->pixelformats = tilcdc_legacy_formats;
 339                         priv->num_pixelformats =
 340                                 ARRAY_SIZE(tilcdc_legacy_formats);
 341                         bpp = 16; /* This is just a guess */
 342                 }
 343         }
 344
 345         ret = tilcdc_crtc_create(ddev);
 346         if (ret < 0) {
 347                 dev_err(dev, "failed to create crtc\n");
 348                 goto init_failed;
 349         }
 350         modeset_init(ddev);
 351
 352 #ifdef CONFIG_CPU_FREQ
 353         priv->freq_transition.notifier_call = cpufreq_transition;
 354         ret = cpufreq_register_notifier(&priv->freq_transition,
 355                         CPUFREQ_TRANSITION_NOTIFIER);
 356         if (ret) {
 357                 dev_err(dev, "failed to register cpufreq notifier\n");
 358                 priv->freq_transition.notifier_call = NULL;
 359                 goto init_failed;
 360         }
 361 #endif
 362
 363         if (priv->is_componentized) {
 364                 ret = component_bind_all(dev, ddev);
 365                 if (ret < 0)
 366                         goto init_failed;
 367
 368                 ret = tilcdc_add_component_encoder(ddev);
 369                 if (ret < 0)
 370                         goto init_failed;
 371         } else {
 372                 ret = tilcdc_attach_external_device(ddev);
 373                 if (ret)
 374                         goto init_failed;
 375         }
 376
 377         if (!priv->external_connector &&
 378             ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
 379                 dev_err(dev, "no encoders/connectors found\n");
 380                 ret = -EPROBE_DEFER;
 381                 goto init_failed;
 382         }
 383
 384         ret = drm_vblank_init(ddev, 1);
 385         if (ret < 0) {
 386                 dev_err(dev, "failed to initialize vblank\n");
 387                 goto init_failed;
 388         }
 389
 390         ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
 391         if (ret < 0) {
 392                 dev_err(dev, "failed to install IRQ handler\n");
 393                 goto init_failed;
 394         }
 395
 396         drm_mode_config_reset(ddev);
 397
 398         ret = drm_fb_cma_fbdev_init(ddev, bpp, 0);
 399         if (ret)
 400                 goto init_failed;
 401
 402         drm_kms_helper_poll_init(ddev);
 403
 404         ret = drm_dev_register(ddev, 0);
 405         if (ret)
 406                 goto init_failed;
 407
 408         priv->is_registered = true;
 409         return 0;
 410
 411 init_failed:
 412         tilcdc_fini(ddev);
 413
 414         return ret;
 415 }
 416
 417 static irqreturn_t tilcdc_irq(int irq, void *arg)
 418 {
 419         struct drm_device *dev = arg;
 420         struct tilcdc_drm_private *priv = dev->dev_private;
 421         return tilcdc_crtc_irq(priv->crtc);
 422 }
 423
 424 #if defined(CONFIG_DEBUG_FS)
 425 static const struct {
 426         const char *name;
 427         uint8_t  rev;
 428         uint8_t  save;
 429         uint32_t reg;
 430 } registers[] =         {
 431 #define REG(rev, save, reg) { #reg, rev, save, reg }
 432                 /* exists in revision 1: */
 433                 REG(1, false, LCDC_PID_REG),
 434                 REG(1, true,  LCDC_CTRL_REG),
 435                 REG(1, false, LCDC_STAT_REG),
 436                 REG(1, true,  LCDC_RASTER_CTRL_REG),
 437                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
 438                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
 439                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
 440                 REG(1, true,  LCDC_DMA_CTRL_REG),
 441                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
 442                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
 443                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
 444                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
 445                 /* new in revision 2: */
 446                 REG(2, false, LCDC_RAW_STAT_REG),
 447                 REG(2, false, LCDC_MASKED_STAT_REG),
 448                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
 449                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
 450                 REG(2, false, LCDC_END_OF_INT_IND_REG),
 451                 REG(2, true,  LCDC_CLK_ENABLE_REG),
 452 #undef REG
 453 };
 454
 455 #endif
 456
 457 #ifdef CONFIG_DEBUG_FS
 458 static int tilcdc_regs_show(struct seq_file *m, void *arg)
 459 {
 460         struct drm_info_node *node = (struct drm_info_node *) m->private;
 461         struct drm_device *dev = node->minor->dev;
 462         struct tilcdc_drm_private *priv = dev->dev_private;
 463         unsigned i;
 464
 465         pm_runtime_get_sync(dev->dev);
 466
 467         seq_printf(m, "revision: %d\n", priv->rev);
 468
 469         for (i = 0; i < ARRAY_SIZE(registers); i++)
 470                 if (priv->rev >= registers[i].rev)
 471                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
 472                                         tilcdc_read(dev, registers[i].reg));
 473
 474         pm_runtime_put_sync(dev->dev);
 475
 476         return 0;
 477 }
 478
 479 static int tilcdc_mm_show(struct seq_file *m, void *arg)
 480 {
 481         struct drm_info_node *node = (struct drm_info_node *) m->private;
 482         struct drm_device *dev = node->minor->dev;
 483         struct drm_printer p = drm_seq_file_printer(m);
 484         drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
 485         return 0;
 486 }
 487
 488 static struct drm_info_list tilcdc_debugfs_list[] = {
 489                 { "regs", tilcdc_regs_show, 0 },
 490                 { "mm",   tilcdc_mm_show,   0 },
 491 };
 492
 493 static int tilcdc_debugfs_init(struct drm_minor *minor)
 494 {
 495         struct drm_device *dev = minor->dev;
 496         struct tilcdc_module *mod;
 497         int ret;
 498
 499         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
 500                         ARRAY_SIZE(tilcdc_debugfs_list),
 501                         minor->debugfs_root, minor);
 502
 503         list_for_each_entry(mod, &module_list, list)
 504                 if (mod->funcs->debugfs_init)
 505                         mod->funcs->debugfs_init(mod, minor);
 506
 507         if (ret) {
 508                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
 509                 return ret;
 510         }
 511
 512         return ret;
 513 }
 514 #endif
 515
 516 DEFINE_DRM_GEM_CMA_FOPS(fops);
 517
 518 static struct drm_driver tilcdc_driver = {
 519         .driver_features    = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
 520                                DRIVER_PRIME | DRIVER_ATOMIC),
 521         .lastclose          = drm_fb_helper_lastclose,
 522         .irq_handler        = tilcdc_irq,
 523         .gem_free_object_unlocked = drm_gem_cma_free_object,
 524         .gem_print_info     = drm_gem_cma_print_info,
 525         .gem_vm_ops         = &drm_gem_cma_vm_ops,
 526         .dumb_create        = drm_gem_cma_dumb_create,
 527
 528         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 529         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 530         .gem_prime_import       = drm_gem_prime_import,
 531         .gem_prime_export       = drm_gem_prime_export,
 532         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 533         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 534         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 535         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 536         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 537 #ifdef CONFIG_DEBUG_FS
 538         .debugfs_init       = tilcdc_debugfs_init,
 539 #endif
 540         .fops               = &fops,
 541         .name               = "tilcdc",
 542         .desc               = "TI LCD Controller DRM",
 543         .date               = "20121205",
 544         .major              = 1,
 545         .minor              = 0,
 546 };
 547
 548 /*
 549  * Power management:
 550  */
 551
 552 #ifdef CONFIG_PM_SLEEP
 553 static int tilcdc_pm_suspend(struct device *dev)
 554 {
 555         struct drm_device *ddev = dev_get_drvdata(dev);
 556         struct tilcdc_drm_private *priv = ddev->dev_private;
 557
 558         priv->saved_state = drm_atomic_helper_suspend(ddev);
 559
 560         /* Select sleep pin state */
 561         pinctrl_pm_select_sleep_state(dev);
 562
 563         return 0;
 564 }
 565
 566 static int tilcdc_pm_resume(struct device *dev)
 567 {
 568         struct drm_device *ddev = dev_get_drvdata(dev);
 569         struct tilcdc_drm_private *priv = ddev->dev_private;
 570         int ret = 0;
 571
 572         /* Select default pin state */
 573         pinctrl_pm_select_default_state(dev);
 574
 575         if (priv->saved_state)
 576                 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
 577
 578         return ret;
 579 }
 580 #endif
 581
 582 static const struct dev_pm_ops tilcdc_pm_ops = {
 583         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
 584 };
 585
 586 /*
 587  * Platform driver:
 588  */
 589 static int tilcdc_bind(struct device *dev)
 590 {
 591         return tilcdc_init(&tilcdc_driver, dev);
 592 }
 593
 594 static void tilcdc_unbind(struct device *dev)
 595 {
 596         struct drm_device *ddev = dev_get_drvdata(dev);
 597
 598         /* Check if a subcomponent has already triggered the unloading. */
 599         if (!ddev->dev_private)
 600                 return;
 601
 602         tilcdc_fini(dev_get_drvdata(dev));
 603 }
 604
 605 static const struct component_master_ops tilcdc_comp_ops = {
 606         .bind = tilcdc_bind,
 607         .unbind = tilcdc_unbind,
 608 };
 609
 610 static int tilcdc_pdev_probe(struct platform_device *pdev)
 611 {
 612         struct component_match *match = NULL;
 613         int ret;
 614
 615         /* bail out early if no DT data: */
 616         if (!pdev->dev.of_node) {
 617                 dev_err(&pdev->dev, "device-tree data is missing\n");
 618                 return -ENXIO;
 619         }
 620
 621         ret = tilcdc_get_external_components(&pdev->dev, &match);
 622         if (ret < 0)
 623                 return ret;
 624         else if (ret == 0)
 625                 return tilcdc_init(&tilcdc_driver, &pdev->dev);
 626         else
 627                 return component_master_add_with_match(&pdev->dev,
 628                                                        &tilcdc_comp_ops,
 629                                                        match);
 630 }
 631
 632 static int tilcdc_pdev_remove(struct platform_device *pdev)
 633 {
 634         int ret;
 635
 636         ret = tilcdc_get_external_components(&pdev->dev, NULL);
 637         if (ret < 0)
 638                 return ret;
 639         else if (ret == 0)
 640                 tilcdc_fini(platform_get_drvdata(pdev));
 641         else
 642                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
 643
 644         return 0;
 645 }
 646
 647 static struct of_device_id tilcdc_of_match[] = {
 648                 { .compatible = "ti,am33xx-tilcdc", },
 649                 { .compatible = "ti,da850-tilcdc", },
 650                 { },
 651 };
 652 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
 653
 654 static struct platform_driver tilcdc_platform_driver = {
 655         .probe      = tilcdc_pdev_probe,
 656         .remove     = tilcdc_pdev_remove,
 657         .driver     = {
 658                 .name   = "tilcdc",
 659                 .pm     = &tilcdc_pm_ops,
 660                 .of_match_table = tilcdc_of_match,
 661         },
 662 };
 663
 664 static int __init tilcdc_drm_init(void)
 665 {
 666         DBG("init");
 667         tilcdc_tfp410_init();
 668         tilcdc_panel_init();
 669         return platform_driver_register(&tilcdc_platform_driver);
 670 }
 671
 672 static void __exit tilcdc_drm_fini(void)
 673 {
 674         DBG("fini");
 675         platform_driver_unregister(&tilcdc_platform_driver);
 676         tilcdc_panel_fini();
 677         tilcdc_tfp410_fini();
 678 }
 679
 680 module_init(tilcdc_drm_init);
 681 module_exit(tilcdc_drm_fini);
 682
 683 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
 684 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
 685 MODULE_LICENSE("GPL");