2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_flip_work.h>
22 #include <drm/drm_plane_helper.h>
23 #include <linux/workqueue.h>
24 #include <linux/completion.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/of_graph.h>
27 #include <linux/math64.h>
29 #include "tilcdc_drv.h"
30 #include "tilcdc_regs.h"
32 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
33 #define TILCDC_PALETTE_SIZE 32
34 #define TILCDC_PALETTE_FIRST_ENTRY 0x4000
39 struct drm_plane primary;
40 const struct tilcdc_panel_info *info;
41 struct drm_pending_vblank_event *event;
42 struct mutex enable_lock;
45 wait_queue_head_t frame_done_wq;
49 unsigned int lcd_fck_rate;
52 unsigned int hvtotal_us;
54 struct drm_framebuffer *curr_fb;
55 struct drm_framebuffer *next_fb;
57 /* for deferred fb unref's: */
58 struct drm_flip_work unref_work;
60 /* Only set if an external encoder is connected */
61 bool simulate_vesa_sync;
65 struct work_struct recover_work;
67 dma_addr_t palette_dma_handle;
69 struct completion palette_loaded;
71 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
73 static void unref_worker(struct drm_flip_work *work, void *val)
75 struct tilcdc_crtc *tilcdc_crtc =
76 container_of(work, struct tilcdc_crtc, unref_work);
77 struct drm_device *dev = tilcdc_crtc->base.dev;
79 mutex_lock(&dev->mode_config.mutex);
80 drm_framebuffer_unreference(val);
81 mutex_unlock(&dev->mode_config.mutex);
84 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
86 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
87 struct drm_device *dev = crtc->dev;
88 struct tilcdc_drm_private *priv = dev->dev_private;
89 struct drm_gem_cma_object *gem;
90 dma_addr_t start, end;
91 u64 dma_base_and_ceiling;
93 gem = drm_fb_cma_get_gem_obj(fb, 0);
95 start = gem->paddr + fb->offsets[0] +
96 crtc->y * fb->pitches[0] +
97 crtc->x * fb->format->cpp[0];
99 end = start + (crtc->mode.vdisplay * fb->pitches[0]);
101 /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
102 * with a single insruction, if available. This should make it more
103 * unlikely that LCDC would fetch the DMA addresses in the middle of
109 dma_base_and_ceiling = (u64)end << 32 | start;
110 tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
112 if (tilcdc_crtc->curr_fb)
113 drm_flip_work_queue(&tilcdc_crtc->unref_work,
114 tilcdc_crtc->curr_fb);
116 tilcdc_crtc->curr_fb = fb;
120 * The driver currently only supports only true color formats. For
121 * true color the palette block is bypassed, but a 32 byte palette
122 * should still be loaded. The first 16-bit entry must be 0x4000 while
123 * all other entries must be zeroed.
125 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
127 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
128 struct drm_device *dev = crtc->dev;
129 struct tilcdc_drm_private *priv = dev->dev_private;
132 reinit_completion(&tilcdc_crtc->palette_loaded);
134 /* Tell the LCDC where the palette is located. */
135 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
136 tilcdc_crtc->palette_dma_handle);
137 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
138 (u32) tilcdc_crtc->palette_dma_handle +
139 TILCDC_PALETTE_SIZE - 1);
141 /* Set dma load mode for palette loading only. */
142 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
143 LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
144 LCDC_PALETTE_LOAD_MODE_MASK);
146 /* Enable DMA Palette Loaded Interrupt */
148 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
150 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
152 /* Enable LCDC DMA and wait for palette to be loaded. */
153 tilcdc_clear_irqstatus(dev, 0xffffffff);
154 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
156 ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded,
157 msecs_to_jiffies(50));
159 dev_err(dev->dev, "%s: Palette loading timeout", __func__);
161 /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
162 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
164 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
166 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
169 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
171 struct tilcdc_drm_private *priv = dev->dev_private;
173 tilcdc_clear_irqstatus(dev, 0xffffffff);
175 if (priv->rev == 1) {
176 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
177 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
178 LCDC_V1_UNDERFLOW_INT_ENA);
179 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
180 LCDC_V1_END_OF_FRAME_INT_ENA);
182 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
183 LCDC_V2_UNDERFLOW_INT_ENA |
184 LCDC_V2_END_OF_FRAME0_INT_ENA |
185 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
189 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
191 struct tilcdc_drm_private *priv = dev->dev_private;
193 /* disable irqs that we might have enabled: */
194 if (priv->rev == 1) {
195 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
196 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
197 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
198 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
199 LCDC_V1_END_OF_FRAME_INT_ENA);
201 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
202 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
203 LCDC_V2_END_OF_FRAME0_INT_ENA |
204 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
208 static void reset(struct drm_crtc *crtc)
210 struct drm_device *dev = crtc->dev;
211 struct tilcdc_drm_private *priv = dev->dev_private;
216 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
217 usleep_range(250, 1000);
218 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
222 * Calculate the percentage difference between the requested pixel clock rate
223 * and the effective rate resulting from calculating the clock divider value.
225 static unsigned int tilcdc_pclk_diff(unsigned long rate,
226 unsigned long real_rate)
228 int r = rate / 100, rr = real_rate / 100;
230 return (unsigned int)(abs(((rr - r) * 100) / r));
233 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
235 struct drm_device *dev = crtc->dev;
236 struct tilcdc_drm_private *priv = dev->dev_private;
237 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
238 unsigned long clk_rate, real_rate, req_rate;
242 clkdiv = 2; /* first try using a standard divider of 2 */
244 /* mode.clock is in KHz, set_rate wants parameter in Hz */
245 req_rate = crtc->mode.clock * 1000;
247 ret = clk_set_rate(priv->clk, req_rate * clkdiv);
248 clk_rate = clk_get_rate(priv->clk);
251 * If we fail to set the clock rate (some architectures don't
252 * use the common clock framework yet and may not implement
253 * all the clk API calls for every clock), try the next best
254 * thing: adjusting the clock divider, unless clk_get_rate()
258 /* Nothing more we can do. Just bail out. */
260 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
264 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate);
267 * Emit a warning if the real clock rate resulting from the
268 * calculated divider differs much from the requested rate.
270 * 5% is an arbitrary value - LCDs are usually quite tolerant
271 * about pixel clock rates.
273 real_rate = clkdiv * req_rate;
275 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
277 "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
278 clk_rate, real_rate);
282 tilcdc_crtc->lcd_fck_rate = clk_rate;
284 DBG("lcd_clk=%u, mode clock=%d, div=%u",
285 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
287 /* Configure the LCD clock divisor. */
288 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
292 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
293 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
294 LCDC_V2_CORE_CLK_EN);
297 uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode)
299 return (uint) div_u64(1000llu * mode->htotal * mode->vtotal,
303 static void tilcdc_crtc_set_mode(struct drm_crtc *crtc)
305 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
306 struct drm_device *dev = crtc->dev;
307 struct tilcdc_drm_private *priv = dev->dev_private;
308 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
309 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
310 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
311 struct drm_framebuffer *fb = crtc->primary->state->fb;
319 /* Configure the Burst Size and fifo threshold of DMA: */
320 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
321 switch (info->dma_burst_sz) {
323 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
326 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
329 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
332 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
335 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
338 dev_err(dev->dev, "invalid burst size\n");
341 reg |= (info->fifo_th << 8);
342 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
344 /* Configure timings: */
345 hbp = mode->htotal - mode->hsync_end;
346 hfp = mode->hsync_start - mode->hdisplay;
347 hsw = mode->hsync_end - mode->hsync_start;
348 vbp = mode->vtotal - mode->vsync_end;
349 vfp = mode->vsync_start - mode->vdisplay;
350 vsw = mode->vsync_end - mode->vsync_start;
352 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
353 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
355 /* Set AC Bias Period and Number of Transitions per Interrupt: */
356 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
357 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
358 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
361 * subtract one from hfp, hbp, hsw because the hardware uses
364 if (priv->rev == 2) {
365 /* clear bits we're going to set */
367 reg |= ((hfp-1) & 0x300) >> 8;
368 reg |= ((hbp-1) & 0x300) >> 4;
369 reg |= ((hsw-1) & 0x3c0) << 21;
371 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
373 reg = (((mode->hdisplay >> 4) - 1) << 4) |
374 (((hbp-1) & 0xff) << 24) |
375 (((hfp-1) & 0xff) << 16) |
376 (((hsw-1) & 0x3f) << 10);
378 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
379 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
381 reg = ((mode->vdisplay - 1) & 0x3ff) |
382 ((vbp & 0xff) << 24) |
383 ((vfp & 0xff) << 16) |
384 (((vsw-1) & 0x3f) << 10);
385 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
388 * be sure to set Bit 10 for the V2 LCDC controller,
389 * otherwise limited to 1024 pixels width, stopping
390 * 1920x1080 being supported.
392 if (priv->rev == 2) {
393 if ((mode->vdisplay - 1) & 0x400) {
394 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
397 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
402 /* Configure display type: */
403 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
404 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
405 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
406 0x000ff000 /* Palette Loading Delay bits */);
407 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
408 if (info->tft_alt_mode)
409 reg |= LCDC_TFT_ALT_ENABLE;
410 if (priv->rev == 2) {
411 switch (fb->format->format) {
412 case DRM_FORMAT_BGR565:
413 case DRM_FORMAT_RGB565:
415 case DRM_FORMAT_XBGR8888:
416 case DRM_FORMAT_XRGB8888:
417 reg |= LCDC_V2_TFT_24BPP_UNPACK;
419 case DRM_FORMAT_BGR888:
420 case DRM_FORMAT_RGB888:
421 reg |= LCDC_V2_TFT_24BPP_MODE;
424 dev_err(dev->dev, "invalid pixel format\n");
428 reg |= info->fdd < 12;
429 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
431 if (info->invert_pxl_clk)
432 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
434 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
437 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
439 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
442 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
444 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
446 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
447 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
449 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
451 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
452 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
454 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
456 if (info->raster_order)
457 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
459 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
461 tilcdc_crtc_set_clk(crtc);
463 tilcdc_crtc_load_palette(crtc);
465 set_scanout(crtc, fb);
467 drm_framebuffer_reference(fb);
469 crtc->hwmode = crtc->state->adjusted_mode;
471 tilcdc_crtc->hvtotal_us =
472 tilcdc_mode_hvtotal(&crtc->hwmode);
475 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
477 struct drm_device *dev = crtc->dev;
478 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
481 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
482 mutex_lock(&tilcdc_crtc->enable_lock);
483 if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
484 mutex_unlock(&tilcdc_crtc->enable_lock);
488 pm_runtime_get_sync(dev->dev);
492 tilcdc_crtc_set_mode(crtc);
494 tilcdc_crtc_enable_irqs(dev);
496 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
497 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
498 LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
499 LCDC_PALETTE_LOAD_MODE_MASK);
501 /* There is no real chance for a race here as the time stamp
502 * is taken before the raster DMA is started. The spin-lock is
503 * taken to have a memory barrier after taking the time-stamp
504 * and to avoid a context switch between taking the stamp and
505 * enabling the raster.
507 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
508 tilcdc_crtc->last_vblank = ktime_get();
509 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
510 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
512 drm_crtc_vblank_on(crtc);
514 tilcdc_crtc->enabled = true;
515 mutex_unlock(&tilcdc_crtc->enable_lock);
518 static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,
519 struct drm_crtc_state *old_state)
521 tilcdc_crtc_enable(crtc);
524 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
526 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
527 struct drm_device *dev = crtc->dev;
528 struct tilcdc_drm_private *priv = dev->dev_private;
531 mutex_lock(&tilcdc_crtc->enable_lock);
533 tilcdc_crtc->shutdown = true;
534 if (!tilcdc_crtc->enabled) {
535 mutex_unlock(&tilcdc_crtc->enable_lock);
538 tilcdc_crtc->frame_done = false;
539 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
542 * Wait for framedone irq which will still come before putting
545 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
546 tilcdc_crtc->frame_done,
547 msecs_to_jiffies(500));
549 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
552 drm_crtc_vblank_off(crtc);
554 tilcdc_crtc_disable_irqs(dev);
556 pm_runtime_put_sync(dev->dev);
558 if (tilcdc_crtc->next_fb) {
559 drm_flip_work_queue(&tilcdc_crtc->unref_work,
560 tilcdc_crtc->next_fb);
561 tilcdc_crtc->next_fb = NULL;
564 if (tilcdc_crtc->curr_fb) {
565 drm_flip_work_queue(&tilcdc_crtc->unref_work,
566 tilcdc_crtc->curr_fb);
567 tilcdc_crtc->curr_fb = NULL;
570 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
572 tilcdc_crtc->enabled = false;
573 mutex_unlock(&tilcdc_crtc->enable_lock);
576 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
578 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
579 tilcdc_crtc_off(crtc, false);
582 static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,
583 struct drm_crtc_state *old_state)
585 tilcdc_crtc_disable(crtc);
588 void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
590 tilcdc_crtc_off(crtc, true);
593 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
595 return crtc->state && crtc->state->enable && crtc->state->active;
598 static void tilcdc_crtc_recover_work(struct work_struct *work)
600 struct tilcdc_crtc *tilcdc_crtc =
601 container_of(work, struct tilcdc_crtc, recover_work);
602 struct drm_crtc *crtc = &tilcdc_crtc->base;
604 dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
606 drm_modeset_lock(&crtc->mutex, NULL);
608 if (!tilcdc_crtc_is_on(crtc))
611 tilcdc_crtc_disable(crtc);
612 tilcdc_crtc_enable(crtc);
614 drm_modeset_unlock(&crtc->mutex);
617 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
619 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
620 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
622 drm_modeset_lock(&crtc->mutex, NULL);
623 tilcdc_crtc_disable(crtc);
624 drm_modeset_unlock(&crtc->mutex);
626 flush_workqueue(priv->wq);
628 of_node_put(crtc->port);
629 drm_crtc_cleanup(crtc);
630 drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
633 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
634 struct drm_framebuffer *fb,
635 struct drm_pending_vblank_event *event)
637 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
638 struct drm_device *dev = crtc->dev;
640 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
642 if (tilcdc_crtc->event) {
643 dev_err(dev->dev, "already pending page flip!\n");
647 drm_framebuffer_reference(fb);
649 crtc->primary->fb = fb;
650 tilcdc_crtc->event = event;
652 mutex_lock(&tilcdc_crtc->enable_lock);
654 if (tilcdc_crtc->enabled) {
659 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
661 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
662 tilcdc_crtc->hvtotal_us);
663 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
665 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
666 tilcdc_crtc->next_fb = fb;
668 set_scanout(crtc, fb);
670 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
673 mutex_unlock(&tilcdc_crtc->enable_lock);
678 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
679 const struct drm_display_mode *mode,
680 struct drm_display_mode *adjusted_mode)
682 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
684 if (!tilcdc_crtc->simulate_vesa_sync)
688 * tilcdc does not generate VESA-compliant sync but aligns
689 * VS on the second edge of HS instead of first edge.
690 * We use adjusted_mode, to fixup sync by aligning both rising
691 * edges and add HSKEW offset to fix the sync.
693 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
694 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
696 if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
697 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
698 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
700 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
701 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
707 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
708 struct drm_crtc_state *state)
710 struct drm_display_mode *mode = &state->mode;
713 /* If we are not active we don't care */
717 if (state->state->planes[0].ptr != crtc->primary ||
718 state->state->planes[0].state == NULL ||
719 state->state->planes[0].state->crtc != crtc) {
720 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
724 ret = tilcdc_crtc_mode_valid(crtc, mode);
726 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
733 static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc)
738 static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc)
742 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
743 .destroy = tilcdc_crtc_destroy,
744 .set_config = drm_atomic_helper_set_config,
745 .page_flip = drm_atomic_helper_page_flip,
746 .reset = drm_atomic_helper_crtc_reset,
747 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
748 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
749 .enable_vblank = tilcdc_crtc_enable_vblank,
750 .disable_vblank = tilcdc_crtc_disable_vblank,
753 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
754 .mode_fixup = tilcdc_crtc_mode_fixup,
755 .atomic_check = tilcdc_crtc_atomic_check,
756 .atomic_enable = tilcdc_crtc_atomic_enable,
757 .atomic_disable = tilcdc_crtc_atomic_disable,
760 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
762 struct drm_device *dev = crtc->dev;
763 struct tilcdc_drm_private *priv = dev->dev_private;
768 else if (priv->rev == 2)
774 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
776 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
777 unsigned int bandwidth;
778 uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
781 * check to see if the width is within the range that
782 * the LCD Controller physically supports
784 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
785 return MODE_VIRTUAL_X;
787 /* width must be multiple of 16 */
788 if (mode->hdisplay & 0xf)
789 return MODE_VIRTUAL_X;
791 if (mode->vdisplay > 2048)
792 return MODE_VIRTUAL_Y;
794 DBG("Processing mode %dx%d@%d with pixel clock %d",
795 mode->hdisplay, mode->vdisplay,
796 drm_mode_vrefresh(mode), mode->clock);
798 hbp = mode->htotal - mode->hsync_end;
799 hfp = mode->hsync_start - mode->hdisplay;
800 hsw = mode->hsync_end - mode->hsync_start;
801 vbp = mode->vtotal - mode->vsync_end;
802 vfp = mode->vsync_start - mode->vdisplay;
803 vsw = mode->vsync_end - mode->vsync_start;
805 if ((hbp-1) & ~0x3ff) {
806 DBG("Pruning mode: Horizontal Back Porch out of range");
807 return MODE_HBLANK_WIDE;
810 if ((hfp-1) & ~0x3ff) {
811 DBG("Pruning mode: Horizontal Front Porch out of range");
812 return MODE_HBLANK_WIDE;
815 if ((hsw-1) & ~0x3ff) {
816 DBG("Pruning mode: Horizontal Sync Width out of range");
817 return MODE_HSYNC_WIDE;
821 DBG("Pruning mode: Vertical Back Porch out of range");
822 return MODE_VBLANK_WIDE;
826 DBG("Pruning mode: Vertical Front Porch out of range");
827 return MODE_VBLANK_WIDE;
830 if ((vsw-1) & ~0x3f) {
831 DBG("Pruning mode: Vertical Sync Width out of range");
832 return MODE_VSYNC_WIDE;
836 * some devices have a maximum allowed pixel clock
837 * configured from the DT
839 if (mode->clock > priv->max_pixelclock) {
840 DBG("Pruning mode: pixel clock too high");
841 return MODE_CLOCK_HIGH;
845 * some devices further limit the max horizontal resolution
846 * configured from the DT
848 if (mode->hdisplay > priv->max_width)
849 return MODE_BAD_WIDTH;
851 /* filter out modes that would require too much memory bandwidth: */
852 bandwidth = mode->hdisplay * mode->vdisplay *
853 drm_mode_vrefresh(mode);
854 if (bandwidth > priv->max_bandwidth) {
855 DBG("Pruning mode: exceeds defined bandwidth limit");
862 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
863 const struct tilcdc_panel_info *info)
865 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
866 tilcdc_crtc->info = info;
869 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
870 bool simulate_vesa_sync)
872 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
874 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
877 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
879 struct drm_device *dev = crtc->dev;
880 struct tilcdc_drm_private *priv = dev->dev_private;
881 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
883 drm_modeset_lock(&crtc->mutex, NULL);
884 if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
885 if (tilcdc_crtc_is_on(crtc)) {
886 pm_runtime_get_sync(dev->dev);
887 tilcdc_crtc_disable(crtc);
889 tilcdc_crtc_set_clk(crtc);
891 tilcdc_crtc_enable(crtc);
892 pm_runtime_put_sync(dev->dev);
895 drm_modeset_unlock(&crtc->mutex);
898 #define SYNC_LOST_COUNT_LIMIT 50
900 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
902 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
903 struct drm_device *dev = crtc->dev;
904 struct tilcdc_drm_private *priv = dev->dev_private;
907 stat = tilcdc_read_irqstatus(dev);
908 tilcdc_clear_irqstatus(dev, stat);
910 if (stat & LCDC_END_OF_FRAME0) {
912 bool skip_event = false;
917 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
919 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
921 tilcdc_crtc->last_vblank = now;
923 if (tilcdc_crtc->next_fb) {
924 set_scanout(crtc, tilcdc_crtc->next_fb);
925 tilcdc_crtc->next_fb = NULL;
929 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
931 drm_crtc_handle_vblank(crtc);
934 struct drm_pending_vblank_event *event;
936 spin_lock_irqsave(&dev->event_lock, flags);
938 event = tilcdc_crtc->event;
939 tilcdc_crtc->event = NULL;
941 drm_crtc_send_vblank_event(crtc, event);
943 spin_unlock_irqrestore(&dev->event_lock, flags);
946 if (tilcdc_crtc->frame_intact)
947 tilcdc_crtc->sync_lost_count = 0;
949 tilcdc_crtc->frame_intact = true;
952 if (stat & LCDC_FIFO_UNDERFLOW)
953 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
956 if (stat & LCDC_PL_LOAD_DONE) {
957 complete(&tilcdc_crtc->palette_loaded);
959 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
962 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
966 if (stat & LCDC_SYNC_LOST) {
967 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
969 tilcdc_crtc->frame_intact = false;
970 if (priv->rev == 1) {
971 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
972 if (reg & LCDC_RASTER_ENABLE) {
973 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
975 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
979 if (tilcdc_crtc->sync_lost_count++ >
980 SYNC_LOST_COUNT_LIMIT) {
982 "%s(0x%08x): Sync lost flood detected, recovering",
984 queue_work(system_wq,
985 &tilcdc_crtc->recover_work);
986 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
988 tilcdc_crtc->sync_lost_count = 0;
993 if (stat & LCDC_FRAME_DONE) {
994 tilcdc_crtc->frame_done = true;
995 wake_up(&tilcdc_crtc->frame_done_wq);
996 /* rev 1 lcdc appears to hang if irq is not disbaled here */
998 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
999 LCDC_V1_FRAME_DONE_INT_ENA);
1002 /* For revision 2 only */
1003 if (priv->rev == 2) {
1004 /* Indicate to LCDC that the interrupt service routine has
1005 * completed, see 13.3.6.1.6 in AM335x TRM.
1007 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
1013 int tilcdc_crtc_create(struct drm_device *dev)
1015 struct tilcdc_drm_private *priv = dev->dev_private;
1016 struct tilcdc_crtc *tilcdc_crtc;
1017 struct drm_crtc *crtc;
1020 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
1022 dev_err(dev->dev, "allocation failed\n");
1026 init_completion(&tilcdc_crtc->palette_loaded);
1027 tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
1028 TILCDC_PALETTE_SIZE,
1029 &tilcdc_crtc->palette_dma_handle,
1030 GFP_KERNEL | __GFP_ZERO);
1031 if (!tilcdc_crtc->palette_base)
1033 *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
1035 crtc = &tilcdc_crtc->base;
1037 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
1041 mutex_init(&tilcdc_crtc->enable_lock);
1043 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
1045 drm_flip_work_init(&tilcdc_crtc->unref_work,
1046 "unref", unref_worker);
1048 spin_lock_init(&tilcdc_crtc->irq_lock);
1049 INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1051 ret = drm_crtc_init_with_planes(dev, crtc,
1052 &tilcdc_crtc->primary,
1059 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1061 if (priv->is_componentized) {
1062 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);
1063 if (!crtc->port) { /* This should never happen */
1064 dev_err(dev->dev, "Port node not found in %pOF\n",
1075 tilcdc_crtc_destroy(crtc);