drivers/gpu/drm/tegra/hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/delay.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/math64.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/reset.h>
  18
  19 #include <soc/tegra/common.h>
  20 #include <sound/hdmi-codec.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_crtc.h>
  24 #include <drm/drm_debugfs.h>
  25 #include <drm/drm_file.h>
  26 #include <drm/drm_fourcc.h>
  27 #include <drm/drm_probe_helper.h>
  28 #include <drm/drm_simple_kms_helper.h>
  29
  30 #include "hda.h"
  31 #include "hdmi.h"
  32 #include "drm.h"
  33 #include "dc.h"
  34 #include "trace.h"
  35
  36 #define HDMI_ELD_BUFFER_SIZE 96
  37
  38 struct tmds_config {
  39         unsigned int pclk;
  40         u32 pll0;
  41         u32 pll1;
  42         u32 pe_current;
  43         u32 drive_current;
  44         u32 peak_current;
  45 };
  46
  47 struct tegra_hdmi_config {
  48         const struct tmds_config *tmds;
  49         unsigned int num_tmds;
  50
  51         unsigned long fuse_override_offset;
  52         u32 fuse_override_value;
  53
  54         bool has_sor_io_peak_current;
  55         bool has_hda;
  56         bool has_hbr;
  57 };
  58
  59 struct tegra_hdmi {
  60         struct host1x_client client;
  61         struct tegra_output output;
  62         struct device *dev;
  63
  64         struct regulator *hdmi;
  65         struct regulator *pll;
  66         struct regulator *vdd;
  67
  68         void __iomem *regs;
  69         unsigned int irq;
  70
  71         struct clk *clk_parent;
  72         struct clk *clk;
  73         struct reset_control *rst;
  74
  75         const struct tegra_hdmi_config *config;
  76
  77         unsigned int audio_source;
  78         struct tegra_hda_format format;
  79
  80         unsigned int pixel_clock;
  81         bool stereo;
  82         bool dvi;
  83
  84         struct drm_info_list *debugfs_files;
  85
  86         struct platform_device *audio_pdev;
  87         struct mutex audio_lock;
  88 };
  89
  90 static inline struct tegra_hdmi *
  91 host1x_client_to_hdmi(struct host1x_client *client)
  92 {
  93         return container_of(client, struct tegra_hdmi, client);
  94 }
  95
  96 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
  97 {
  98         return container_of(output, struct tegra_hdmi, output);
  99 }
 100
 101 #define HDMI_AUDIOCLK_FREQ 216000000
 102 #define HDMI_REKEY_DEFAULT 56
 103
 104 enum {
 105         AUTO = 0,
 106         SPDIF,
 107         HDA,
 108 };
 109
 110 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
 111                                    unsigned int offset)
 112 {
 113         u32 value = readl(hdmi->regs + (offset << 2));
 114
 115         trace_hdmi_readl(hdmi->dev, offset, value);
 116
 117         return value;
 118 }
 119
 120 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
 121                                      unsigned int offset)
 122 {
 123         trace_hdmi_writel(hdmi->dev, offset, value);
 124         writel(value, hdmi->regs + (offset << 2));
 125 }
 126
 127 struct tegra_hdmi_audio_config {
 128         unsigned int n;
 129         unsigned int cts;
 130         unsigned int aval;
 131 };
 132
 133 static const struct tmds_config tegra20_tmds_config[] = {
 134         { /* slow pixel clock modes */
 135                 .pclk = 27000000,
 136                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 137                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 138                         SOR_PLL_TX_REG_LOAD(3),
 139                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 140                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 141                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 142                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 143                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 144                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 145                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 146                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 147                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 148         },
 149         { /* high pixel clock modes */
 150                 .pclk = UINT_MAX,
 151                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 152                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 153                         SOR_PLL_TX_REG_LOAD(3),
 154                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 155                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
 156                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
 157                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
 158                         PE_CURRENT3(PE_CURRENT_6_0_mA),
 159                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 160                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 161                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 162                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 163         },
 164 };
 165
 166 static const struct tmds_config tegra30_tmds_config[] = {
 167         { /* 480p modes */
 168                 .pclk = 27000000,
 169                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 170                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 171                         SOR_PLL_TX_REG_LOAD(0),
 172                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 173                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 174                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 175                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 176                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 177                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 178                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 179                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 180                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 181         }, { /* 720p modes */
 182                 .pclk = 74250000,
 183                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 184                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 185                         SOR_PLL_TX_REG_LOAD(0),
 186                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 187                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 188                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 189                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 190                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 191                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 192                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 193                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 194                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 195         }, { /* 1080p modes */
 196                 .pclk = UINT_MAX,
 197                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 198                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
 199                         SOR_PLL_TX_REG_LOAD(0),
 200                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 201                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 202                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 203                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 204                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 205                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 206                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 207                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 208                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 209         },
 210 };
 211
 212 static const struct tmds_config tegra114_tmds_config[] = {
 213         { /* 480p/576p / 25.2MHz/27MHz modes */
 214                 .pclk = 27000000,
 215                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 216                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 217                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 218                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 219                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 220                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 221                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 222                 .drive_current =
 223                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 224                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 225                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 226                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 227                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 228                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 229                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 230                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 231         }, { /* 720p / 74.25MHz modes */
 232                 .pclk = 74250000,
 233                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 234                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 235                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 236                         SOR_PLL_TMDS_TERMADJ(0),
 237                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 238                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 239                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 240                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 241                 .drive_current =
 242                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 243                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 244                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 245                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 246                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 247                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 248                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 249                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 250         }, { /* 1080p / 148.5MHz modes */
 251                 .pclk = 148500000,
 252                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 253                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 254                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 255                         SOR_PLL_TMDS_TERMADJ(0),
 256                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 257                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 258                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 259                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 260                 .drive_current =
 261                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 262                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 263                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 264                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 265                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 266                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 267                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 268                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 269         }, { /* 225/297MHz modes */
 270                 .pclk = UINT_MAX,
 271                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 272                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 273                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 274                         | SOR_PLL_TMDS_TERM_ENABLE,
 275                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 276                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 277                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 278                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 279                 .drive_current =
 280                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 281                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 282                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 283                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 284                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 285                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 286                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 287                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 288         },
 289 };
 290
 291 static const struct tmds_config tegra124_tmds_config[] = {
 292         { /* 480p/576p / 25.2MHz/27MHz modes */
 293                 .pclk = 27000000,
 294                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 295                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 296                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 297                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 298                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 299                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 300                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 301                 .drive_current =
 302                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 303                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 304                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 305                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 306                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 307                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 308                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 309                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 310         }, { /* 720p / 74.25MHz modes */
 311                 .pclk = 74250000,
 312                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 313                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 314                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 315                         SOR_PLL_TMDS_TERMADJ(0),
 316                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 317                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 318                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 319                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 320                 .drive_current =
 321                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 322                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 323                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 324                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 325                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 326                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 327                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 328                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 329         }, { /* 1080p / 148.5MHz modes */
 330                 .pclk = 148500000,
 331                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 332                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 333                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 334                         SOR_PLL_TMDS_TERMADJ(0),
 335                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 336                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 337                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 338                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 339                 .drive_current =
 340                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 341                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 342                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 343                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 344                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 345                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 346                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 347                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 348         }, { /* 225/297MHz modes */
 349                 .pclk = UINT_MAX,
 350                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 351                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 352                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 353                         | SOR_PLL_TMDS_TERM_ENABLE,
 354                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 355                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 356                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 357                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 358                 .drive_current =
 359                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 360                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 361                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 362                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 363                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 364                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 365                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 366                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 367         },
 368 };
 369
 370 static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
 371 {
 372         mutex_lock(&hdmi->audio_lock);
 373         disable_irq(hdmi->irq);
 374 }
 375
 376 static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
 377 {
 378         enable_irq(hdmi->irq);
 379         mutex_unlock(&hdmi->audio_lock);
 380 }
 381
 382 static int
 383 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
 384                             struct tegra_hdmi_audio_config *config)
 385 {
 386         const unsigned int afreq = 128 * audio_freq;
 387         const unsigned int min_n = afreq / 1500;
 388         const unsigned int max_n = afreq / 300;
 389         const unsigned int ideal_n = afreq / 1000;
 390         int64_t min_err = (uint64_t)-1 >> 1;
 391         unsigned int min_delta = -1;
 392         int n;
 393
 394         memset(config, 0, sizeof(*config));
 395         config->n = -1;
 396
 397         for (n = min_n; n <= max_n; n++) {
 398                 uint64_t cts_f, aval_f;
 399                 unsigned int delta;
 400                 int64_t cts, err;
 401
 402                 /* compute aval in 48.16 fixed point */
 403                 aval_f = ((int64_t)24000000 << 16) * n;
 404                 do_div(aval_f, afreq);
 405                 /* It should round without any rest */
 406                 if (aval_f & 0xFFFF)
 407                         continue;
 408
 409                 /* Compute cts in 48.16 fixed point */
 410                 cts_f = ((int64_t)pix_clock << 16) * n;
 411                 do_div(cts_f, afreq);
 412                 /* Round it to the nearest integer */
 413                 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
 414
 415                 delta = abs(n - ideal_n);
 416
 417                 /* Compute the absolute error */
 418                 err = abs((int64_t)cts_f - cts);
 419                 if (err < min_err || (err == min_err && delta < min_delta)) {
 420                         config->n = n;
 421                         config->cts = cts >> 16;
 422                         config->aval = aval_f >> 16;
 423                         min_delta = delta;
 424                         min_err = err;
 425                 }
 426         }
 427
 428         return config->n != -1 ? 0 : -EINVAL;
 429 }
 430
 431 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
 432 {
 433         const unsigned int freqs[] = {
 434                 32000, 44100, 48000, 88200, 96000, 176400, 192000
 435         };
 436         unsigned int i;
 437
 438         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 439                 unsigned int f = freqs[i];
 440                 unsigned int eight_half;
 441                 unsigned int delta;
 442                 u32 value;
 443
 444                 if (f > 96000)
 445                         delta = 2;
 446                 else if (f > 48000)
 447                         delta = 6;
 448                 else
 449                         delta = 9;
 450
 451                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 452                 value = AUDIO_FS_LOW(eight_half - delta) |
 453                         AUDIO_FS_HIGH(eight_half + delta);
 454                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
 455         }
 456 }
 457
 458 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
 459 {
 460         static const struct {
 461                 unsigned int sample_rate;
 462                 unsigned int offset;
 463         } regs[] = {
 464                 {  32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
 465                 {  44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
 466                 {  48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
 467                 {  88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
 468                 {  96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
 469                 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
 470                 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
 471         };
 472         unsigned int i;
 473
 474         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 475                 if (regs[i].sample_rate == hdmi->format.sample_rate) {
 476                         tegra_hdmi_writel(hdmi, value, regs[i].offset);
 477                         break;
 478                 }
 479         }
 480 }
 481
 482 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
 483 {
 484         struct tegra_hdmi_audio_config config;
 485         u32 source, value;
 486         int err;
 487
 488         switch (hdmi->audio_source) {
 489         case HDA:
 490                 if (hdmi->config->has_hda)
 491                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
 492                 else
 493                         return -EINVAL;
 494
 495                 break;
 496
 497         case SPDIF:
 498                 if (hdmi->config->has_hda)
 499                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 500                 else
 501                         source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 502                 break;
 503
 504         default:
 505                 if (hdmi->config->has_hda)
 506                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 507                 else
 508                         source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 509                 break;
 510         }
 511
 512         /*
 513          * Tegra30 and later use a slightly modified version of the register
 514          * layout to accomodate for changes related to supporting HDA as the
 515          * audio input source for HDMI. The source select field has moved to
 516          * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
 517          * per block fields remain in the AUDIO_CNTRL0 register.
 518          */
 519         if (hdmi->config->has_hda) {
 520                 /*
 521                  * Inject null samples into the audio FIFO for every frame in
 522                  * which the codec did not receive any samples. This applies
 523                  * to stereo LPCM only.
 524                  *
 525                  * XXX: This seems to be a remnant of MCP days when this was
 526                  * used to work around issues with monitors not being able to
 527                  * play back system startup sounds early. It is possibly not
 528                  * needed on Linux at all.
 529                  */
 530                 if (hdmi->format.channels == 2)
 531                         value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
 532                 else
 533                         value = 0;
 534
 535                 value |= source;
 536
 537                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
 538         }
 539
 540         /*
 541          * On Tegra20, HDA is not a supported audio source and the source
 542          * select field is part of the AUDIO_CNTRL0 register.
 543          */
 544         value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 545                 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
 546
 547         if (!hdmi->config->has_hda)
 548                 value |= source;
 549
 550         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 551
 552         /*
 553          * Advertise support for High Bit-Rate on Tegra114 and later.
 554          */
 555         if (hdmi->config->has_hbr) {
 556                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 557                 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
 558                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 559         }
 560
 561         err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
 562                                           hdmi->pixel_clock, &config);
 563         if (err < 0) {
 564                 dev_err(hdmi->dev,
 565                         "cannot set audio to %u Hz at %u Hz pixel clock\n",
 566                         hdmi->format.sample_rate, hdmi->pixel_clock);
 567                 return err;
 568         }
 569
 570         dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
 571                 hdmi->pixel_clock, config.n, config.cts, config.aval);
 572
 573         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 574
 575         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
 576                 AUDIO_N_VALUE(config.n - 1);
 577         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 578
 579         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
 580                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 581
 582         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
 583                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 584
 585         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
 586         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
 587
 588         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
 589         value &= ~AUDIO_N_RESETF;
 590         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 591
 592         if (hdmi->config->has_hda)
 593                 tegra_hdmi_write_aval(hdmi, config.aval);
 594
 595         tegra_hdmi_setup_audio_fs_tables(hdmi);
 596
 597         return 0;
 598 }
 599
 600 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
 601 {
 602         u32 value;
 603
 604         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 605         value &= ~GENERIC_CTRL_AUDIO;
 606         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 607 }
 608
 609 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
 610 {
 611         u32 value;
 612
 613         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 614         value |= GENERIC_CTRL_AUDIO;
 615         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 616 }
 617
 618 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
 619 {
 620         size_t length = drm_eld_size(hdmi->output.connector.eld), i;
 621         u32 value;
 622
 623         for (i = 0; i < length; i++)
 624                 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
 625                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 626
 627         /*
 628          * The HDA codec will always report an ELD buffer size of 96 bytes and
 629          * the HDA codec driver will check that each byte read from the buffer
 630          * is valid. Therefore every byte must be written, even if no 96 bytes
 631          * were parsed from EDID.
 632          */
 633         for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
 634                 tegra_hdmi_writel(hdmi, i << 8 | 0,
 635                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 636
 637         value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
 638         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 639 }
 640
 641 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
 642 {
 643         u32 value = 0;
 644         size_t i;
 645
 646         for (i = size; i > 0; i--)
 647                 value = (value << 8) | ptr[i - 1];
 648
 649         return value;
 650 }
 651
 652 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
 653                                       size_t size)
 654 {
 655         const u8 *ptr = data;
 656         unsigned long offset;
 657         size_t i, j;
 658         u32 value;
 659
 660         switch (ptr[0]) {
 661         case HDMI_INFOFRAME_TYPE_AVI:
 662                 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
 663                 break;
 664
 665         case HDMI_INFOFRAME_TYPE_AUDIO:
 666                 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
 667                 break;
 668
 669         case HDMI_INFOFRAME_TYPE_VENDOR:
 670                 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
 671                 break;
 672
 673         default:
 674                 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
 675                         ptr[0]);
 676                 return;
 677         }
 678
 679         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
 680                 INFOFRAME_HEADER_VERSION(ptr[1]) |
 681                 INFOFRAME_HEADER_LEN(ptr[2]);
 682         tegra_hdmi_writel(hdmi, value, offset);
 683         offset++;
 684
 685         /*
 686          * Each subpack contains 7 bytes, divided into:
 687          * - subpack_low: bytes 0 - 3
 688          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
 689          */
 690         for (i = 3, j = 0; i < size; i += 7, j += 8) {
 691                 size_t rem = size - i, num = min_t(size_t, rem, 4);
 692
 693                 value = tegra_hdmi_subpack(&ptr[i], num);
 694                 tegra_hdmi_writel(hdmi, value, offset++);
 695
 696                 num = min_t(size_t, rem - num, 3);
 697
 698                 value = tegra_hdmi_subpack(&ptr[i + 4], num);
 699                 tegra_hdmi_writel(hdmi, value, offset++);
 700         }
 701 }
 702
 703 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
 704                                            struct drm_display_mode *mode)
 705 {
 706         struct hdmi_avi_infoframe frame;
 707         u8 buffer[17];
 708         ssize_t err;
 709
 710         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 711                                                        &hdmi->output.connector, mode);
 712         if (err < 0) {
 713                 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
 714                 return;
 715         }
 716
 717         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 718         if (err < 0) {
 719                 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
 720                 return;
 721         }
 722
 723         tegra_hdmi_write_infopack(hdmi, buffer, err);
 724 }
 725
 726 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
 727 {
 728         u32 value;
 729
 730         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 731         value &= ~INFOFRAME_CTRL_ENABLE;
 732         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 733 }
 734
 735 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
 736 {
 737         u32 value;
 738
 739         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 740         value |= INFOFRAME_CTRL_ENABLE;
 741         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 742 }
 743
 744 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
 745 {
 746         struct hdmi_audio_infoframe frame;
 747         u8 buffer[14];
 748         ssize_t err;
 749
 750         err = hdmi_audio_infoframe_init(&frame);
 751         if (err < 0) {
 752                 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
 753                         err);
 754                 return;
 755         }
 756
 757         frame.channels = hdmi->format.channels;
 758
 759         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 760         if (err < 0) {
 761                 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
 762                         err);
 763                 return;
 764         }
 765
 766         /*
 767          * The audio infoframe has only one set of subpack registers, so the
 768          * infoframe needs to be truncated. One set of subpack registers can
 769          * contain 7 bytes. Including the 3 byte header only the first 10
 770          * bytes can be programmed.
 771          */
 772         tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
 773 }
 774
 775 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
 776 {
 777         u32 value;
 778
 779         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 780         value &= ~INFOFRAME_CTRL_ENABLE;
 781         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 782 }
 783
 784 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
 785 {
 786         u32 value;
 787
 788         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 789         value |= INFOFRAME_CTRL_ENABLE;
 790         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 791 }
 792
 793 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
 794 {
 795         struct hdmi_vendor_infoframe frame;
 796         u8 buffer[10];
 797         ssize_t err;
 798
 799         hdmi_vendor_infoframe_init(&frame);
 800         frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
 801
 802         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
 803         if (err < 0) {
 804                 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
 805                         err);
 806                 return;
 807         }
 808
 809         tegra_hdmi_write_infopack(hdmi, buffer, err);
 810 }
 811
 812 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
 813 {
 814         u32 value;
 815
 816         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 817         value &= ~GENERIC_CTRL_ENABLE;
 818         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 819 }
 820
 821 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
 822 {
 823         u32 value;
 824
 825         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 826         value |= GENERIC_CTRL_ENABLE;
 827         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 828 }
 829
 830 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 831                                   const struct tmds_config *tmds)
 832 {
 833         u32 value;
 834
 835         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
 836         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
 837         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
 838
 839         tegra_hdmi_writel(hdmi, tmds->drive_current,
 840                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 841
 842         value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
 843         value |= hdmi->config->fuse_override_value;
 844         tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
 845
 846         if (hdmi->config->has_sor_io_peak_current)
 847                 tegra_hdmi_writel(hdmi, tmds->peak_current,
 848                                   HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
 849 }
 850
 851 static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
 852 {
 853         int err;
 854
 855         err = tegra_hdmi_setup_audio(hdmi);
 856         if (err < 0) {
 857                 tegra_hdmi_disable_audio_infoframe(hdmi);
 858                 tegra_hdmi_disable_audio(hdmi);
 859         } else {
 860                 tegra_hdmi_setup_audio_infoframe(hdmi);
 861                 tegra_hdmi_enable_audio_infoframe(hdmi);
 862                 tegra_hdmi_enable_audio(hdmi);
 863         }
 864
 865         return err;
 866 }
 867
 868 static bool tegra_output_is_hdmi(struct tegra_output *output)
 869 {
 870         struct edid *edid;
 871
 872         if (!output->connector.edid_blob_ptr)
 873                 return false;
 874
 875         edid = (struct edid *)output->connector.edid_blob_ptr->data;
 876
 877         return drm_detect_hdmi_monitor(edid);
 878 }
 879
 880 static enum drm_connector_status
 881 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
 882 {
 883         struct tegra_output *output = connector_to_output(connector);
 884         struct tegra_hdmi *hdmi = to_hdmi(output);
 885         enum drm_connector_status status;
 886
 887         status = tegra_output_connector_detect(connector, force);
 888         if (status == connector_status_connected)
 889                 return status;
 890
 891         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 892         return status;
 893 }
 894
 895 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
 896
 897 static const struct debugfs_reg32 tegra_hdmi_regs[] = {
 898         DEBUGFS_REG32(HDMI_CTXSW),
 899         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
 900         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
 901         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
 902         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
 903         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
 904         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
 905         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
 906         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
 907         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
 908         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
 909         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
 910         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
 911         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
 912         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
 913         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
 914         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
 915         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
 916         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
 917         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
 918         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
 919         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
 920         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
 921         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
 922         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
 923         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
 924         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
 925         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
 926         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
 927         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
 928         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
 929         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
 930         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
 931         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
 932         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
 933         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
 934         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
 935         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
 936         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
 937         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
 938         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
 939         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
 940         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
 941         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
 942         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
 943         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
 944         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
 945         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
 946         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
 947         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
 948         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
 949         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
 950         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
 951         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
 952         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
 953         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
 954         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
 955         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
 956         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
 957         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
 958         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
 959         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
 960         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
 961         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
 962         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
 963         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
 964         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
 965         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
 966         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
 967         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
 968         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
 969         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
 970         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
 971         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
 972         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
 973         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
 974         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
 975         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
 976         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
 977         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
 978         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
 979         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
 980         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
 981         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
 982         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
 983         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
 984         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
 985         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
 986         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
 987         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
 988         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
 989         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
 990         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
 991         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
 992         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
 993         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
 994         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
 995         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
 996         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
 997         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
 998         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
 999         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
1000         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
1001         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
1002         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
1003         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1004         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1005         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1006         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1007         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1008         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1009         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1010         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1011         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1012         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1013         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1014         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1015         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1016         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1017         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1018         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1019         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1020         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1021         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1022         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1023         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1024         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1025         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1026         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1027         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1028         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1029         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1030         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1031         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1032         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1033         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1034         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1035         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1036         DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1037         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1038         DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1039         DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1040         DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1041         DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1042         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1043         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1044         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1045         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1046         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1047         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1048         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1049         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1050         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1051         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1052         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1053         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1054         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1055         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1056         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1057         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1058         DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1059         DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1060         DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1061         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1062 };
1063
1064 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1065 {
1066         struct drm_info_node *node = s->private;
1067         struct tegra_hdmi *hdmi = node->info_ent->data;
1068         struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1069         struct drm_device *drm = node->minor->dev;
1070         unsigned int i;
1071         int err = 0;
1072
1073         drm_modeset_lock_all(drm);
1074
1075         if (!crtc || !crtc->state->active) {
1076                 err = -EBUSY;
1077                 goto unlock;
1078         }
1079
1080         for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1081                 unsigned int offset = tegra_hdmi_regs[i].offset;
1082
1083                 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1084                            offset, tegra_hdmi_readl(hdmi, offset));
1085         }
1086
1087 unlock:
1088         drm_modeset_unlock_all(drm);
1089         return err;
1090 }
1091
1092 static struct drm_info_list debugfs_files[] = {
1093         { "regs", tegra_hdmi_show_regs, 0, NULL },
1094 };
1095
1096 static int tegra_hdmi_late_register(struct drm_connector *connector)
1097 {
1098         struct tegra_output *output = connector_to_output(connector);
1099         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1100         struct drm_minor *minor = connector->dev->primary;
1101         struct dentry *root = connector->debugfs_entry;
1102         struct tegra_hdmi *hdmi = to_hdmi(output);
1103
1104         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1105                                       GFP_KERNEL);
1106         if (!hdmi->debugfs_files)
1107                 return -ENOMEM;
1108
1109         for (i = 0; i < count; i++)
1110                 hdmi->debugfs_files[i].data = hdmi;
1111
1112         drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1113
1114         return 0;
1115 }
1116
1117 static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1118 {
1119         struct tegra_output *output = connector_to_output(connector);
1120         struct drm_minor *minor = connector->dev->primary;
1121         unsigned int count = ARRAY_SIZE(debugfs_files);
1122         struct tegra_hdmi *hdmi = to_hdmi(output);
1123
1124         drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1125         kfree(hdmi->debugfs_files);
1126         hdmi->debugfs_files = NULL;
1127 }
1128
1129 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1130         .reset = drm_atomic_helper_connector_reset,
1131         .detect = tegra_hdmi_connector_detect,
1132         .fill_modes = drm_helper_probe_single_connector_modes,
1133         .destroy = tegra_output_connector_destroy,
1134         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1135         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1136         .late_register = tegra_hdmi_late_register,
1137         .early_unregister = tegra_hdmi_early_unregister,
1138 };
1139
1140 static enum drm_mode_status
1141 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1142                                 struct drm_display_mode *mode)
1143 {
1144         struct tegra_output *output = connector_to_output(connector);
1145         struct tegra_hdmi *hdmi = to_hdmi(output);
1146         unsigned long pclk = mode->clock * 1000;
1147         enum drm_mode_status status = MODE_OK;
1148         struct clk *parent;
1149         long err;
1150
1151         parent = clk_get_parent(hdmi->clk_parent);
1152
1153         err = clk_round_rate(parent, pclk * 4);
1154         if (err <= 0)
1155                 status = MODE_NOCLOCK;
1156
1157         return status;
1158 }
1159
1160 static const struct drm_connector_helper_funcs
1161 tegra_hdmi_connector_helper_funcs = {
1162         .get_modes = tegra_output_connector_get_modes,
1163         .mode_valid = tegra_hdmi_connector_mode_valid,
1164 };
1165
1166 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1167 {
1168         struct tegra_output *output = encoder_to_output(encoder);
1169         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1170         struct tegra_hdmi *hdmi = to_hdmi(output);
1171         u32 value;
1172         int err;
1173
1174         tegra_hdmi_audio_lock(hdmi);
1175
1176         /*
1177          * The following accesses registers of the display controller, so make
1178          * sure it's only executed when the output is attached to one.
1179          */
1180         if (dc) {
1181                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1182                 value &= ~HDMI_ENABLE;
1183                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1184
1185                 tegra_dc_commit(dc);
1186         }
1187
1188         if (!hdmi->dvi) {
1189                 if (hdmi->stereo)
1190                         tegra_hdmi_disable_stereo_infoframe(hdmi);
1191
1192                 tegra_hdmi_disable_audio_infoframe(hdmi);
1193                 tegra_hdmi_disable_avi_infoframe(hdmi);
1194                 tegra_hdmi_disable_audio(hdmi);
1195         }
1196
1197         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1198         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1199
1200         hdmi->pixel_clock = 0;
1201
1202         tegra_hdmi_audio_unlock(hdmi);
1203
1204         err = host1x_client_suspend(&hdmi->client);
1205         if (err < 0)
1206                 dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1207 }
1208
1209 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1210 {
1211         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1212         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1213         struct tegra_output *output = encoder_to_output(encoder);
1214         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1215         struct tegra_hdmi *hdmi = to_hdmi(output);
1216         unsigned int pulse_start, div82;
1217         int retries = 1000;
1218         u32 value;
1219         int err;
1220
1221         err = host1x_client_resume(&hdmi->client);
1222         if (err < 0) {
1223                 dev_err(hdmi->dev, "failed to resume: %d\n", err);
1224                 return;
1225         }
1226
1227         tegra_hdmi_audio_lock(hdmi);
1228
1229         /*
1230          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1231          * is used for interoperability between the HDA codec driver and the
1232          * HDMI driver.
1233          */
1234         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1235         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1236
1237         hdmi->pixel_clock = mode->clock * 1000;
1238         h_sync_width = mode->hsync_end - mode->hsync_start;
1239         h_back_porch = mode->htotal - mode->hsync_end;
1240         h_front_porch = mode->hsync_start - mode->hdisplay;
1241
1242         err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1243         if (err < 0) {
1244                 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1245                         err);
1246         }
1247
1248         DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1249
1250         /* power up sequence */
1251         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1252         value &= ~SOR_PLL_PDBG;
1253         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1254
1255         usleep_range(10, 20);
1256
1257         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1258         value &= ~SOR_PLL_PWR;
1259         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1260
1261         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1262                         DC_DISP_DISP_TIMING_OPTIONS);
1263         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1264                         DC_DISP_DISP_COLOR_CONTROL);
1265
1266         /* video_preamble uses h_pulse2 */
1267         pulse_start = 1 + h_sync_width + h_back_porch - 10;
1268
1269         tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1270
1271         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1272                 PULSE_LAST_END_A;
1273         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1274
1275         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1276         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1277
1278         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1279                 VSYNC_WINDOW_ENABLE;
1280         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1281
1282         if (dc->pipe)
1283                 value = HDMI_SRC_DISPLAYB;
1284         else
1285                 value = HDMI_SRC_DISPLAYA;
1286
1287         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1288                                         (mode->vdisplay == 576)))
1289                 tegra_hdmi_writel(hdmi,
1290                                   value | ARM_VIDEO_RANGE_FULL,
1291                                   HDMI_NV_PDISP_INPUT_CONTROL);
1292         else
1293                 tegra_hdmi_writel(hdmi,
1294                                   value | ARM_VIDEO_RANGE_LIMITED,
1295                                   HDMI_NV_PDISP_INPUT_CONTROL);
1296
1297         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1298         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1299         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1300
1301         hdmi->dvi = !tegra_output_is_hdmi(output);
1302         if (!hdmi->dvi) {
1303                 /*
1304                  * Make sure that the audio format has been configured before
1305                  * enabling audio, otherwise we may try to divide by zero.
1306                 */
1307                 if (hdmi->format.sample_rate > 0) {
1308                         err = tegra_hdmi_setup_audio(hdmi);
1309                         if (err < 0)
1310                                 hdmi->dvi = true;
1311                 }
1312         }
1313
1314         if (hdmi->config->has_hda)
1315                 tegra_hdmi_write_eld(hdmi);
1316
1317         rekey = HDMI_REKEY_DEFAULT;
1318         value = HDMI_CTRL_REKEY(rekey);
1319         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1320                                           h_front_porch - rekey - 18) / 32);
1321
1322         if (!hdmi->dvi)
1323                 value |= HDMI_CTRL_ENABLE;
1324
1325         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1326
1327         if (!hdmi->dvi) {
1328                 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1329                 tegra_hdmi_setup_audio_infoframe(hdmi);
1330
1331                 if (hdmi->stereo)
1332                         tegra_hdmi_setup_stereo_infoframe(hdmi);
1333         }
1334
1335         /* TMDS CONFIG */
1336         for (i = 0; i < hdmi->config->num_tmds; i++) {
1337                 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1338                         tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1339                         break;
1340                 }
1341         }
1342
1343         tegra_hdmi_writel(hdmi,
1344                           SOR_SEQ_PU_PC(0) |
1345                           SOR_SEQ_PU_PC_ALT(0) |
1346                           SOR_SEQ_PD_PC(8) |
1347                           SOR_SEQ_PD_PC_ALT(8),
1348                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1349
1350         value = SOR_SEQ_INST_WAIT_TIME(1) |
1351                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1352                 SOR_SEQ_INST_HALT |
1353                 SOR_SEQ_INST_PIN_A_LOW |
1354                 SOR_SEQ_INST_PIN_B_LOW |
1355                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1356
1357         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1358         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1359
1360         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1361         value &= ~SOR_CSTM_ROTCLK(~0);
1362         value |= SOR_CSTM_ROTCLK(2);
1363         value |= SOR_CSTM_PLLDIV;
1364         value &= ~SOR_CSTM_LVDS_ENABLE;
1365         value &= ~SOR_CSTM_MODE_MASK;
1366         value |= SOR_CSTM_MODE_TMDS;
1367         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1368
1369         /* start SOR */
1370         tegra_hdmi_writel(hdmi,
1371                           SOR_PWR_NORMAL_STATE_PU |
1372                           SOR_PWR_NORMAL_START_NORMAL |
1373                           SOR_PWR_SAFE_STATE_PD |
1374                           SOR_PWR_SETTING_NEW_TRIGGER,
1375                           HDMI_NV_PDISP_SOR_PWR);
1376         tegra_hdmi_writel(hdmi,
1377                           SOR_PWR_NORMAL_STATE_PU |
1378                           SOR_PWR_NORMAL_START_NORMAL |
1379                           SOR_PWR_SAFE_STATE_PD |
1380                           SOR_PWR_SETTING_NEW_DONE,
1381                           HDMI_NV_PDISP_SOR_PWR);
1382
1383         do {
1384                 BUG_ON(--retries < 0);
1385                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1386         } while (value & SOR_PWR_SETTING_NEW_PENDING);
1387
1388         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1389                 SOR_STATE_ASY_OWNER_HEAD0 |
1390                 SOR_STATE_ASY_SUBOWNER_BOTH |
1391                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1392                 SOR_STATE_ASY_DEPOL_POS;
1393
1394         /* setup sync polarities */
1395         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1396                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1397
1398         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1399                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1400
1401         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1402                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1403
1404         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1405                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1406
1407         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1408
1409         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1410         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1411
1412         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1413         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1414         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1415                           HDMI_NV_PDISP_SOR_STATE1);
1416         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1417
1418         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1419         value |= HDMI_ENABLE;
1420         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1421
1422         tegra_dc_commit(dc);
1423
1424         if (!hdmi->dvi) {
1425                 tegra_hdmi_enable_avi_infoframe(hdmi);
1426                 tegra_hdmi_enable_audio_infoframe(hdmi);
1427                 tegra_hdmi_enable_audio(hdmi);
1428
1429                 if (hdmi->stereo)
1430                         tegra_hdmi_enable_stereo_infoframe(hdmi);
1431         }
1432
1433         /* TODO: add HDCP support */
1434
1435         tegra_hdmi_audio_unlock(hdmi);
1436 }
1437
1438 static int
1439 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1440                                 struct drm_crtc_state *crtc_state,
1441                                 struct drm_connector_state *conn_state)
1442 {
1443         struct tegra_output *output = encoder_to_output(encoder);
1444         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1445         unsigned long pclk = crtc_state->mode.clock * 1000;
1446         struct tegra_hdmi *hdmi = to_hdmi(output);
1447         int err;
1448
1449         err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1450                                          pclk, 0);
1451         if (err < 0) {
1452                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1453                 return err;
1454         }
1455
1456         return err;
1457 }
1458
1459 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1460         .disable = tegra_hdmi_encoder_disable,
1461         .enable = tegra_hdmi_encoder_enable,
1462         .atomic_check = tegra_hdmi_encoder_atomic_check,
1463 };
1464
1465 static int tegra_hdmi_hw_params(struct device *dev, void *data,
1466                                 struct hdmi_codec_daifmt *fmt,
1467                                 struct hdmi_codec_params *hparms)
1468 {
1469         struct tegra_hdmi *hdmi = data;
1470         int ret = 0;
1471
1472         tegra_hdmi_audio_lock(hdmi);
1473
1474         hdmi->format.sample_rate = hparms->sample_rate;
1475         hdmi->format.channels = hparms->channels;
1476
1477         if (hdmi->pixel_clock && !hdmi->dvi)
1478                 ret = tegra_hdmi_reconfigure_audio(hdmi);
1479
1480         tegra_hdmi_audio_unlock(hdmi);
1481
1482         return ret;
1483 }
1484
1485 static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1486 {
1487         struct tegra_hdmi *hdmi = data;
1488         int ret;
1489
1490         ret = host1x_client_resume(&hdmi->client);
1491         if (ret < 0)
1492                 dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1493
1494         return ret;
1495 }
1496
1497 static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1498 {
1499         struct tegra_hdmi *hdmi = data;
1500         int ret;
1501
1502         tegra_hdmi_audio_lock(hdmi);
1503
1504         hdmi->format.sample_rate = 0;
1505         hdmi->format.channels = 0;
1506
1507         tegra_hdmi_audio_unlock(hdmi);
1508
1509         ret = host1x_client_suspend(&hdmi->client);
1510         if (ret < 0)
1511                 dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1512 }
1513
1514 static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1515         .hw_params = tegra_hdmi_hw_params,
1516         .audio_startup = tegra_hdmi_audio_startup,
1517         .audio_shutdown = tegra_hdmi_audio_shutdown,
1518 };
1519
1520 static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1521 {
1522         struct hdmi_codec_pdata codec_data = {};
1523
1524         if (hdmi->config->has_hda)
1525                 return 0;
1526
1527         codec_data.ops = &tegra_hdmi_codec_ops;
1528         codec_data.data = hdmi;
1529         codec_data.spdif = 1;
1530
1531         hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1532                                                          HDMI_CODEC_DRV_NAME,
1533                                                          PLATFORM_DEVID_AUTO,
1534                                                          &codec_data,
1535                                                          sizeof(codec_data));
1536         if (IS_ERR(hdmi->audio_pdev))
1537                 return PTR_ERR(hdmi->audio_pdev);
1538
1539         hdmi->format.channels = 2;
1540
1541         return 0;
1542 }
1543
1544 static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1545 {
1546         if (hdmi->audio_pdev)
1547                 platform_device_unregister(hdmi->audio_pdev);
1548 }
1549
1550 static int tegra_hdmi_init(struct host1x_client *client)
1551 {
1552         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1553         struct drm_device *drm = dev_get_drvdata(client->host);
1554         int err;
1555
1556         hdmi->output.dev = client->dev;
1557
1558         drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1559                                     &tegra_hdmi_connector_funcs,
1560                                     DRM_MODE_CONNECTOR_HDMIA,
1561                                     hdmi->output.ddc);
1562         drm_connector_helper_add(&hdmi->output.connector,
1563                                  &tegra_hdmi_connector_helper_funcs);
1564         hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1565
1566         drm_simple_encoder_init(drm, &hdmi->output.encoder,
1567                                 DRM_MODE_ENCODER_TMDS);
1568         drm_encoder_helper_add(&hdmi->output.encoder,
1569                                &tegra_hdmi_encoder_helper_funcs);
1570
1571         drm_connector_attach_encoder(&hdmi->output.connector,
1572                                           &hdmi->output.encoder);
1573         drm_connector_register(&hdmi->output.connector);
1574
1575         err = tegra_output_init(drm, &hdmi->output);
1576         if (err < 0) {
1577                 dev_err(client->dev, "failed to initialize output: %d\n", err);
1578                 return err;
1579         }
1580
1581         hdmi->output.encoder.possible_crtcs = 0x3;
1582
1583         err = regulator_enable(hdmi->hdmi);
1584         if (err < 0) {
1585                 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1586                         err);
1587                 goto output_exit;
1588         }
1589
1590         err = regulator_enable(hdmi->pll);
1591         if (err < 0) {
1592                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1593                 goto disable_hdmi;
1594         }
1595
1596         err = regulator_enable(hdmi->vdd);
1597         if (err < 0) {
1598                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1599                 goto disable_pll;
1600         }
1601
1602         err = tegra_hdmi_codec_register(hdmi);
1603         if (err < 0) {
1604                 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1605                 goto disable_vdd;
1606         }
1607
1608         return 0;
1609
1610 disable_vdd:
1611         regulator_disable(hdmi->vdd);
1612 disable_pll:
1613         regulator_disable(hdmi->pll);
1614 disable_hdmi:
1615         regulator_disable(hdmi->hdmi);
1616 output_exit:
1617         tegra_output_exit(&hdmi->output);
1618
1619         return err;
1620 }
1621
1622 static int tegra_hdmi_exit(struct host1x_client *client)
1623 {
1624         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1625
1626         tegra_hdmi_codec_unregister(hdmi);
1627
1628         tegra_output_exit(&hdmi->output);
1629
1630         regulator_disable(hdmi->vdd);
1631         regulator_disable(hdmi->pll);
1632         regulator_disable(hdmi->hdmi);
1633
1634         return 0;
1635 }
1636
1637 static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1638 {
1639         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1640         struct device *dev = client->dev;
1641         int err;
1642
1643         err = reset_control_assert(hdmi->rst);
1644         if (err < 0) {
1645                 dev_err(dev, "failed to assert reset: %d\n", err);
1646                 return err;
1647         }
1648
1649         usleep_range(1000, 2000);
1650
1651         clk_disable_unprepare(hdmi->clk);
1652         pm_runtime_put_sync(dev);
1653
1654         return 0;
1655 }
1656
1657 static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1658 {
1659         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1660         struct device *dev = client->dev;
1661         int err;
1662
1663         err = pm_runtime_resume_and_get(dev);
1664         if (err < 0) {
1665                 dev_err(dev, "failed to get runtime PM: %d\n", err);
1666                 return err;
1667         }
1668
1669         err = clk_prepare_enable(hdmi->clk);
1670         if (err < 0) {
1671                 dev_err(dev, "failed to enable clock: %d\n", err);
1672                 goto put_rpm;
1673         }
1674
1675         usleep_range(1000, 2000);
1676
1677         err = reset_control_deassert(hdmi->rst);
1678         if (err < 0) {
1679                 dev_err(dev, "failed to deassert reset: %d\n", err);
1680                 goto disable_clk;
1681         }
1682
1683         return 0;
1684
1685 disable_clk:
1686         clk_disable_unprepare(hdmi->clk);
1687 put_rpm:
1688         pm_runtime_put_sync(dev);
1689         return err;
1690 }
1691
1692 static const struct host1x_client_ops hdmi_client_ops = {
1693         .init = tegra_hdmi_init,
1694         .exit = tegra_hdmi_exit,
1695         .suspend = tegra_hdmi_runtime_suspend,
1696         .resume = tegra_hdmi_runtime_resume,
1697 };
1698
1699 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1700         .tmds = tegra20_tmds_config,
1701         .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1702         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1703         .fuse_override_value = 1 << 31,
1704         .has_sor_io_peak_current = false,
1705         .has_hda = false,
1706         .has_hbr = false,
1707 };
1708
1709 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1710         .tmds = tegra30_tmds_config,
1711         .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1712         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1713         .fuse_override_value = 1 << 31,
1714         .has_sor_io_peak_current = false,
1715         .has_hda = true,
1716         .has_hbr = false,
1717 };
1718
1719 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1720         .tmds = tegra114_tmds_config,
1721         .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1722         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1723         .fuse_override_value = 1 << 31,
1724         .has_sor_io_peak_current = true,
1725         .has_hda = true,
1726         .has_hbr = true,
1727 };
1728
1729 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1730         .tmds = tegra124_tmds_config,
1731         .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1732         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1733         .fuse_override_value = 1 << 31,
1734         .has_sor_io_peak_current = true,
1735         .has_hda = true,
1736         .has_hbr = true,
1737 };
1738
1739 static const struct of_device_id tegra_hdmi_of_match[] = {
1740         { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1741         { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1742         { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1743         { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1744         { },
1745 };
1746 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1747
1748 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1749 {
1750         struct tegra_hdmi *hdmi = data;
1751         u32 value;
1752
1753         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1754         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1755
1756         if (value & INT_CODEC_SCRATCH0) {
1757                 unsigned int format;
1758                 u32 value;
1759
1760                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1761
1762                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1763                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1764
1765                         tegra_hda_parse_format(format, &hdmi->format);
1766                         tegra_hdmi_reconfigure_audio(hdmi);
1767                 } else {
1768                         tegra_hdmi_disable_audio_infoframe(hdmi);
1769                         tegra_hdmi_disable_audio(hdmi);
1770                 }
1771         }
1772
1773         return IRQ_HANDLED;
1774 }
1775
1776 static int tegra_hdmi_probe(struct platform_device *pdev)
1777 {
1778         struct tegra_hdmi *hdmi;
1779         struct resource *regs;
1780         int err;
1781
1782         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1783         if (!hdmi)
1784                 return -ENOMEM;
1785
1786         hdmi->config = of_device_get_match_data(&pdev->dev);
1787         hdmi->dev = &pdev->dev;
1788
1789         hdmi->audio_source = AUTO;
1790         hdmi->stereo = false;
1791         hdmi->dvi = false;
1792
1793         mutex_init(&hdmi->audio_lock);
1794
1795         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1796         if (IS_ERR(hdmi->clk)) {
1797                 dev_err(&pdev->dev, "failed to get clock\n");
1798                 return PTR_ERR(hdmi->clk);
1799         }
1800
1801         hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1802         if (IS_ERR(hdmi->rst)) {
1803                 dev_err(&pdev->dev, "failed to get reset\n");
1804                 return PTR_ERR(hdmi->rst);
1805         }
1806
1807         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1808         if (IS_ERR(hdmi->clk_parent))
1809                 return PTR_ERR(hdmi->clk_parent);
1810
1811         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1812         if (err < 0) {
1813                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1814                 return err;
1815         }
1816
1817         hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1818         err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1819         if (err)
1820                 return dev_err_probe(&pdev->dev, err,
1821                                      "failed to get HDMI regulator\n");
1822
1823         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1824         err = PTR_ERR_OR_ZERO(hdmi->pll);
1825         if (err)
1826                 return dev_err_probe(&pdev->dev, err,
1827                                      "failed to get PLL regulator\n");
1828
1829         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1830         err = PTR_ERR_OR_ZERO(hdmi->vdd);
1831         if (err)
1832                 return dev_err_probe(&pdev->dev, err,
1833                                      "failed to get VDD regulator\n");
1834
1835         hdmi->output.dev = &pdev->dev;
1836
1837         err = tegra_output_probe(&hdmi->output);
1838         if (err < 0)
1839                 return err;
1840
1841         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1842         hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1843         if (IS_ERR(hdmi->regs))
1844                 return PTR_ERR(hdmi->regs);
1845
1846         err = platform_get_irq(pdev, 0);
1847         if (err < 0)
1848                 return err;
1849
1850         hdmi->irq = err;
1851
1852         err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1853                                dev_name(hdmi->dev), hdmi);
1854         if (err < 0) {
1855                 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1856                         hdmi->irq, err);
1857                 return err;
1858         }
1859
1860         platform_set_drvdata(pdev, hdmi);
1861
1862         err = devm_pm_runtime_enable(&pdev->dev);
1863         if (err)
1864                 return err;
1865
1866         err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1867         if (err)
1868                 return err;
1869
1870         INIT_LIST_HEAD(&hdmi->client.list);
1871         hdmi->client.ops = &hdmi_client_ops;
1872         hdmi->client.dev = &pdev->dev;
1873
1874         err = host1x_client_register(&hdmi->client);
1875         if (err < 0) {
1876                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1877                         err);
1878                 return err;
1879         }
1880
1881         return 0;
1882 }
1883
1884 static int tegra_hdmi_remove(struct platform_device *pdev)
1885 {
1886         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1887         int err;
1888
1889         err = host1x_client_unregister(&hdmi->client);
1890         if (err < 0) {
1891                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1892                         err);
1893                 return err;
1894         }
1895
1896         tegra_output_remove(&hdmi->output);
1897
1898         return 0;
1899 }
1900
1901 struct platform_driver tegra_hdmi_driver = {
1902         .driver = {
1903                 .name = "tegra-hdmi",
1904                 .of_match_table = tegra_hdmi_of_match,
1905         },
1906         .probe = tegra_hdmi_probe,
1907         .remove = tegra_hdmi_remove,
1908 };